1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * STMicroelectronics STM32 USB PHY Controller driver
4  *
5  * Copyright (C) 2018 STMicroelectronics
6  * Author(s): Amelie Delaunay <amelie.delaunay@st.com>.
7  */
8 #include <linux/bitfield.h>
9 #include <linux/clk.h>
10 #include <linux/clk-provider.h>
11 #include <linux/delay.h>
12 #include <linux/iopoll.h>
13 #include <linux/kernel.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/reset.h>
19 #include <linux/units.h>
20 
21 #define STM32_USBPHYC_PLL	0x0
22 #define STM32_USBPHYC_MISC	0x8
23 #define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100))
24 #define STM32_USBPHYC_TUNE(X)	(0x10C + ((X) * 0x100))
25 #define STM32_USBPHYC_VERSION	0x3F4
26 
27 /* STM32_USBPHYC_PLL bit fields */
28 #define PLLNDIV			GENMASK(6, 0)
29 #define PLLFRACIN		GENMASK(25, 10)
30 #define PLLEN			BIT(26)
31 #define PLLSTRB			BIT(27)
32 #define PLLSTRBYP		BIT(28)
33 #define PLLFRACCTL		BIT(29)
34 #define PLLDITHEN0		BIT(30)
35 #define PLLDITHEN1		BIT(31)
36 
37 /* STM32_USBPHYC_MISC bit fields */
38 #define SWITHOST		BIT(0)
39 
40 /* STM32_USBPHYC_MONITOR bit fields */
41 #define STM32_USBPHYC_MON_OUT	GENMASK(3, 0)
42 #define STM32_USBPHYC_MON_SEL	GENMASK(8, 4)
43 #define STM32_USBPHYC_MON_SEL_LOCKP 0x1F
44 #define STM32_USBPHYC_MON_OUT_LOCKP BIT(3)
45 
46 /* STM32_USBPHYC_TUNE bit fields */
47 #define INCURREN		BIT(0)
48 #define INCURRINT		BIT(1)
49 #define LFSCAPEN		BIT(2)
50 #define HSDRVSLEW		BIT(3)
51 #define HSDRVDCCUR		BIT(4)
52 #define HSDRVDCLEV		BIT(5)
53 #define HSDRVCURINCR		BIT(6)
54 #define FSDRVRFADJ		BIT(7)
55 #define HSDRVRFRED		BIT(8)
56 #define HSDRVCHKITRM		GENMASK(12, 9)
57 #define HSDRVCHKZTRM		GENMASK(14, 13)
58 #define OTPCOMP			GENMASK(19, 15)
59 #define SQLCHCTL		GENMASK(21, 20)
60 #define HDRXGNEQEN		BIT(22)
61 #define HSRXOFF			GENMASK(24, 23)
62 #define HSFALLPREEM		BIT(25)
63 #define SHTCCTCTLPROT		BIT(26)
64 #define STAGSEL			BIT(27)
65 
66 enum boosting_vals {
67 	BOOST_1000_UA = 1000,
68 	BOOST_2000_UA = 2000,
69 };
70 
71 enum dc_level_vals {
72 	DC_NOMINAL,
73 	DC_PLUS_5_TO_7_MV,
74 	DC_PLUS_10_TO_14_MV,
75 	DC_MINUS_5_TO_7_MV,
76 	DC_MAX,
77 };
78 
79 enum current_trim {
80 	CUR_NOMINAL,
81 	CUR_PLUS_1_56_PCT,
82 	CUR_PLUS_3_12_PCT,
83 	CUR_PLUS_4_68_PCT,
84 	CUR_PLUS_6_24_PCT,
85 	CUR_PLUS_7_8_PCT,
86 	CUR_PLUS_9_36_PCT,
87 	CUR_PLUS_10_92_PCT,
88 	CUR_PLUS_12_48_PCT,
89 	CUR_PLUS_14_04_PCT,
90 	CUR_PLUS_15_6_PCT,
91 	CUR_PLUS_17_16_PCT,
92 	CUR_PLUS_19_01_PCT,
93 	CUR_PLUS_20_58_PCT,
94 	CUR_PLUS_22_16_PCT,
95 	CUR_PLUS_23_73_PCT,
96 	CUR_MAX,
97 };
98 
99 enum impedance_trim {
100 	IMP_NOMINAL,
101 	IMP_MINUS_2_OHMS,
102 	IMP_MINUS_4_OMHS,
103 	IMP_MINUS_6_OHMS,
104 	IMP_MAX,
105 };
106 
107 enum squelch_level {
108 	SQLCH_NOMINAL,
109 	SQLCH_PLUS_7_MV,
110 	SQLCH_MINUS_5_MV,
111 	SQLCH_PLUS_14_MV,
112 	SQLCH_MAX,
113 };
114 
115 enum rx_offset {
116 	NO_RX_OFFSET,
117 	RX_OFFSET_PLUS_5_MV,
118 	RX_OFFSET_PLUS_10_MV,
119 	RX_OFFSET_MINUS_5_MV,
120 	RX_OFFSET_MAX,
121 };
122 
123 /* STM32_USBPHYC_VERSION bit fields */
124 #define MINREV			GENMASK(3, 0)
125 #define MAJREV			GENMASK(7, 4)
126 
127 #define PLL_FVCO_MHZ		2880
128 #define PLL_INFF_MIN_RATE_HZ	19200000
129 #define PLL_INFF_MAX_RATE_HZ	38400000
130 
131 struct pll_params {
132 	u8 ndiv;
133 	u16 frac;
134 };
135 
136 struct stm32_usbphyc_phy {
137 	struct phy *phy;
138 	struct stm32_usbphyc *usbphyc;
139 	struct regulator *vbus;
140 	u32 index;
141 	bool active;
142 	u32 tune;
143 };
144 
145 struct stm32_usbphyc {
146 	struct device *dev;
147 	void __iomem *base;
148 	struct clk *clk;
149 	struct reset_control *rst;
150 	struct stm32_usbphyc_phy **phys;
151 	int nphys;
152 	struct regulator *vdda1v1;
153 	struct regulator *vdda1v8;
154 	atomic_t n_pll_cons;
155 	struct clk_hw clk48_hw;
156 	int switch_setup;
157 };
158 
159 static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits)
160 {
161 	writel_relaxed(readl_relaxed(reg) | bits, reg);
162 }
163 
164 static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits)
165 {
166 	writel_relaxed(readl_relaxed(reg) & ~bits, reg);
167 }
168 
169 static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc)
170 {
171 	int ret;
172 
173 	ret = regulator_enable(usbphyc->vdda1v1);
174 	if (ret)
175 		return ret;
176 
177 	ret = regulator_enable(usbphyc->vdda1v8);
178 	if (ret)
179 		goto vdda1v1_disable;
180 
181 	return 0;
182 
183 vdda1v1_disable:
184 	regulator_disable(usbphyc->vdda1v1);
185 
186 	return ret;
187 }
188 
189 static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc)
190 {
191 	int ret;
192 
193 	ret = regulator_disable(usbphyc->vdda1v8);
194 	if (ret)
195 		return ret;
196 
197 	ret = regulator_disable(usbphyc->vdda1v1);
198 	if (ret)
199 		return ret;
200 
201 	return 0;
202 }
203 
204 static void stm32_usbphyc_get_pll_params(u32 clk_rate,
205 					 struct pll_params *pll_params)
206 {
207 	unsigned long long fvco, ndiv, frac;
208 
209 	/*    _
210 	 *   | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1
211 	 *   | FVCO = 2880MHz
212 	 *  <
213 	 *   | NDIV = integer part of input bits to set the LDF
214 	 *   |_FRACT = fractional part of input bits to set the LDF
215 	 *  =>	PLLNDIV = integer part of (FVCO / (INFF*2))
216 	 *  =>	PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16
217 	 * <=>  PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16
218 	 */
219 	fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ;
220 
221 	ndiv = fvco;
222 	do_div(ndiv, (clk_rate * 2));
223 	pll_params->ndiv = (u8)ndiv;
224 
225 	frac = fvco * (1 << 16);
226 	do_div(frac, (clk_rate * 2));
227 	frac = frac - (ndiv * (1 << 16));
228 	pll_params->frac = (u16)frac;
229 }
230 
231 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc)
232 {
233 	struct pll_params pll_params;
234 	u32 clk_rate = clk_get_rate(usbphyc->clk);
235 	u32 ndiv, frac;
236 	u32 usbphyc_pll;
237 
238 	if ((clk_rate < PLL_INFF_MIN_RATE_HZ) ||
239 	    (clk_rate > PLL_INFF_MAX_RATE_HZ)) {
240 		dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n",
241 			clk_rate);
242 		return -EINVAL;
243 	}
244 
245 	stm32_usbphyc_get_pll_params(clk_rate, &pll_params);
246 	ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv);
247 	frac = FIELD_PREP(PLLFRACIN, pll_params.frac);
248 
249 	usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv;
250 
251 	if (pll_params.frac)
252 		usbphyc_pll |= PLLFRACCTL | frac;
253 
254 	writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL);
255 
256 	dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n",
257 		clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll),
258 		FIELD_GET(PLLFRACIN, usbphyc_pll));
259 
260 	return 0;
261 }
262 
263 static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
264 {
265 	void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
266 	u32 pllen;
267 
268 	stm32_usbphyc_clr_bits(pll_reg, PLLEN);
269 
270 	/* Wait for minimum width of powerdown pulse (ENABLE = Low) */
271 	if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50))
272 		dev_err(usbphyc->dev, "PLL not reset\n");
273 
274 	return stm32_usbphyc_regulators_disable(usbphyc);
275 }
276 
277 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc)
278 {
279 	/* Check if a phy port is still active or clk48 in use */
280 	if (atomic_dec_return(&usbphyc->n_pll_cons) > 0)
281 		return 0;
282 
283 	return __stm32_usbphyc_pll_disable(usbphyc);
284 }
285 
286 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
287 {
288 	void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL;
289 	bool pllen = readl_relaxed(pll_reg) & PLLEN;
290 	int ret;
291 
292 	/*
293 	 * Check if a phy port or clk48 prepare has configured the pll
294 	 * and ensure the PLL is enabled
295 	 */
296 	if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen)
297 		return 0;
298 
299 	if (pllen) {
300 		/*
301 		 * PLL shouldn't be enabled without known consumer,
302 		 * disable it and reinit n_pll_cons
303 		 */
304 		dev_warn(usbphyc->dev, "PLL enabled without known consumers\n");
305 
306 		ret = __stm32_usbphyc_pll_disable(usbphyc);
307 		if (ret)
308 			goto dec_n_pll_cons;
309 	}
310 
311 	ret = stm32_usbphyc_regulators_enable(usbphyc);
312 	if (ret)
313 		goto dec_n_pll_cons;
314 
315 	ret = stm32_usbphyc_pll_init(usbphyc);
316 	if (ret)
317 		goto reg_disable;
318 
319 	stm32_usbphyc_set_bits(pll_reg, PLLEN);
320 
321 	/* Wait for maximum lock time */
322 	usleep_range(200, 300);
323 
324 	return 0;
325 
326 reg_disable:
327 	stm32_usbphyc_regulators_disable(usbphyc);
328 
329 dec_n_pll_cons:
330 	atomic_dec(&usbphyc->n_pll_cons);
331 
332 	return ret;
333 }
334 
335 static int stm32_usbphyc_phy_init(struct phy *phy)
336 {
337 	struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
338 	struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
339 	u32 reg_mon = STM32_USBPHYC_MONITOR(usbphyc_phy->index);
340 	u32 monsel = FIELD_PREP(STM32_USBPHYC_MON_SEL,
341 				STM32_USBPHYC_MON_SEL_LOCKP);
342 	u32 monout;
343 	int ret;
344 
345 	ret = stm32_usbphyc_pll_enable(usbphyc);
346 	if (ret)
347 		return ret;
348 
349 	/* Check that PLL Lock input to PHY is High */
350 	writel_relaxed(monsel, usbphyc->base + reg_mon);
351 	ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout,
352 					 (monout & STM32_USBPHYC_MON_OUT_LOCKP),
353 					 100, 1000);
354 	if (ret) {
355 		dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n",
356 			(u32)(monout & STM32_USBPHYC_MON_OUT));
357 		goto pll_disable;
358 	}
359 
360 	usbphyc_phy->active = true;
361 
362 	return 0;
363 
364 pll_disable:
365 	stm32_usbphyc_pll_disable(usbphyc);
366 
367 	return ret;
368 }
369 
370 static int stm32_usbphyc_phy_exit(struct phy *phy)
371 {
372 	struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
373 	struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc;
374 
375 	usbphyc_phy->active = false;
376 
377 	return stm32_usbphyc_pll_disable(usbphyc);
378 }
379 
380 static int stm32_usbphyc_phy_power_on(struct phy *phy)
381 {
382 	struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
383 
384 	if (usbphyc_phy->vbus)
385 		return regulator_enable(usbphyc_phy->vbus);
386 
387 	return 0;
388 }
389 
390 static int stm32_usbphyc_phy_power_off(struct phy *phy)
391 {
392 	struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy);
393 
394 	if (usbphyc_phy->vbus)
395 		return regulator_disable(usbphyc_phy->vbus);
396 
397 	return 0;
398 }
399 
400 static const struct phy_ops stm32_usbphyc_phy_ops = {
401 	.init = stm32_usbphyc_phy_init,
402 	.exit = stm32_usbphyc_phy_exit,
403 	.power_on = stm32_usbphyc_phy_power_on,
404 	.power_off = stm32_usbphyc_phy_power_off,
405 	.owner = THIS_MODULE,
406 };
407 
408 static int stm32_usbphyc_clk48_prepare(struct clk_hw *hw)
409 {
410 	struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
411 
412 	return stm32_usbphyc_pll_enable(usbphyc);
413 }
414 
415 static void stm32_usbphyc_clk48_unprepare(struct clk_hw *hw)
416 {
417 	struct stm32_usbphyc *usbphyc = container_of(hw, struct stm32_usbphyc, clk48_hw);
418 
419 	stm32_usbphyc_pll_disable(usbphyc);
420 }
421 
422 static unsigned long stm32_usbphyc_clk48_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
423 {
424 	return 48000000;
425 }
426 
427 static const struct clk_ops usbphyc_clk48_ops = {
428 	.prepare = stm32_usbphyc_clk48_prepare,
429 	.unprepare = stm32_usbphyc_clk48_unprepare,
430 	.recalc_rate = stm32_usbphyc_clk48_recalc_rate,
431 };
432 
433 static void stm32_usbphyc_clk48_unregister(void *data)
434 {
435 	struct stm32_usbphyc *usbphyc = data;
436 
437 	of_clk_del_provider(usbphyc->dev->of_node);
438 	clk_hw_unregister(&usbphyc->clk48_hw);
439 }
440 
441 static int stm32_usbphyc_clk48_register(struct stm32_usbphyc *usbphyc)
442 {
443 	struct device_node *node = usbphyc->dev->of_node;
444 	struct clk_init_data init = { };
445 	int ret = 0;
446 
447 	init.name = "ck_usbo_48m";
448 	init.ops = &usbphyc_clk48_ops;
449 
450 	usbphyc->clk48_hw.init = &init;
451 
452 	ret = clk_hw_register(usbphyc->dev, &usbphyc->clk48_hw);
453 	if (ret)
454 		return ret;
455 
456 	ret = of_clk_add_hw_provider(node, of_clk_hw_simple_get, &usbphyc->clk48_hw);
457 	if (ret)
458 		clk_hw_unregister(&usbphyc->clk48_hw);
459 
460 	return ret;
461 }
462 
463 static void stm32_usbphyc_phy_tuning(struct stm32_usbphyc *usbphyc,
464 				     struct device_node *np, u32 index)
465 {
466 	struct stm32_usbphyc_phy *usbphyc_phy = usbphyc->phys[index];
467 	u32 reg = STM32_USBPHYC_TUNE(index);
468 	u32 otpcomp, val;
469 	int ret;
470 
471 	/* Backup OTP compensation code */
472 	otpcomp = FIELD_GET(OTPCOMP, readl_relaxed(usbphyc->base + reg));
473 
474 	ret = of_property_read_u32(np, "st,current-boost-microamp", &val);
475 	if (ret != -EINVAL) {
476 		if (!ret && (val == BOOST_1000_UA || val == BOOST_2000_UA)) {
477 			val = (val == BOOST_2000_UA) ? 1 : 0;
478 			usbphyc_phy->tune |= INCURREN | FIELD_PREP(INCURRINT, val);
479 		} else {
480 			dev_warn(usbphyc->dev, "phy%d: invalid st,current-boost-microamp\n", index);
481 		}
482 	}
483 
484 	if (!of_property_read_bool(np, "st,no-lsfs-fb-cap"))
485 		usbphyc_phy->tune |= LFSCAPEN;
486 
487 	if (of_property_read_bool(np, "st,decrease-hs-slew-rate"))
488 		usbphyc_phy->tune |= HSDRVSLEW;
489 
490 	ret = of_property_read_u32(np, "st,tune-hs-dc-level", &val);
491 	if (ret != -EINVAL) {
492 		if (!ret && val < DC_MAX) {
493 			if (val == DC_MINUS_5_TO_7_MV) {/* Decreases HS driver DC level */
494 				usbphyc_phy->tune |= HSDRVDCCUR;
495 			} else if (val > 0) {		/* Increases HS driver DC level */
496 				val = (val == DC_PLUS_10_TO_14_MV) ? 1 : 0;
497 				usbphyc_phy->tune |= HSDRVCURINCR | FIELD_PREP(HSDRVDCLEV, val);
498 			}
499 		} else {
500 			dev_warn(usbphyc->dev, "phy%d: invalid st,tune-hs-dc-level\n", index);
501 		}
502 	}
503 
504 	if (of_property_read_bool(np, "st,enable-fs-rftime-tuning"))
505 		usbphyc_phy->tune |= FSDRVRFADJ;
506 
507 	if (of_property_read_bool(np, "st,enable-hs-rftime-reduction"))
508 		usbphyc_phy->tune |= HSDRVRFRED;
509 
510 	ret = of_property_read_u32(np, "st,trim-hs-current", &val);
511 	if (ret != -EINVAL) {
512 		if (!ret && val < CUR_MAX)
513 			usbphyc_phy->tune |= FIELD_PREP(HSDRVCHKITRM, val);
514 		else
515 			dev_warn(usbphyc->dev, "phy%d: invalid st,trim-hs-current\n", index);
516 	}
517 
518 	ret = of_property_read_u32(np, "st,trim-hs-impedance", &val);
519 	if (ret != -EINVAL) {
520 		if (!ret && val < IMP_MAX)
521 			usbphyc_phy->tune |= FIELD_PREP(HSDRVCHKZTRM, val);
522 		else
523 			dev_warn(usbphyc->dev, "phy%d: invalid st,trim-hs-impedance\n", index);
524 	}
525 
526 	ret = of_property_read_u32(np, "st,tune-squelch-level", &val);
527 	if (ret != -EINVAL) {
528 		if (!ret && val < SQLCH_MAX)
529 			usbphyc_phy->tune |= FIELD_PREP(SQLCHCTL, val);
530 		else
531 			dev_warn(usbphyc->dev, "phy%d: invalid st,tune-squelch\n", index);
532 	}
533 
534 	if (of_property_read_bool(np, "st,enable-hs-rx-gain-eq"))
535 		usbphyc_phy->tune |= HDRXGNEQEN;
536 
537 	ret = of_property_read_u32(np, "st,tune-hs-rx-offset", &val);
538 	if (ret != -EINVAL) {
539 		if (!ret && val < RX_OFFSET_MAX)
540 			usbphyc_phy->tune |= FIELD_PREP(HSRXOFF, val);
541 		else
542 			dev_warn(usbphyc->dev, "phy%d: invalid st,tune-hs-rx-offset\n", index);
543 	}
544 
545 	if (of_property_read_bool(np, "st,no-hs-ftime-ctrl"))
546 		usbphyc_phy->tune |= HSFALLPREEM;
547 
548 	if (!of_property_read_bool(np, "st,no-lsfs-sc"))
549 		usbphyc_phy->tune |= SHTCCTCTLPROT;
550 
551 	if (of_property_read_bool(np, "st,enable-hs-tx-staggering"))
552 		usbphyc_phy->tune |= STAGSEL;
553 
554 	/* Restore OTP compensation code */
555 	usbphyc_phy->tune |= FIELD_PREP(OTPCOMP, otpcomp);
556 
557 	/*
558 	 * By default, if no st,xxx tuning property is used, usbphyc_phy->tune is equal to
559 	 * STM32_USBPHYC_TUNE reset value (LFSCAPEN | SHTCCTCTLPROT | OTPCOMP).
560 	 */
561 	writel_relaxed(usbphyc_phy->tune, usbphyc->base + reg);
562 }
563 
564 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc,
565 				       u32 utmi_switch)
566 {
567 	if (!utmi_switch)
568 		stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC,
569 				       SWITHOST);
570 	else
571 		stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC,
572 				       SWITHOST);
573 	usbphyc->switch_setup = utmi_switch;
574 }
575 
576 static struct phy *stm32_usbphyc_of_xlate(struct device *dev,
577 					  struct of_phandle_args *args)
578 {
579 	struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
580 	struct stm32_usbphyc_phy *usbphyc_phy = NULL;
581 	struct device_node *phynode = args->np;
582 	int port = 0;
583 
584 	for (port = 0; port < usbphyc->nphys; port++) {
585 		if (phynode == usbphyc->phys[port]->phy->dev.of_node) {
586 			usbphyc_phy = usbphyc->phys[port];
587 			break;
588 		}
589 	}
590 	if (!usbphyc_phy) {
591 		dev_err(dev, "failed to find phy\n");
592 		return ERR_PTR(-EINVAL);
593 	}
594 
595 	if (((usbphyc_phy->index == 0) && (args->args_count != 0)) ||
596 	    ((usbphyc_phy->index == 1) && (args->args_count != 1))) {
597 		dev_err(dev, "invalid number of cells for phy port%d\n",
598 			usbphyc_phy->index);
599 		return ERR_PTR(-EINVAL);
600 	}
601 
602 	/* Configure the UTMI switch for PHY port#2 */
603 	if (usbphyc_phy->index == 1) {
604 		if (usbphyc->switch_setup < 0) {
605 			stm32_usbphyc_switch_setup(usbphyc, args->args[0]);
606 		} else {
607 			if (args->args[0] != usbphyc->switch_setup) {
608 				dev_err(dev, "phy port1 already used\n");
609 				return ERR_PTR(-EBUSY);
610 			}
611 		}
612 	}
613 
614 	return usbphyc_phy->phy;
615 }
616 
617 static int stm32_usbphyc_probe(struct platform_device *pdev)
618 {
619 	struct stm32_usbphyc *usbphyc;
620 	struct device *dev = &pdev->dev;
621 	struct device_node *child, *np = dev->of_node;
622 	struct phy_provider *phy_provider;
623 	u32 pllen, version;
624 	int ret, port = 0;
625 
626 	usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL);
627 	if (!usbphyc)
628 		return -ENOMEM;
629 	usbphyc->dev = dev;
630 	dev_set_drvdata(dev, usbphyc);
631 
632 	usbphyc->base = devm_platform_ioremap_resource(pdev, 0);
633 	if (IS_ERR(usbphyc->base))
634 		return PTR_ERR(usbphyc->base);
635 
636 	usbphyc->clk = devm_clk_get(dev, NULL);
637 	if (IS_ERR(usbphyc->clk))
638 		return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n");
639 
640 	ret = clk_prepare_enable(usbphyc->clk);
641 	if (ret) {
642 		dev_err(dev, "clk enable failed: %d\n", ret);
643 		return ret;
644 	}
645 
646 	usbphyc->rst = devm_reset_control_get(dev, NULL);
647 	if (!IS_ERR(usbphyc->rst)) {
648 		reset_control_assert(usbphyc->rst);
649 		udelay(2);
650 		reset_control_deassert(usbphyc->rst);
651 	} else {
652 		ret = PTR_ERR(usbphyc->rst);
653 		if (ret == -EPROBE_DEFER)
654 			goto clk_disable;
655 
656 		stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN);
657 	}
658 
659 	/*
660 	 * Wait for minimum width of powerdown pulse (ENABLE = Low):
661 	 * we have to ensure the PLL is disabled before phys initialization.
662 	 */
663 	if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL,
664 				       pllen, !(pllen & PLLEN), 5, 50)) {
665 		dev_warn(usbphyc->dev, "PLL not reset\n");
666 		ret = -EPROBE_DEFER;
667 		goto clk_disable;
668 	}
669 
670 	usbphyc->switch_setup = -EINVAL;
671 	usbphyc->nphys = of_get_child_count(np);
672 	usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys,
673 				     sizeof(*usbphyc->phys), GFP_KERNEL);
674 	if (!usbphyc->phys) {
675 		ret = -ENOMEM;
676 		goto clk_disable;
677 	}
678 
679 	usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1");
680 	if (IS_ERR(usbphyc->vdda1v1)) {
681 		ret = dev_err_probe(dev, PTR_ERR(usbphyc->vdda1v1),
682 				    "failed to get vdda1v1 supply\n");
683 		goto clk_disable;
684 	}
685 
686 	usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8");
687 	if (IS_ERR(usbphyc->vdda1v8)) {
688 		ret = dev_err_probe(dev, PTR_ERR(usbphyc->vdda1v8),
689 				    "failed to get vdda1v8 supply\n");
690 		goto clk_disable;
691 	}
692 
693 	for_each_child_of_node(np, child) {
694 		struct stm32_usbphyc_phy *usbphyc_phy;
695 		struct phy *phy;
696 		u32 index;
697 
698 		phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops);
699 		if (IS_ERR(phy)) {
700 			ret = PTR_ERR(phy);
701 			if (ret != -EPROBE_DEFER)
702 				dev_err(dev, "failed to create phy%d: %d\n",
703 					port, ret);
704 			goto put_child;
705 		}
706 
707 		usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy),
708 					   GFP_KERNEL);
709 		if (!usbphyc_phy) {
710 			ret = -ENOMEM;
711 			goto put_child;
712 		}
713 
714 		ret = of_property_read_u32(child, "reg", &index);
715 		if (ret || index > usbphyc->nphys) {
716 			dev_err(&phy->dev, "invalid reg property: %d\n", ret);
717 			if (!ret)
718 				ret = -EINVAL;
719 			goto put_child;
720 		}
721 
722 		usbphyc->phys[port] = usbphyc_phy;
723 		phy_set_bus_width(phy, 8);
724 		phy_set_drvdata(phy, usbphyc_phy);
725 
726 		usbphyc->phys[port]->phy = phy;
727 		usbphyc->phys[port]->usbphyc = usbphyc;
728 		usbphyc->phys[port]->index = index;
729 		usbphyc->phys[port]->active = false;
730 
731 		usbphyc->phys[port]->vbus = devm_regulator_get_optional(&phy->dev, "vbus");
732 		if (IS_ERR(usbphyc->phys[port]->vbus)) {
733 			ret = PTR_ERR(usbphyc->phys[port]->vbus);
734 			if (ret == -EPROBE_DEFER)
735 				goto put_child;
736 			usbphyc->phys[port]->vbus = NULL;
737 		}
738 
739 		/* Configure phy tuning */
740 		stm32_usbphyc_phy_tuning(usbphyc, child, index);
741 
742 		port++;
743 	}
744 
745 	phy_provider = devm_of_phy_provider_register(dev,
746 						     stm32_usbphyc_of_xlate);
747 	if (IS_ERR(phy_provider)) {
748 		ret = PTR_ERR(phy_provider);
749 		dev_err(dev, "failed to register phy provider: %d\n", ret);
750 		goto clk_disable;
751 	}
752 
753 	ret = stm32_usbphyc_clk48_register(usbphyc);
754 	if (ret) {
755 		dev_err(dev, "failed to register ck_usbo_48m clock: %d\n", ret);
756 		goto clk_disable;
757 	}
758 
759 	version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION);
760 	dev_info(dev, "registered rev:%lu.%lu\n",
761 		 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version));
762 
763 	return 0;
764 
765 put_child:
766 	of_node_put(child);
767 clk_disable:
768 	clk_disable_unprepare(usbphyc->clk);
769 
770 	return ret;
771 }
772 
773 static void stm32_usbphyc_remove(struct platform_device *pdev)
774 {
775 	struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev);
776 	int port;
777 
778 	/* Ensure PHYs are not active, to allow PLL disabling */
779 	for (port = 0; port < usbphyc->nphys; port++)
780 		if (usbphyc->phys[port]->active)
781 			stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy);
782 
783 	stm32_usbphyc_clk48_unregister(usbphyc);
784 
785 	clk_disable_unprepare(usbphyc->clk);
786 }
787 
788 static int __maybe_unused stm32_usbphyc_resume(struct device *dev)
789 {
790 	struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev);
791 	struct stm32_usbphyc_phy *usbphyc_phy;
792 	int port;
793 
794 	if (usbphyc->switch_setup >= 0)
795 		stm32_usbphyc_switch_setup(usbphyc, usbphyc->switch_setup);
796 
797 	for (port = 0; port < usbphyc->nphys; port++) {
798 		usbphyc_phy = usbphyc->phys[port];
799 		writel_relaxed(usbphyc_phy->tune, usbphyc->base + STM32_USBPHYC_TUNE(port));
800 	}
801 
802 	return 0;
803 }
804 
805 static SIMPLE_DEV_PM_OPS(stm32_usbphyc_pm_ops, NULL, stm32_usbphyc_resume);
806 
807 static const struct of_device_id stm32_usbphyc_of_match[] = {
808 	{ .compatible = "st,stm32mp1-usbphyc", },
809 	{ },
810 };
811 MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match);
812 
813 static struct platform_driver stm32_usbphyc_driver = {
814 	.probe = stm32_usbphyc_probe,
815 	.remove_new = stm32_usbphyc_remove,
816 	.driver = {
817 		.of_match_table = stm32_usbphyc_of_match,
818 		.name = "stm32-usbphyc",
819 		.pm = &stm32_usbphyc_pm_ops,
820 	}
821 };
822 module_platform_driver(stm32_usbphyc_driver);
823 
824 MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver");
825 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>");
826 MODULE_LICENSE("GPL v2");
827