1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * STMicroelectronics STM32 USB PHY Controller driver 4 * 5 * Copyright (C) 2018 STMicroelectronics 6 * Author(s): Amelie Delaunay <amelie.delaunay@st.com>. 7 */ 8 #include <linux/bitfield.h> 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of_platform.h> 15 #include <linux/phy/phy.h> 16 #include <linux/reset.h> 17 18 #define STM32_USBPHYC_PLL 0x0 19 #define STM32_USBPHYC_MISC 0x8 20 #define STM32_USBPHYC_MONITOR(X) (0x108 + ((X) * 0x100)) 21 #define STM32_USBPHYC_VERSION 0x3F4 22 23 /* STM32_USBPHYC_PLL bit fields */ 24 #define PLLNDIV GENMASK(6, 0) 25 #define PLLFRACIN GENMASK(25, 10) 26 #define PLLEN BIT(26) 27 #define PLLSTRB BIT(27) 28 #define PLLSTRBYP BIT(28) 29 #define PLLFRACCTL BIT(29) 30 #define PLLDITHEN0 BIT(30) 31 #define PLLDITHEN1 BIT(31) 32 33 /* STM32_USBPHYC_MISC bit fields */ 34 #define SWITHOST BIT(0) 35 36 /* STM32_USBPHYC_MONITOR bit fields */ 37 #define STM32_USBPHYC_MON_OUT GENMASK(3, 0) 38 #define STM32_USBPHYC_MON_SEL GENMASK(8, 4) 39 #define STM32_USBPHYC_MON_SEL_LOCKP 0x1F 40 #define STM32_USBPHYC_MON_OUT_LOCKP BIT(3) 41 42 /* STM32_USBPHYC_VERSION bit fields */ 43 #define MINREV GENMASK(3, 0) 44 #define MAJREV GENMASK(7, 4) 45 46 #define PLL_FVCO_MHZ 2880 47 #define PLL_INFF_MIN_RATE_HZ 19200000 48 #define PLL_INFF_MAX_RATE_HZ 38400000 49 #define HZ_PER_MHZ 1000000L 50 51 struct pll_params { 52 u8 ndiv; 53 u16 frac; 54 }; 55 56 struct stm32_usbphyc_phy { 57 struct phy *phy; 58 struct stm32_usbphyc *usbphyc; 59 u32 index; 60 bool active; 61 }; 62 63 struct stm32_usbphyc { 64 struct device *dev; 65 void __iomem *base; 66 struct clk *clk; 67 struct reset_control *rst; 68 struct stm32_usbphyc_phy **phys; 69 int nphys; 70 struct regulator *vdda1v1; 71 struct regulator *vdda1v8; 72 atomic_t n_pll_cons; 73 int switch_setup; 74 }; 75 76 static inline void stm32_usbphyc_set_bits(void __iomem *reg, u32 bits) 77 { 78 writel_relaxed(readl_relaxed(reg) | bits, reg); 79 } 80 81 static inline void stm32_usbphyc_clr_bits(void __iomem *reg, u32 bits) 82 { 83 writel_relaxed(readl_relaxed(reg) & ~bits, reg); 84 } 85 86 static int stm32_usbphyc_regulators_enable(struct stm32_usbphyc *usbphyc) 87 { 88 int ret; 89 90 ret = regulator_enable(usbphyc->vdda1v1); 91 if (ret) 92 return ret; 93 94 ret = regulator_enable(usbphyc->vdda1v8); 95 if (ret) 96 goto vdda1v1_disable; 97 98 return 0; 99 100 vdda1v1_disable: 101 regulator_disable(usbphyc->vdda1v1); 102 103 return ret; 104 } 105 106 static int stm32_usbphyc_regulators_disable(struct stm32_usbphyc *usbphyc) 107 { 108 int ret; 109 110 ret = regulator_disable(usbphyc->vdda1v8); 111 if (ret) 112 return ret; 113 114 ret = regulator_disable(usbphyc->vdda1v1); 115 if (ret) 116 return ret; 117 118 return 0; 119 } 120 121 static void stm32_usbphyc_get_pll_params(u32 clk_rate, 122 struct pll_params *pll_params) 123 { 124 unsigned long long fvco, ndiv, frac; 125 126 /* _ 127 * | FVCO = INFF*2*(NDIV + FRACT/2^16) when DITHER_DISABLE[1] = 1 128 * | FVCO = 2880MHz 129 * < 130 * | NDIV = integer part of input bits to set the LDF 131 * |_FRACT = fractional part of input bits to set the LDF 132 * => PLLNDIV = integer part of (FVCO / (INFF*2)) 133 * => PLLFRACIN = fractional part of(FVCO / INFF*2) * 2^16 134 * <=> PLLFRACIN = ((FVCO / (INFF*2)) - PLLNDIV) * 2^16 135 */ 136 fvco = (unsigned long long)PLL_FVCO_MHZ * HZ_PER_MHZ; 137 138 ndiv = fvco; 139 do_div(ndiv, (clk_rate * 2)); 140 pll_params->ndiv = (u8)ndiv; 141 142 frac = fvco * (1 << 16); 143 do_div(frac, (clk_rate * 2)); 144 frac = frac - (ndiv * (1 << 16)); 145 pll_params->frac = (u16)frac; 146 } 147 148 static int stm32_usbphyc_pll_init(struct stm32_usbphyc *usbphyc) 149 { 150 struct pll_params pll_params; 151 u32 clk_rate = clk_get_rate(usbphyc->clk); 152 u32 ndiv, frac; 153 u32 usbphyc_pll; 154 155 if ((clk_rate < PLL_INFF_MIN_RATE_HZ) || 156 (clk_rate > PLL_INFF_MAX_RATE_HZ)) { 157 dev_err(usbphyc->dev, "input clk freq (%dHz) out of range\n", 158 clk_rate); 159 return -EINVAL; 160 } 161 162 stm32_usbphyc_get_pll_params(clk_rate, &pll_params); 163 ndiv = FIELD_PREP(PLLNDIV, pll_params.ndiv); 164 frac = FIELD_PREP(PLLFRACIN, pll_params.frac); 165 166 usbphyc_pll = PLLDITHEN1 | PLLDITHEN0 | PLLSTRBYP | ndiv; 167 168 if (pll_params.frac) 169 usbphyc_pll |= PLLFRACCTL | frac; 170 171 writel_relaxed(usbphyc_pll, usbphyc->base + STM32_USBPHYC_PLL); 172 173 dev_dbg(usbphyc->dev, "input clk freq=%dHz, ndiv=%lu, frac=%lu\n", 174 clk_rate, FIELD_GET(PLLNDIV, usbphyc_pll), 175 FIELD_GET(PLLFRACIN, usbphyc_pll)); 176 177 return 0; 178 } 179 180 static int __stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc) 181 { 182 void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL; 183 u32 pllen; 184 185 stm32_usbphyc_clr_bits(pll_reg, PLLEN); 186 187 /* Wait for minimum width of powerdown pulse (ENABLE = Low) */ 188 if (readl_relaxed_poll_timeout(pll_reg, pllen, !(pllen & PLLEN), 5, 50)) 189 dev_err(usbphyc->dev, "PLL not reset\n"); 190 191 return stm32_usbphyc_regulators_disable(usbphyc); 192 } 193 194 static int stm32_usbphyc_pll_disable(struct stm32_usbphyc *usbphyc) 195 { 196 /* Check if a phy port is still active or clk48 in use */ 197 if (atomic_dec_return(&usbphyc->n_pll_cons) > 0) 198 return 0; 199 200 return __stm32_usbphyc_pll_disable(usbphyc); 201 } 202 203 static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc) 204 { 205 void __iomem *pll_reg = usbphyc->base + STM32_USBPHYC_PLL; 206 bool pllen = readl_relaxed(pll_reg) & PLLEN; 207 int ret; 208 209 /* 210 * Check if a phy port or clk48 prepare has configured the pll 211 * and ensure the PLL is enabled 212 */ 213 if (atomic_inc_return(&usbphyc->n_pll_cons) > 1 && pllen) 214 return 0; 215 216 if (pllen) { 217 /* 218 * PLL shouldn't be enabled without known consumer, 219 * disable it and reinit n_pll_cons 220 */ 221 dev_warn(usbphyc->dev, "PLL enabled without known consumers\n"); 222 223 ret = __stm32_usbphyc_pll_disable(usbphyc); 224 if (ret) 225 return ret; 226 } 227 228 ret = stm32_usbphyc_regulators_enable(usbphyc); 229 if (ret) 230 goto dec_n_pll_cons; 231 232 ret = stm32_usbphyc_pll_init(usbphyc); 233 if (ret) 234 goto reg_disable; 235 236 stm32_usbphyc_set_bits(pll_reg, PLLEN); 237 238 return 0; 239 240 reg_disable: 241 stm32_usbphyc_regulators_disable(usbphyc); 242 243 dec_n_pll_cons: 244 atomic_dec(&usbphyc->n_pll_cons); 245 246 return ret; 247 } 248 249 static int stm32_usbphyc_phy_init(struct phy *phy) 250 { 251 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy); 252 struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc; 253 u32 reg_mon = STM32_USBPHYC_MONITOR(usbphyc_phy->index); 254 u32 monsel = FIELD_PREP(STM32_USBPHYC_MON_SEL, 255 STM32_USBPHYC_MON_SEL_LOCKP); 256 u32 monout; 257 int ret; 258 259 ret = stm32_usbphyc_pll_enable(usbphyc); 260 if (ret) 261 return ret; 262 263 /* Check that PLL Lock input to PHY is High */ 264 writel_relaxed(monsel, usbphyc->base + reg_mon); 265 ret = readl_relaxed_poll_timeout(usbphyc->base + reg_mon, monout, 266 (monout & STM32_USBPHYC_MON_OUT_LOCKP), 267 100, 1000); 268 if (ret) { 269 dev_err(usbphyc->dev, "PLL Lock input to PHY is Low (val=%x)\n", 270 (u32)(monout & STM32_USBPHYC_MON_OUT)); 271 goto pll_disable; 272 } 273 274 usbphyc_phy->active = true; 275 276 return 0; 277 278 pll_disable: 279 return stm32_usbphyc_pll_disable(usbphyc); 280 } 281 282 static int stm32_usbphyc_phy_exit(struct phy *phy) 283 { 284 struct stm32_usbphyc_phy *usbphyc_phy = phy_get_drvdata(phy); 285 struct stm32_usbphyc *usbphyc = usbphyc_phy->usbphyc; 286 287 usbphyc_phy->active = false; 288 289 return stm32_usbphyc_pll_disable(usbphyc); 290 } 291 292 static const struct phy_ops stm32_usbphyc_phy_ops = { 293 .init = stm32_usbphyc_phy_init, 294 .exit = stm32_usbphyc_phy_exit, 295 .owner = THIS_MODULE, 296 }; 297 298 static void stm32_usbphyc_switch_setup(struct stm32_usbphyc *usbphyc, 299 u32 utmi_switch) 300 { 301 if (!utmi_switch) 302 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_MISC, 303 SWITHOST); 304 else 305 stm32_usbphyc_set_bits(usbphyc->base + STM32_USBPHYC_MISC, 306 SWITHOST); 307 usbphyc->switch_setup = utmi_switch; 308 } 309 310 static struct phy *stm32_usbphyc_of_xlate(struct device *dev, 311 struct of_phandle_args *args) 312 { 313 struct stm32_usbphyc *usbphyc = dev_get_drvdata(dev); 314 struct stm32_usbphyc_phy *usbphyc_phy = NULL; 315 struct device_node *phynode = args->np; 316 int port = 0; 317 318 for (port = 0; port < usbphyc->nphys; port++) { 319 if (phynode == usbphyc->phys[port]->phy->dev.of_node) { 320 usbphyc_phy = usbphyc->phys[port]; 321 break; 322 } 323 } 324 if (!usbphyc_phy) { 325 dev_err(dev, "failed to find phy\n"); 326 return ERR_PTR(-EINVAL); 327 } 328 329 if (((usbphyc_phy->index == 0) && (args->args_count != 0)) || 330 ((usbphyc_phy->index == 1) && (args->args_count != 1))) { 331 dev_err(dev, "invalid number of cells for phy port%d\n", 332 usbphyc_phy->index); 333 return ERR_PTR(-EINVAL); 334 } 335 336 /* Configure the UTMI switch for PHY port#2 */ 337 if (usbphyc_phy->index == 1) { 338 if (usbphyc->switch_setup < 0) { 339 stm32_usbphyc_switch_setup(usbphyc, args->args[0]); 340 } else { 341 if (args->args[0] != usbphyc->switch_setup) { 342 dev_err(dev, "phy port1 already used\n"); 343 return ERR_PTR(-EBUSY); 344 } 345 } 346 } 347 348 return usbphyc_phy->phy; 349 } 350 351 static int stm32_usbphyc_probe(struct platform_device *pdev) 352 { 353 struct stm32_usbphyc *usbphyc; 354 struct device *dev = &pdev->dev; 355 struct device_node *child, *np = dev->of_node; 356 struct phy_provider *phy_provider; 357 u32 pllen, version; 358 int ret, port = 0; 359 360 usbphyc = devm_kzalloc(dev, sizeof(*usbphyc), GFP_KERNEL); 361 if (!usbphyc) 362 return -ENOMEM; 363 usbphyc->dev = dev; 364 dev_set_drvdata(dev, usbphyc); 365 366 usbphyc->base = devm_platform_ioremap_resource(pdev, 0); 367 if (IS_ERR(usbphyc->base)) 368 return PTR_ERR(usbphyc->base); 369 370 usbphyc->clk = devm_clk_get(dev, NULL); 371 if (IS_ERR(usbphyc->clk)) 372 return dev_err_probe(dev, PTR_ERR(usbphyc->clk), "clk get_failed\n"); 373 374 ret = clk_prepare_enable(usbphyc->clk); 375 if (ret) { 376 dev_err(dev, "clk enable failed: %d\n", ret); 377 return ret; 378 } 379 380 usbphyc->rst = devm_reset_control_get(dev, NULL); 381 if (!IS_ERR(usbphyc->rst)) { 382 reset_control_assert(usbphyc->rst); 383 udelay(2); 384 reset_control_deassert(usbphyc->rst); 385 } else { 386 ret = PTR_ERR(usbphyc->rst); 387 if (ret == -EPROBE_DEFER) 388 goto clk_disable; 389 390 stm32_usbphyc_clr_bits(usbphyc->base + STM32_USBPHYC_PLL, PLLEN); 391 } 392 393 /* 394 * Wait for minimum width of powerdown pulse (ENABLE = Low): 395 * we have to ensure the PLL is disabled before phys initialization. 396 */ 397 if (readl_relaxed_poll_timeout(usbphyc->base + STM32_USBPHYC_PLL, 398 pllen, !(pllen & PLLEN), 5, 50)) { 399 dev_warn(usbphyc->dev, "PLL not reset\n"); 400 ret = -EPROBE_DEFER; 401 goto clk_disable; 402 } 403 404 usbphyc->switch_setup = -EINVAL; 405 usbphyc->nphys = of_get_child_count(np); 406 usbphyc->phys = devm_kcalloc(dev, usbphyc->nphys, 407 sizeof(*usbphyc->phys), GFP_KERNEL); 408 if (!usbphyc->phys) { 409 ret = -ENOMEM; 410 goto clk_disable; 411 } 412 413 usbphyc->vdda1v1 = devm_regulator_get(dev, "vdda1v1"); 414 if (IS_ERR(usbphyc->vdda1v1)) { 415 ret = PTR_ERR(usbphyc->vdda1v1); 416 if (ret != -EPROBE_DEFER) 417 dev_err(dev, "failed to get vdda1v1 supply: %d\n", ret); 418 goto clk_disable; 419 } 420 421 usbphyc->vdda1v8 = devm_regulator_get(dev, "vdda1v8"); 422 if (IS_ERR(usbphyc->vdda1v8)) { 423 ret = PTR_ERR(usbphyc->vdda1v8); 424 if (ret != -EPROBE_DEFER) 425 dev_err(dev, "failed to get vdda1v8 supply: %d\n", ret); 426 goto clk_disable; 427 } 428 429 for_each_child_of_node(np, child) { 430 struct stm32_usbphyc_phy *usbphyc_phy; 431 struct phy *phy; 432 u32 index; 433 434 phy = devm_phy_create(dev, child, &stm32_usbphyc_phy_ops); 435 if (IS_ERR(phy)) { 436 ret = PTR_ERR(phy); 437 if (ret != -EPROBE_DEFER) 438 dev_err(dev, "failed to create phy%d: %d\n", 439 port, ret); 440 goto put_child; 441 } 442 443 usbphyc_phy = devm_kzalloc(dev, sizeof(*usbphyc_phy), 444 GFP_KERNEL); 445 if (!usbphyc_phy) { 446 ret = -ENOMEM; 447 goto put_child; 448 } 449 450 ret = of_property_read_u32(child, "reg", &index); 451 if (ret || index > usbphyc->nphys) { 452 dev_err(&phy->dev, "invalid reg property: %d\n", ret); 453 goto put_child; 454 } 455 456 usbphyc->phys[port] = usbphyc_phy; 457 phy_set_bus_width(phy, 8); 458 phy_set_drvdata(phy, usbphyc_phy); 459 460 usbphyc->phys[port]->phy = phy; 461 usbphyc->phys[port]->usbphyc = usbphyc; 462 usbphyc->phys[port]->index = index; 463 usbphyc->phys[port]->active = false; 464 465 port++; 466 } 467 468 phy_provider = devm_of_phy_provider_register(dev, 469 stm32_usbphyc_of_xlate); 470 if (IS_ERR(phy_provider)) { 471 ret = PTR_ERR(phy_provider); 472 dev_err(dev, "failed to register phy provider: %d\n", ret); 473 goto clk_disable; 474 } 475 476 version = readl_relaxed(usbphyc->base + STM32_USBPHYC_VERSION); 477 dev_info(dev, "registered rev:%lu.%lu\n", 478 FIELD_GET(MAJREV, version), FIELD_GET(MINREV, version)); 479 480 return 0; 481 482 put_child: 483 of_node_put(child); 484 clk_disable: 485 clk_disable_unprepare(usbphyc->clk); 486 487 return ret; 488 } 489 490 static int stm32_usbphyc_remove(struct platform_device *pdev) 491 { 492 struct stm32_usbphyc *usbphyc = dev_get_drvdata(&pdev->dev); 493 int port; 494 495 /* Ensure PHYs are not active, to allow PLL disabling */ 496 for (port = 0; port < usbphyc->nphys; port++) 497 if (usbphyc->phys[port]->active) 498 stm32_usbphyc_phy_exit(usbphyc->phys[port]->phy); 499 500 clk_disable_unprepare(usbphyc->clk); 501 502 return 0; 503 } 504 505 static const struct of_device_id stm32_usbphyc_of_match[] = { 506 { .compatible = "st,stm32mp1-usbphyc", }, 507 { }, 508 }; 509 MODULE_DEVICE_TABLE(of, stm32_usbphyc_of_match); 510 511 static struct platform_driver stm32_usbphyc_driver = { 512 .probe = stm32_usbphyc_probe, 513 .remove = stm32_usbphyc_remove, 514 .driver = { 515 .of_match_table = stm32_usbphyc_of_match, 516 .name = "stm32-usbphyc", 517 } 518 }; 519 module_platform_driver(stm32_usbphyc_driver); 520 521 MODULE_DESCRIPTION("STMicroelectronics STM32 USBPHYC driver"); 522 MODULE_AUTHOR("Amelie Delaunay <amelie.delaunay@st.com>"); 523 MODULE_LICENSE("GPL v2"); 524