1 /* 2 * Copyright (C) 2014 STMicroelectronics 3 * 4 * STMicroelectronics PHY driver MiPHY28lp (for SoC STiH407). 5 * 6 * Author: Alexandre Torgue <alexandre.torgue@st.com> 7 * 8 * This program is free software; you can redistribute it and/or modify 9 * it under the terms of the GNU General Public License version 2, as 10 * published by the Free Software Foundation. 11 * 12 */ 13 14 #include <linux/platform_device.h> 15 #include <linux/io.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/of.h> 19 #include <linux/of_platform.h> 20 #include <linux/of_address.h> 21 #include <linux/clk.h> 22 #include <linux/phy/phy.h> 23 #include <linux/delay.h> 24 #include <linux/mfd/syscon.h> 25 #include <linux/regmap.h> 26 #include <linux/reset.h> 27 28 #include <dt-bindings/phy/phy.h> 29 30 /* MiPHY registers */ 31 #define MIPHY_CONF_RESET 0x00 32 #define RST_APPLI_SW BIT(0) 33 #define RST_CONF_SW BIT(1) 34 #define RST_MACRO_SW BIT(2) 35 36 #define MIPHY_RESET 0x01 37 #define RST_PLL_SW BIT(0) 38 #define RST_COMP_SW BIT(2) 39 40 #define MIPHY_STATUS_1 0x02 41 #define PHY_RDY BIT(0) 42 #define HFC_RDY BIT(1) 43 #define HFC_PLL BIT(2) 44 45 #define MIPHY_CONTROL 0x04 46 #define TERM_EN_SW BIT(2) 47 #define DIS_LINK_RST BIT(3) 48 #define AUTO_RST_RX BIT(4) 49 #define PX_RX_POL BIT(5) 50 51 #define MIPHY_BOUNDARY_SEL 0x0a 52 #define TX_SEL BIT(6) 53 #define SSC_SEL BIT(4) 54 #define GENSEL_SEL BIT(0) 55 56 #define MIPHY_BOUNDARY_1 0x0b 57 #define MIPHY_BOUNDARY_2 0x0c 58 #define SSC_EN_SW BIT(2) 59 60 #define MIPHY_PLL_CLKREF_FREQ 0x0d 61 #define MIPHY_SPEED 0x0e 62 #define TX_SPDSEL_80DEC 0 63 #define TX_SPDSEL_40DEC 1 64 #define TX_SPDSEL_20DEC 2 65 #define RX_SPDSEL_80DEC 0 66 #define RX_SPDSEL_40DEC (1 << 2) 67 #define RX_SPDSEL_20DEC (2 << 2) 68 69 #define MIPHY_CONF 0x0f 70 #define MIPHY_CTRL_TEST_SEL 0x20 71 #define MIPHY_CTRL_TEST_1 0x21 72 #define MIPHY_CTRL_TEST_2 0x22 73 #define MIPHY_CTRL_TEST_3 0x23 74 #define MIPHY_CTRL_TEST_4 0x24 75 #define MIPHY_FEEDBACK_TEST 0x25 76 #define MIPHY_DEBUG_BUS 0x26 77 #define MIPHY_DEBUG_STATUS_MSB 0x27 78 #define MIPHY_DEBUG_STATUS_LSB 0x28 79 #define MIPHY_PWR_RAIL_1 0x29 80 #define MIPHY_PWR_RAIL_2 0x2a 81 #define MIPHY_SYNCHAR_CONTROL 0x30 82 83 #define MIPHY_COMP_FSM_1 0x3a 84 #define COMP_START BIT(6) 85 86 #define MIPHY_COMP_FSM_6 0x3f 87 #define COMP_DONE BIT(7) 88 89 #define MIPHY_COMP_POSTP 0x42 90 #define MIPHY_TX_CTRL_1 0x49 91 #define TX_REG_STEP_0V 0 92 #define TX_REG_STEP_P_25MV 1 93 #define TX_REG_STEP_P_50MV 2 94 #define TX_REG_STEP_N_25MV 7 95 #define TX_REG_STEP_N_50MV 6 96 #define TX_REG_STEP_N_75MV 5 97 98 #define MIPHY_TX_CTRL_2 0x4a 99 #define TX_SLEW_SW_40_PS 0 100 #define TX_SLEW_SW_80_PS 1 101 #define TX_SLEW_SW_120_PS 2 102 103 #define MIPHY_TX_CTRL_3 0x4b 104 #define MIPHY_TX_CAL_MAN 0x4e 105 #define TX_SLEW_CAL_MAN_EN BIT(0) 106 107 #define MIPHY_TST_BIAS_BOOST_2 0x62 108 #define MIPHY_BIAS_BOOST_1 0x63 109 #define MIPHY_BIAS_BOOST_2 0x64 110 #define MIPHY_RX_DESBUFF_FDB_2 0x67 111 #define MIPHY_RX_DESBUFF_FDB_3 0x68 112 #define MIPHY_SIGDET_COMPENS1 0x69 113 #define MIPHY_SIGDET_COMPENS2 0x6a 114 #define MIPHY_JITTER_PERIOD 0x6b 115 #define MIPHY_JITTER_AMPLITUDE_1 0x6c 116 #define MIPHY_JITTER_AMPLITUDE_2 0x6d 117 #define MIPHY_JITTER_AMPLITUDE_3 0x6e 118 #define MIPHY_RX_K_GAIN 0x78 119 #define MIPHY_RX_BUFFER_CTRL 0x7a 120 #define VGA_GAIN BIT(0) 121 #define EQ_DC_GAIN BIT(2) 122 #define EQ_BOOST_GAIN BIT(3) 123 124 #define MIPHY_RX_VGA_GAIN 0x7b 125 #define MIPHY_RX_EQU_GAIN_1 0x7f 126 #define MIPHY_RX_EQU_GAIN_2 0x80 127 #define MIPHY_RX_EQU_GAIN_3 0x81 128 #define MIPHY_RX_CAL_CTRL_1 0x97 129 #define MIPHY_RX_CAL_CTRL_2 0x98 130 131 #define MIPHY_RX_CAL_OFFSET_CTRL 0x99 132 #define CAL_OFFSET_VGA_64 (0x03 << 0) 133 #define CAL_OFFSET_THRESHOLD_64 (0x03 << 2) 134 #define VGA_OFFSET_POLARITY BIT(4) 135 #define OFFSET_COMPENSATION_EN BIT(6) 136 137 #define MIPHY_RX_CAL_VGA_STEP 0x9a 138 #define MIPHY_RX_CAL_EYE_MIN 0x9d 139 #define MIPHY_RX_CAL_OPT_LENGTH 0x9f 140 #define MIPHY_RX_LOCK_CTRL_1 0xc1 141 #define MIPHY_RX_LOCK_SETTINGS_OPT 0xc2 142 #define MIPHY_RX_LOCK_STEP 0xc4 143 144 #define MIPHY_RX_SIGDET_SLEEP_OA 0xc9 145 #define MIPHY_RX_SIGDET_SLEEP_SEL 0xca 146 #define MIPHY_RX_SIGDET_WAIT_SEL 0xcb 147 #define MIPHY_RX_SIGDET_DATA_SEL 0xcc 148 #define EN_ULTRA_LOW_POWER BIT(0) 149 #define EN_FIRST_HALF BIT(1) 150 #define EN_SECOND_HALF BIT(2) 151 #define EN_DIGIT_SIGNAL_CHECK BIT(3) 152 153 #define MIPHY_RX_POWER_CTRL_1 0xcd 154 #define MIPHY_RX_POWER_CTRL_2 0xce 155 #define MIPHY_PLL_CALSET_CTRL 0xd3 156 #define MIPHY_PLL_CALSET_1 0xd4 157 #define MIPHY_PLL_CALSET_2 0xd5 158 #define MIPHY_PLL_CALSET_3 0xd6 159 #define MIPHY_PLL_CALSET_4 0xd7 160 #define MIPHY_PLL_SBR_1 0xe3 161 #define SET_NEW_CHANGE BIT(1) 162 163 #define MIPHY_PLL_SBR_2 0xe4 164 #define MIPHY_PLL_SBR_3 0xe5 165 #define MIPHY_PLL_SBR_4 0xe6 166 #define MIPHY_PLL_COMMON_MISC_2 0xe9 167 #define START_ACT_FILT BIT(6) 168 169 #define MIPHY_PLL_SPAREIN 0xeb 170 171 /* 172 * On STiH407 the glue logic can be different among MiPHY devices; for example: 173 * MiPHY0: OSC_FORCE_EXT means: 174 * 0: 30MHz crystal clk - 1: 100MHz ext clk routed through MiPHY1 175 * MiPHY1: OSC_FORCE_EXT means: 176 * 1: 30MHz crystal clk - 0: 100MHz ext clk routed through MiPHY1 177 * Some devices have not the possibility to check if the osc is ready. 178 */ 179 #define MIPHY_OSC_FORCE_EXT BIT(3) 180 #define MIPHY_OSC_RDY BIT(5) 181 182 #define MIPHY_CTRL_MASK 0x0f 183 #define MIPHY_CTRL_DEFAULT 0 184 #define MIPHY_CTRL_SYNC_D_EN BIT(2) 185 186 /* SATA / PCIe defines */ 187 #define SATA_CTRL_MASK 0x07 188 #define PCIE_CTRL_MASK 0xff 189 #define SATA_CTRL_SELECT_SATA 1 190 #define SATA_CTRL_SELECT_PCIE 0 191 #define SYSCFG_PCIE_PCIE_VAL 0x80 192 #define SATA_SPDMODE 1 193 194 #define MIPHY_SATA_BANK_NB 3 195 #define MIPHY_PCIE_BANK_NB 2 196 197 enum { 198 SYSCFG_CTRL, 199 SYSCFG_STATUS, 200 SYSCFG_PCI, 201 SYSCFG_SATA, 202 SYSCFG_REG_MAX, 203 }; 204 205 struct miphy28lp_phy { 206 struct phy *phy; 207 struct miphy28lp_dev *phydev; 208 void __iomem *base; 209 void __iomem *pipebase; 210 211 bool osc_force_ext; 212 bool osc_rdy; 213 bool px_rx_pol_inv; 214 bool ssc; 215 bool tx_impedance; 216 217 struct reset_control *miphy_rst; 218 219 u32 sata_gen; 220 221 /* Sysconfig registers offsets needed to configure the device */ 222 u32 syscfg_reg[SYSCFG_REG_MAX]; 223 u8 type; 224 }; 225 226 struct miphy28lp_dev { 227 struct device *dev; 228 struct regmap *regmap; 229 struct mutex miphy_mutex; 230 struct miphy28lp_phy **phys; 231 int nphys; 232 }; 233 234 struct miphy_initval { 235 u16 reg; 236 u16 val; 237 }; 238 239 enum miphy_sata_gen { SATA_GEN1, SATA_GEN2, SATA_GEN3 }; 240 241 static char *PHY_TYPE_name[] = { "sata-up", "pcie-up", "", "usb3-up" }; 242 243 struct pll_ratio { 244 int clk_ref; 245 int calset_1; 246 int calset_2; 247 int calset_3; 248 int calset_4; 249 int cal_ctrl; 250 }; 251 252 static struct pll_ratio sata_pll_ratio = { 253 .clk_ref = 0x1e, 254 .calset_1 = 0xc8, 255 .calset_2 = 0x00, 256 .calset_3 = 0x00, 257 .calset_4 = 0x00, 258 .cal_ctrl = 0x00, 259 }; 260 261 static struct pll_ratio pcie_pll_ratio = { 262 .clk_ref = 0x1e, 263 .calset_1 = 0xa6, 264 .calset_2 = 0xaa, 265 .calset_3 = 0xaa, 266 .calset_4 = 0x00, 267 .cal_ctrl = 0x00, 268 }; 269 270 static struct pll_ratio usb3_pll_ratio = { 271 .clk_ref = 0x1e, 272 .calset_1 = 0xa6, 273 .calset_2 = 0xaa, 274 .calset_3 = 0xaa, 275 .calset_4 = 0x04, 276 .cal_ctrl = 0x00, 277 }; 278 279 struct miphy28lp_pll_gen { 280 int bank; 281 int speed; 282 int bias_boost_1; 283 int bias_boost_2; 284 int tx_ctrl_1; 285 int tx_ctrl_2; 286 int tx_ctrl_3; 287 int rx_k_gain; 288 int rx_vga_gain; 289 int rx_equ_gain_1; 290 int rx_equ_gain_2; 291 int rx_equ_gain_3; 292 int rx_buff_ctrl; 293 }; 294 295 static struct miphy28lp_pll_gen sata_pll_gen[] = { 296 { 297 .bank = 0x00, 298 .speed = TX_SPDSEL_80DEC | RX_SPDSEL_80DEC, 299 .bias_boost_1 = 0x00, 300 .bias_boost_2 = 0xae, 301 .tx_ctrl_2 = 0x53, 302 .tx_ctrl_3 = 0x00, 303 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN, 304 .rx_vga_gain = 0x00, 305 .rx_equ_gain_1 = 0x7d, 306 .rx_equ_gain_2 = 0x56, 307 .rx_equ_gain_3 = 0x00, 308 }, 309 { 310 .bank = 0x01, 311 .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC, 312 .bias_boost_1 = 0x00, 313 .bias_boost_2 = 0xae, 314 .tx_ctrl_2 = 0x72, 315 .tx_ctrl_3 = 0x20, 316 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN, 317 .rx_vga_gain = 0x00, 318 .rx_equ_gain_1 = 0x7d, 319 .rx_equ_gain_2 = 0x56, 320 .rx_equ_gain_3 = 0x00, 321 }, 322 { 323 .bank = 0x02, 324 .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC, 325 .bias_boost_1 = 0x00, 326 .bias_boost_2 = 0xae, 327 .tx_ctrl_2 = 0xc0, 328 .tx_ctrl_3 = 0x20, 329 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN, 330 .rx_vga_gain = 0x00, 331 .rx_equ_gain_1 = 0x7d, 332 .rx_equ_gain_2 = 0x56, 333 .rx_equ_gain_3 = 0x00, 334 }, 335 }; 336 337 static struct miphy28lp_pll_gen pcie_pll_gen[] = { 338 { 339 .bank = 0x00, 340 .speed = TX_SPDSEL_40DEC | RX_SPDSEL_40DEC, 341 .bias_boost_1 = 0x00, 342 .bias_boost_2 = 0xa5, 343 .tx_ctrl_1 = TX_REG_STEP_N_25MV, 344 .tx_ctrl_2 = 0x71, 345 .tx_ctrl_3 = 0x60, 346 .rx_k_gain = 0x98, 347 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN, 348 .rx_vga_gain = 0x00, 349 .rx_equ_gain_1 = 0x79, 350 .rx_equ_gain_2 = 0x56, 351 }, 352 { 353 .bank = 0x01, 354 .speed = TX_SPDSEL_20DEC | RX_SPDSEL_20DEC, 355 .bias_boost_1 = 0x00, 356 .bias_boost_2 = 0xa5, 357 .tx_ctrl_1 = TX_REG_STEP_N_25MV, 358 .tx_ctrl_2 = 0x70, 359 .tx_ctrl_3 = 0x60, 360 .rx_k_gain = 0xcc, 361 .rx_buff_ctrl = EQ_BOOST_GAIN | EQ_DC_GAIN | VGA_GAIN, 362 .rx_vga_gain = 0x00, 363 .rx_equ_gain_1 = 0x78, 364 .rx_equ_gain_2 = 0x07, 365 }, 366 }; 367 368 static inline void miphy28lp_set_reset(struct miphy28lp_phy *miphy_phy) 369 { 370 void __iomem *base = miphy_phy->base; 371 u8 val; 372 373 /* Putting Macro in reset */ 374 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); 375 376 val = RST_APPLI_SW | RST_CONF_SW; 377 writeb_relaxed(val, base + MIPHY_CONF_RESET); 378 379 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); 380 381 /* Bringing the MIPHY-CPU registers out of reset */ 382 if (miphy_phy->type == PHY_TYPE_PCIE) { 383 val = AUTO_RST_RX | TERM_EN_SW; 384 writeb_relaxed(val, base + MIPHY_CONTROL); 385 } else { 386 val = AUTO_RST_RX | TERM_EN_SW | DIS_LINK_RST; 387 writeb_relaxed(val, base + MIPHY_CONTROL); 388 } 389 } 390 391 static inline void miphy28lp_pll_calibration(struct miphy28lp_phy *miphy_phy, 392 struct pll_ratio *pll_ratio) 393 { 394 void __iomem *base = miphy_phy->base; 395 u8 val; 396 397 /* Applying PLL Settings */ 398 writeb_relaxed(0x1d, base + MIPHY_PLL_SPAREIN); 399 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); 400 401 /* PLL Ratio */ 402 writeb_relaxed(pll_ratio->calset_1, base + MIPHY_PLL_CALSET_1); 403 writeb_relaxed(pll_ratio->calset_2, base + MIPHY_PLL_CALSET_2); 404 writeb_relaxed(pll_ratio->calset_3, base + MIPHY_PLL_CALSET_3); 405 writeb_relaxed(pll_ratio->calset_4, base + MIPHY_PLL_CALSET_4); 406 writeb_relaxed(pll_ratio->cal_ctrl, base + MIPHY_PLL_CALSET_CTRL); 407 408 writeb_relaxed(TX_SEL, base + MIPHY_BOUNDARY_SEL); 409 410 val = (0x68 << 1) | TX_SLEW_CAL_MAN_EN; 411 writeb_relaxed(val, base + MIPHY_TX_CAL_MAN); 412 413 val = VGA_OFFSET_POLARITY | CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64; 414 415 if (miphy_phy->type != PHY_TYPE_SATA) 416 val |= OFFSET_COMPENSATION_EN; 417 418 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); 419 420 if (miphy_phy->type == PHY_TYPE_USB3) { 421 writeb_relaxed(0x00, base + MIPHY_CONF); 422 writeb_relaxed(0x70, base + MIPHY_RX_LOCK_STEP); 423 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_OA); 424 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_SLEEP_SEL); 425 writeb_relaxed(EN_FIRST_HALF, base + MIPHY_RX_SIGDET_WAIT_SEL); 426 427 val = EN_DIGIT_SIGNAL_CHECK | EN_FIRST_HALF; 428 writeb_relaxed(val, base + MIPHY_RX_SIGDET_DATA_SEL); 429 } 430 431 } 432 433 static inline void miphy28lp_sata_config_gen(struct miphy28lp_phy *miphy_phy) 434 { 435 void __iomem *base = miphy_phy->base; 436 int i; 437 438 for (i = 0; i < ARRAY_SIZE(sata_pll_gen); i++) { 439 struct miphy28lp_pll_gen *gen = &sata_pll_gen[i]; 440 441 /* Banked settings */ 442 writeb_relaxed(gen->bank, base + MIPHY_CONF); 443 writeb_relaxed(gen->speed, base + MIPHY_SPEED); 444 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); 445 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); 446 447 /* TX buffer Settings */ 448 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); 449 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); 450 451 /* RX Buffer Settings */ 452 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); 453 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); 454 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); 455 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); 456 writeb_relaxed(gen->rx_equ_gain_3, base + MIPHY_RX_EQU_GAIN_3); 457 } 458 } 459 460 static inline void miphy28lp_pcie_config_gen(struct miphy28lp_phy *miphy_phy) 461 { 462 void __iomem *base = miphy_phy->base; 463 int i; 464 465 for (i = 0; i < ARRAY_SIZE(pcie_pll_gen); i++) { 466 struct miphy28lp_pll_gen *gen = &pcie_pll_gen[i]; 467 468 /* Banked settings */ 469 writeb_relaxed(gen->bank, base + MIPHY_CONF); 470 writeb_relaxed(gen->speed, base + MIPHY_SPEED); 471 writeb_relaxed(gen->bias_boost_1, base + MIPHY_BIAS_BOOST_1); 472 writeb_relaxed(gen->bias_boost_2, base + MIPHY_BIAS_BOOST_2); 473 474 /* TX buffer Settings */ 475 writeb_relaxed(gen->tx_ctrl_1, base + MIPHY_TX_CTRL_1); 476 writeb_relaxed(gen->tx_ctrl_2, base + MIPHY_TX_CTRL_2); 477 writeb_relaxed(gen->tx_ctrl_3, base + MIPHY_TX_CTRL_3); 478 479 writeb_relaxed(gen->rx_k_gain, base + MIPHY_RX_K_GAIN); 480 481 /* RX Buffer Settings */ 482 writeb_relaxed(gen->rx_buff_ctrl, base + MIPHY_RX_BUFFER_CTRL); 483 writeb_relaxed(gen->rx_vga_gain, base + MIPHY_RX_VGA_GAIN); 484 writeb_relaxed(gen->rx_equ_gain_1, base + MIPHY_RX_EQU_GAIN_1); 485 writeb_relaxed(gen->rx_equ_gain_2, base + MIPHY_RX_EQU_GAIN_2); 486 } 487 } 488 489 static inline int miphy28lp_wait_compensation(struct miphy28lp_phy *miphy_phy) 490 { 491 unsigned long finish = jiffies + 5 * HZ; 492 u8 val; 493 494 /* Waiting for Compensation to complete */ 495 do { 496 val = readb_relaxed(miphy_phy->base + MIPHY_COMP_FSM_6); 497 498 if (time_after_eq(jiffies, finish)) 499 return -EBUSY; 500 cpu_relax(); 501 } while (!(val & COMP_DONE)); 502 503 return 0; 504 } 505 506 507 static inline int miphy28lp_compensation(struct miphy28lp_phy *miphy_phy, 508 struct pll_ratio *pll_ratio) 509 { 510 void __iomem *base = miphy_phy->base; 511 512 /* Poll for HFC ready after reset release */ 513 /* Compensation measurement */ 514 writeb_relaxed(RST_PLL_SW | RST_COMP_SW, base + MIPHY_RESET); 515 516 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2); 517 writeb_relaxed(pll_ratio->clk_ref, base + MIPHY_PLL_CLKREF_FREQ); 518 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1); 519 520 if (miphy_phy->type == PHY_TYPE_PCIE) 521 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET); 522 523 writeb_relaxed(0x00, base + MIPHY_RESET); 524 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2); 525 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); 526 527 /* TX compensation offset to re-center TX impedance */ 528 writeb_relaxed(0x00, base + MIPHY_COMP_POSTP); 529 530 if (miphy_phy->type == PHY_TYPE_PCIE) 531 return miphy28lp_wait_compensation(miphy_phy); 532 533 return 0; 534 } 535 536 static inline void miphy28_usb3_miphy_reset(struct miphy28lp_phy *miphy_phy) 537 { 538 void __iomem *base = miphy_phy->base; 539 u8 val; 540 541 /* MIPHY Reset */ 542 writeb_relaxed(RST_APPLI_SW, base + MIPHY_CONF_RESET); 543 writeb_relaxed(0x00, base + MIPHY_CONF_RESET); 544 writeb_relaxed(RST_COMP_SW, base + MIPHY_RESET); 545 546 val = RST_COMP_SW | RST_PLL_SW; 547 writeb_relaxed(val, base + MIPHY_RESET); 548 549 writeb_relaxed(0x00, base + MIPHY_PLL_COMMON_MISC_2); 550 writeb_relaxed(0x1e, base + MIPHY_PLL_CLKREF_FREQ); 551 writeb_relaxed(COMP_START, base + MIPHY_COMP_FSM_1); 552 writeb_relaxed(RST_PLL_SW, base + MIPHY_RESET); 553 writeb_relaxed(0x00, base + MIPHY_RESET); 554 writeb_relaxed(START_ACT_FILT, base + MIPHY_PLL_COMMON_MISC_2); 555 writeb_relaxed(0x00, base + MIPHY_CONF); 556 writeb_relaxed(0x00, base + MIPHY_BOUNDARY_1); 557 writeb_relaxed(0x00, base + MIPHY_TST_BIAS_BOOST_2); 558 writeb_relaxed(0x00, base + MIPHY_CONF); 559 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); 560 writeb_relaxed(0xa5, base + MIPHY_DEBUG_BUS); 561 writeb_relaxed(0x00, base + MIPHY_CONF); 562 } 563 564 static void miphy_sata_tune_ssc(struct miphy28lp_phy *miphy_phy) 565 { 566 void __iomem *base = miphy_phy->base; 567 u8 val; 568 569 /* Compensate Tx impedance to avoid out of range values */ 570 /* 571 * Enable the SSC on PLL for all banks 572 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp 573 */ 574 val = readb_relaxed(base + MIPHY_BOUNDARY_2); 575 val |= SSC_EN_SW; 576 writeb_relaxed(val, base + MIPHY_BOUNDARY_2); 577 578 val = readb_relaxed(base + MIPHY_BOUNDARY_SEL); 579 val |= SSC_SEL; 580 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); 581 582 for (val = 0; val < MIPHY_SATA_BANK_NB; val++) { 583 writeb_relaxed(val, base + MIPHY_CONF); 584 585 /* Add value to each reference clock cycle */ 586 /* and define the period length of the SSC */ 587 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); 588 writeb_relaxed(0x6c, base + MIPHY_PLL_SBR_3); 589 writeb_relaxed(0x81, base + MIPHY_PLL_SBR_4); 590 591 /* Clear any previous request */ 592 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); 593 594 /* requests the PLL to take in account new parameters */ 595 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); 596 597 /* To be sure there is no other pending requests */ 598 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); 599 } 600 } 601 602 static void miphy_pcie_tune_ssc(struct miphy28lp_phy *miphy_phy) 603 { 604 void __iomem *base = miphy_phy->base; 605 u8 val; 606 607 /* Compensate Tx impedance to avoid out of range values */ 608 /* 609 * Enable the SSC on PLL for all banks 610 * SSC Modulation @ 31 KHz and 4000 ppm modulation amp 611 */ 612 val = readb_relaxed(base + MIPHY_BOUNDARY_2); 613 val |= SSC_EN_SW; 614 writeb_relaxed(val, base + MIPHY_BOUNDARY_2); 615 616 val = readb_relaxed(base + MIPHY_BOUNDARY_SEL); 617 val |= SSC_SEL; 618 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); 619 620 for (val = 0; val < MIPHY_PCIE_BANK_NB; val++) { 621 writeb_relaxed(val, base + MIPHY_CONF); 622 623 /* Validate Step component */ 624 writeb_relaxed(0x69, base + MIPHY_PLL_SBR_3); 625 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4); 626 627 /* Validate Period component */ 628 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); 629 writeb_relaxed(0x21, base + MIPHY_PLL_SBR_4); 630 631 /* Clear any previous request */ 632 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); 633 634 /* requests the PLL to take in account new parameters */ 635 writeb_relaxed(SET_NEW_CHANGE, base + MIPHY_PLL_SBR_1); 636 637 /* To be sure there is no other pending requests */ 638 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); 639 } 640 } 641 642 static inline void miphy_tune_tx_impedance(struct miphy28lp_phy *miphy_phy) 643 { 644 /* Compensate Tx impedance to avoid out of range values */ 645 writeb_relaxed(0x02, miphy_phy->base + MIPHY_COMP_POSTP); 646 } 647 648 static inline int miphy28lp_configure_sata(struct miphy28lp_phy *miphy_phy) 649 { 650 void __iomem *base = miphy_phy->base; 651 int err; 652 u8 val; 653 654 /* Putting Macro in reset */ 655 miphy28lp_set_reset(miphy_phy); 656 657 /* PLL calibration */ 658 miphy28lp_pll_calibration(miphy_phy, &sata_pll_ratio); 659 660 /* Banked settings Gen1/Gen2/Gen3 */ 661 miphy28lp_sata_config_gen(miphy_phy); 662 663 /* Power control */ 664 /* Input bridge enable, manual input bridge control */ 665 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); 666 667 /* Macro out of reset */ 668 writeb_relaxed(0x00, base + MIPHY_CONF_RESET); 669 670 /* Poll for HFC ready after reset release */ 671 /* Compensation measurement */ 672 err = miphy28lp_compensation(miphy_phy, &sata_pll_ratio); 673 if (err) 674 return err; 675 676 if (miphy_phy->px_rx_pol_inv) { 677 /* Invert Rx polarity */ 678 val = readb_relaxed(miphy_phy->base + MIPHY_CONTROL); 679 val |= PX_RX_POL; 680 writeb_relaxed(val, miphy_phy->base + MIPHY_CONTROL); 681 } 682 683 if (miphy_phy->ssc) 684 miphy_sata_tune_ssc(miphy_phy); 685 686 if (miphy_phy->tx_impedance) 687 miphy_tune_tx_impedance(miphy_phy); 688 689 return 0; 690 } 691 692 static inline int miphy28lp_configure_pcie(struct miphy28lp_phy *miphy_phy) 693 { 694 void __iomem *base = miphy_phy->base; 695 int err; 696 697 /* Putting Macro in reset */ 698 miphy28lp_set_reset(miphy_phy); 699 700 /* PLL calibration */ 701 miphy28lp_pll_calibration(miphy_phy, &pcie_pll_ratio); 702 703 /* Banked settings Gen1/Gen2 */ 704 miphy28lp_pcie_config_gen(miphy_phy); 705 706 /* Power control */ 707 /* Input bridge enable, manual input bridge control */ 708 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); 709 710 /* Macro out of reset */ 711 writeb_relaxed(0x00, base + MIPHY_CONF_RESET); 712 713 /* Poll for HFC ready after reset release */ 714 /* Compensation measurement */ 715 err = miphy28lp_compensation(miphy_phy, &pcie_pll_ratio); 716 if (err) 717 return err; 718 719 if (miphy_phy->ssc) 720 miphy_pcie_tune_ssc(miphy_phy); 721 722 if (miphy_phy->tx_impedance) 723 miphy_tune_tx_impedance(miphy_phy); 724 725 return 0; 726 } 727 728 729 static inline void miphy28lp_configure_usb3(struct miphy28lp_phy *miphy_phy) 730 { 731 void __iomem *base = miphy_phy->base; 732 u8 val; 733 734 /* Putting Macro in reset */ 735 miphy28lp_set_reset(miphy_phy); 736 737 /* PLL calibration */ 738 miphy28lp_pll_calibration(miphy_phy, &usb3_pll_ratio); 739 740 /* Writing The Speed Rate */ 741 writeb_relaxed(0x00, base + MIPHY_CONF); 742 743 val = RX_SPDSEL_20DEC | TX_SPDSEL_20DEC; 744 writeb_relaxed(val, base + MIPHY_SPEED); 745 746 /* RX Channel compensation and calibration */ 747 writeb_relaxed(0x1c, base + MIPHY_RX_LOCK_SETTINGS_OPT); 748 writeb_relaxed(0x51, base + MIPHY_RX_CAL_CTRL_1); 749 writeb_relaxed(0x70, base + MIPHY_RX_CAL_CTRL_2); 750 751 val = OFFSET_COMPENSATION_EN | VGA_OFFSET_POLARITY | 752 CAL_OFFSET_THRESHOLD_64 | CAL_OFFSET_VGA_64; 753 writeb_relaxed(val, base + MIPHY_RX_CAL_OFFSET_CTRL); 754 writeb_relaxed(0x22, base + MIPHY_RX_CAL_VGA_STEP); 755 writeb_relaxed(0x0e, base + MIPHY_RX_CAL_OPT_LENGTH); 756 757 val = EQ_DC_GAIN | VGA_GAIN; 758 writeb_relaxed(val, base + MIPHY_RX_BUFFER_CTRL); 759 writeb_relaxed(0x78, base + MIPHY_RX_EQU_GAIN_1); 760 writeb_relaxed(0x1b, base + MIPHY_SYNCHAR_CONTROL); 761 762 /* TX compensation offset to re-center TX impedance */ 763 writeb_relaxed(0x02, base + MIPHY_COMP_POSTP); 764 765 /* Enable GENSEL_SEL and SSC */ 766 /* TX_SEL=0 swing preemp forced by pipe registres */ 767 val = SSC_SEL | GENSEL_SEL; 768 writeb_relaxed(val, base + MIPHY_BOUNDARY_SEL); 769 770 /* MIPHY Bias boost */ 771 writeb_relaxed(0x00, base + MIPHY_BIAS_BOOST_1); 772 writeb_relaxed(0xa7, base + MIPHY_BIAS_BOOST_2); 773 774 /* SSC modulation */ 775 writeb_relaxed(SSC_EN_SW, base + MIPHY_BOUNDARY_2); 776 777 /* MIPHY TX control */ 778 writeb_relaxed(0x00, base + MIPHY_CONF); 779 780 /* Validate Step component */ 781 writeb_relaxed(0x5a, base + MIPHY_PLL_SBR_3); 782 writeb_relaxed(0xa0, base + MIPHY_PLL_SBR_4); 783 784 /* Validate Period component */ 785 writeb_relaxed(0x3c, base + MIPHY_PLL_SBR_2); 786 writeb_relaxed(0xa1, base + MIPHY_PLL_SBR_4); 787 788 /* Clear any previous request */ 789 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); 790 791 /* requests the PLL to take in account new parameters */ 792 writeb_relaxed(0x02, base + MIPHY_PLL_SBR_1); 793 794 /* To be sure there is no other pending requests */ 795 writeb_relaxed(0x00, base + MIPHY_PLL_SBR_1); 796 797 /* Rx PI controller settings */ 798 writeb_relaxed(0xca, base + MIPHY_RX_K_GAIN); 799 800 /* MIPHY RX input bridge control */ 801 /* INPUT_BRIDGE_EN_SW=1, manual input bridge control[0]=1 */ 802 writeb_relaxed(0x21, base + MIPHY_RX_POWER_CTRL_1); 803 writeb_relaxed(0x29, base + MIPHY_RX_POWER_CTRL_1); 804 writeb_relaxed(0x1a, base + MIPHY_RX_POWER_CTRL_2); 805 806 /* MIPHY Reset for usb3 */ 807 miphy28_usb3_miphy_reset(miphy_phy); 808 } 809 810 static inline int miphy_is_ready(struct miphy28lp_phy *miphy_phy) 811 { 812 unsigned long finish = jiffies + 5 * HZ; 813 u8 mask = HFC_PLL | HFC_RDY; 814 u8 val; 815 816 /* 817 * For PCIe and USB3 check only that PLL and HFC are ready 818 * For SATA check also that phy is ready! 819 */ 820 if (miphy_phy->type == PHY_TYPE_SATA) 821 mask |= PHY_RDY; 822 823 do { 824 val = readb_relaxed(miphy_phy->base + MIPHY_STATUS_1); 825 if ((val & mask) != mask) 826 cpu_relax(); 827 else 828 return 0; 829 } while (!time_after_eq(jiffies, finish)); 830 831 return -EBUSY; 832 } 833 834 static int miphy_osc_is_ready(struct miphy28lp_phy *miphy_phy) 835 { 836 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; 837 unsigned long finish = jiffies + 5 * HZ; 838 u32 val; 839 840 if (!miphy_phy->osc_rdy) 841 return 0; 842 843 if (!miphy_phy->syscfg_reg[SYSCFG_STATUS]) 844 return -EINVAL; 845 846 do { 847 regmap_read(miphy_dev->regmap, 848 miphy_phy->syscfg_reg[SYSCFG_STATUS], &val); 849 850 if ((val & MIPHY_OSC_RDY) != MIPHY_OSC_RDY) 851 cpu_relax(); 852 else 853 return 0; 854 } while (!time_after_eq(jiffies, finish)); 855 856 return -EBUSY; 857 } 858 859 static int miphy28lp_get_resource_byname(struct device_node *child, 860 char *rname, struct resource *res) 861 { 862 int index; 863 864 index = of_property_match_string(child, "reg-names", rname); 865 if (index < 0) 866 return -ENODEV; 867 868 return of_address_to_resource(child, index, res); 869 } 870 871 static int miphy28lp_get_one_addr(struct device *dev, 872 struct device_node *child, char *rname, 873 void __iomem **base) 874 { 875 struct resource res; 876 int ret; 877 878 ret = miphy28lp_get_resource_byname(child, rname, &res); 879 if (!ret) { 880 *base = devm_ioremap(dev, res.start, resource_size(&res)); 881 if (!*base) { 882 dev_err(dev, "failed to ioremap %s address region\n" 883 , rname); 884 return -ENOENT; 885 } 886 } 887 888 return 0; 889 } 890 891 /* MiPHY reset and sysconf setup */ 892 static int miphy28lp_setup(struct miphy28lp_phy *miphy_phy, u32 miphy_val) 893 { 894 int err; 895 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; 896 897 if (!miphy_phy->syscfg_reg[SYSCFG_CTRL]) 898 return -EINVAL; 899 900 err = reset_control_assert(miphy_phy->miphy_rst); 901 if (err) { 902 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); 903 return err; 904 } 905 906 if (miphy_phy->osc_force_ext) 907 miphy_val |= MIPHY_OSC_FORCE_EXT; 908 909 regmap_update_bits(miphy_dev->regmap, 910 miphy_phy->syscfg_reg[SYSCFG_CTRL], 911 MIPHY_CTRL_MASK, miphy_val); 912 913 err = reset_control_deassert(miphy_phy->miphy_rst); 914 if (err) { 915 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); 916 return err; 917 } 918 919 return miphy_osc_is_ready(miphy_phy); 920 } 921 922 static int miphy28lp_init_sata(struct miphy28lp_phy *miphy_phy) 923 { 924 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; 925 int err, sata_conf = SATA_CTRL_SELECT_SATA; 926 927 if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) || 928 (!miphy_phy->syscfg_reg[SYSCFG_PCI]) || 929 (!miphy_phy->base)) 930 return -EINVAL; 931 932 dev_info(miphy_dev->dev, "sata-up mode, addr 0x%p\n", miphy_phy->base); 933 934 /* Configure the glue-logic */ 935 sata_conf |= ((miphy_phy->sata_gen - SATA_GEN1) << SATA_SPDMODE); 936 937 regmap_update_bits(miphy_dev->regmap, 938 miphy_phy->syscfg_reg[SYSCFG_SATA], 939 SATA_CTRL_MASK, sata_conf); 940 941 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI], 942 PCIE_CTRL_MASK, SATA_CTRL_SELECT_PCIE); 943 944 /* MiPHY path and clocking init */ 945 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT); 946 947 if (err) { 948 dev_err(miphy_dev->dev, "SATA phy setup failed\n"); 949 return err; 950 } 951 952 /* initialize miphy */ 953 miphy28lp_configure_sata(miphy_phy); 954 955 return miphy_is_ready(miphy_phy); 956 } 957 958 static int miphy28lp_init_pcie(struct miphy28lp_phy *miphy_phy) 959 { 960 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; 961 int err; 962 963 if ((!miphy_phy->syscfg_reg[SYSCFG_SATA]) || 964 (!miphy_phy->syscfg_reg[SYSCFG_PCI]) 965 || (!miphy_phy->base) || (!miphy_phy->pipebase)) 966 return -EINVAL; 967 968 dev_info(miphy_dev->dev, "pcie-up mode, addr 0x%p\n", miphy_phy->base); 969 970 /* Configure the glue-logic */ 971 regmap_update_bits(miphy_dev->regmap, 972 miphy_phy->syscfg_reg[SYSCFG_SATA], 973 SATA_CTRL_MASK, SATA_CTRL_SELECT_PCIE); 974 975 regmap_update_bits(miphy_dev->regmap, miphy_phy->syscfg_reg[SYSCFG_PCI], 976 PCIE_CTRL_MASK, SYSCFG_PCIE_PCIE_VAL); 977 978 /* MiPHY path and clocking init */ 979 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_DEFAULT); 980 981 if (err) { 982 dev_err(miphy_dev->dev, "PCIe phy setup failed\n"); 983 return err; 984 } 985 986 /* initialize miphy */ 987 err = miphy28lp_configure_pcie(miphy_phy); 988 if (err) 989 return err; 990 991 /* PIPE Wrapper Configuration */ 992 writeb_relaxed(0x68, miphy_phy->pipebase + 0x104); /* Rise_0 */ 993 writeb_relaxed(0x61, miphy_phy->pipebase + 0x105); /* Rise_1 */ 994 writeb_relaxed(0x68, miphy_phy->pipebase + 0x108); /* Fall_0 */ 995 writeb_relaxed(0x61, miphy_phy->pipebase + 0x109); /* Fall-1 */ 996 writeb_relaxed(0x68, miphy_phy->pipebase + 0x10c); /* Threshold_0 */ 997 writeb_relaxed(0x60, miphy_phy->pipebase + 0x10d); /* Threshold_1 */ 998 999 /* Wait for phy_ready */ 1000 return miphy_is_ready(miphy_phy); 1001 } 1002 1003 static int miphy28lp_init_usb3(struct miphy28lp_phy *miphy_phy) 1004 { 1005 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; 1006 int err; 1007 1008 if ((!miphy_phy->base) || (!miphy_phy->pipebase)) 1009 return -EINVAL; 1010 1011 dev_info(miphy_dev->dev, "usb3-up mode, addr 0x%p\n", miphy_phy->base); 1012 1013 /* MiPHY path and clocking init */ 1014 err = miphy28lp_setup(miphy_phy, MIPHY_CTRL_SYNC_D_EN); 1015 if (err) { 1016 dev_err(miphy_dev->dev, "USB3 phy setup failed\n"); 1017 return err; 1018 } 1019 1020 /* initialize miphy */ 1021 miphy28lp_configure_usb3(miphy_phy); 1022 1023 /* PIPE Wrapper Configuration */ 1024 writeb_relaxed(0x68, miphy_phy->pipebase + 0x23); 1025 writeb_relaxed(0x61, miphy_phy->pipebase + 0x24); 1026 writeb_relaxed(0x68, miphy_phy->pipebase + 0x26); 1027 writeb_relaxed(0x61, miphy_phy->pipebase + 0x27); 1028 writeb_relaxed(0x18, miphy_phy->pipebase + 0x29); 1029 writeb_relaxed(0x61, miphy_phy->pipebase + 0x2a); 1030 1031 /* pipe Wrapper usb3 TX swing de-emph margin PREEMPH[7:4], SWING[3:0] */ 1032 writeb_relaxed(0X67, miphy_phy->pipebase + 0x68); 1033 writeb_relaxed(0x0d, miphy_phy->pipebase + 0x69); 1034 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6a); 1035 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6b); 1036 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6c); 1037 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6d); 1038 writeb_relaxed(0X67, miphy_phy->pipebase + 0x6e); 1039 writeb_relaxed(0X0d, miphy_phy->pipebase + 0x6f); 1040 1041 return miphy_is_ready(miphy_phy); 1042 } 1043 1044 static int miphy28lp_init(struct phy *phy) 1045 { 1046 struct miphy28lp_phy *miphy_phy = phy_get_drvdata(phy); 1047 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; 1048 int ret; 1049 1050 mutex_lock(&miphy_dev->miphy_mutex); 1051 1052 switch (miphy_phy->type) { 1053 1054 case PHY_TYPE_SATA: 1055 ret = miphy28lp_init_sata(miphy_phy); 1056 break; 1057 case PHY_TYPE_PCIE: 1058 ret = miphy28lp_init_pcie(miphy_phy); 1059 break; 1060 case PHY_TYPE_USB3: 1061 ret = miphy28lp_init_usb3(miphy_phy); 1062 break; 1063 default: 1064 ret = -EINVAL; 1065 break; 1066 } 1067 1068 mutex_unlock(&miphy_dev->miphy_mutex); 1069 1070 return ret; 1071 } 1072 1073 static int miphy28lp_get_addr(struct miphy28lp_phy *miphy_phy) 1074 { 1075 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; 1076 struct device_node *phynode = miphy_phy->phy->dev.of_node; 1077 int err; 1078 1079 if ((miphy_phy->type != PHY_TYPE_SATA) && 1080 (miphy_phy->type != PHY_TYPE_PCIE) && 1081 (miphy_phy->type != PHY_TYPE_USB3)) { 1082 return -EINVAL; 1083 } 1084 1085 err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, 1086 PHY_TYPE_name[miphy_phy->type - PHY_TYPE_SATA], 1087 &miphy_phy->base); 1088 if (err) 1089 return err; 1090 1091 if ((miphy_phy->type == PHY_TYPE_PCIE) || 1092 (miphy_phy->type == PHY_TYPE_USB3)) { 1093 err = miphy28lp_get_one_addr(miphy_dev->dev, phynode, "pipew", 1094 &miphy_phy->pipebase); 1095 if (err) 1096 return err; 1097 } 1098 1099 return 0; 1100 } 1101 1102 static struct phy *miphy28lp_xlate(struct device *dev, 1103 struct of_phandle_args *args) 1104 { 1105 struct miphy28lp_dev *miphy_dev = dev_get_drvdata(dev); 1106 struct miphy28lp_phy *miphy_phy = NULL; 1107 struct device_node *phynode = args->np; 1108 int ret, index = 0; 1109 1110 if (args->args_count != 1) { 1111 dev_err(dev, "Invalid number of cells in 'phy' property\n"); 1112 return ERR_PTR(-EINVAL); 1113 } 1114 1115 for (index = 0; index < miphy_dev->nphys; index++) 1116 if (phynode == miphy_dev->phys[index]->phy->dev.of_node) { 1117 miphy_phy = miphy_dev->phys[index]; 1118 break; 1119 } 1120 1121 if (!miphy_phy) { 1122 dev_err(dev, "Failed to find appropriate phy\n"); 1123 return ERR_PTR(-EINVAL); 1124 } 1125 1126 miphy_phy->type = args->args[0]; 1127 1128 ret = miphy28lp_get_addr(miphy_phy); 1129 if (ret < 0) 1130 return ERR_PTR(ret); 1131 1132 return miphy_phy->phy; 1133 } 1134 1135 static const struct phy_ops miphy28lp_ops = { 1136 .init = miphy28lp_init, 1137 .owner = THIS_MODULE, 1138 }; 1139 1140 static int miphy28lp_probe_resets(struct device_node *node, 1141 struct miphy28lp_phy *miphy_phy) 1142 { 1143 struct miphy28lp_dev *miphy_dev = miphy_phy->phydev; 1144 int err; 1145 1146 miphy_phy->miphy_rst = 1147 of_reset_control_get_shared(node, "miphy-sw-rst"); 1148 1149 if (IS_ERR(miphy_phy->miphy_rst)) { 1150 dev_err(miphy_dev->dev, 1151 "miphy soft reset control not defined\n"); 1152 return PTR_ERR(miphy_phy->miphy_rst); 1153 } 1154 1155 err = reset_control_deassert(miphy_phy->miphy_rst); 1156 if (err) { 1157 dev_err(miphy_dev->dev, "unable to bring out of miphy reset\n"); 1158 return err; 1159 } 1160 1161 return 0; 1162 } 1163 1164 static int miphy28lp_of_probe(struct device_node *np, 1165 struct miphy28lp_phy *miphy_phy) 1166 { 1167 int i; 1168 u32 ctrlreg; 1169 1170 miphy_phy->osc_force_ext = 1171 of_property_read_bool(np, "st,osc-force-ext"); 1172 1173 miphy_phy->osc_rdy = of_property_read_bool(np, "st,osc-rdy"); 1174 1175 miphy_phy->px_rx_pol_inv = 1176 of_property_read_bool(np, "st,px_rx_pol_inv"); 1177 1178 miphy_phy->ssc = of_property_read_bool(np, "st,ssc-on"); 1179 1180 miphy_phy->tx_impedance = 1181 of_property_read_bool(np, "st,tx-impedance-comp"); 1182 1183 of_property_read_u32(np, "st,sata-gen", &miphy_phy->sata_gen); 1184 if (!miphy_phy->sata_gen) 1185 miphy_phy->sata_gen = SATA_GEN1; 1186 1187 for (i = 0; i < SYSCFG_REG_MAX; i++) { 1188 if (!of_property_read_u32_index(np, "st,syscfg", i, &ctrlreg)) 1189 miphy_phy->syscfg_reg[i] = ctrlreg; 1190 } 1191 1192 return 0; 1193 } 1194 1195 static int miphy28lp_probe(struct platform_device *pdev) 1196 { 1197 struct device_node *child, *np = pdev->dev.of_node; 1198 struct miphy28lp_dev *miphy_dev; 1199 struct phy_provider *provider; 1200 struct phy *phy; 1201 int ret, port = 0; 1202 1203 miphy_dev = devm_kzalloc(&pdev->dev, sizeof(*miphy_dev), GFP_KERNEL); 1204 if (!miphy_dev) 1205 return -ENOMEM; 1206 1207 miphy_dev->nphys = of_get_child_count(np); 1208 miphy_dev->phys = devm_kcalloc(&pdev->dev, miphy_dev->nphys, 1209 sizeof(*miphy_dev->phys), GFP_KERNEL); 1210 if (!miphy_dev->phys) 1211 return -ENOMEM; 1212 1213 miphy_dev->regmap = syscon_regmap_lookup_by_phandle(np, "st,syscfg"); 1214 if (IS_ERR(miphy_dev->regmap)) { 1215 dev_err(miphy_dev->dev, "No syscfg phandle specified\n"); 1216 return PTR_ERR(miphy_dev->regmap); 1217 } 1218 1219 miphy_dev->dev = &pdev->dev; 1220 1221 dev_set_drvdata(&pdev->dev, miphy_dev); 1222 1223 mutex_init(&miphy_dev->miphy_mutex); 1224 1225 for_each_child_of_node(np, child) { 1226 struct miphy28lp_phy *miphy_phy; 1227 1228 miphy_phy = devm_kzalloc(&pdev->dev, sizeof(*miphy_phy), 1229 GFP_KERNEL); 1230 if (!miphy_phy) { 1231 ret = -ENOMEM; 1232 goto put_child; 1233 } 1234 1235 miphy_dev->phys[port] = miphy_phy; 1236 1237 phy = devm_phy_create(&pdev->dev, child, &miphy28lp_ops); 1238 if (IS_ERR(phy)) { 1239 dev_err(&pdev->dev, "failed to create PHY\n"); 1240 ret = PTR_ERR(phy); 1241 goto put_child; 1242 } 1243 1244 miphy_dev->phys[port]->phy = phy; 1245 miphy_dev->phys[port]->phydev = miphy_dev; 1246 1247 ret = miphy28lp_of_probe(child, miphy_phy); 1248 if (ret) 1249 goto put_child; 1250 1251 ret = miphy28lp_probe_resets(child, miphy_dev->phys[port]); 1252 if (ret) 1253 goto put_child; 1254 1255 phy_set_drvdata(phy, miphy_dev->phys[port]); 1256 port++; 1257 1258 } 1259 1260 provider = devm_of_phy_provider_register(&pdev->dev, miphy28lp_xlate); 1261 return PTR_ERR_OR_ZERO(provider); 1262 put_child: 1263 of_node_put(child); 1264 return ret; 1265 } 1266 1267 static const struct of_device_id miphy28lp_of_match[] = { 1268 {.compatible = "st,miphy28lp-phy", }, 1269 {}, 1270 }; 1271 1272 MODULE_DEVICE_TABLE(of, miphy28lp_of_match); 1273 1274 static struct platform_driver miphy28lp_driver = { 1275 .probe = miphy28lp_probe, 1276 .driver = { 1277 .name = "miphy28lp-phy", 1278 .of_match_table = miphy28lp_of_match, 1279 } 1280 }; 1281 1282 module_platform_driver(miphy28lp_driver); 1283 1284 MODULE_AUTHOR("Alexandre Torgue <alexandre.torgue@st.com>"); 1285 MODULE_DESCRIPTION("STMicroelectronics miphy28lp driver"); 1286 MODULE_LICENSE("GPL v2"); 1287