10b56e9a7SVivek Gautam /* 20b56e9a7SVivek Gautam * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4x12 support 30b56e9a7SVivek Gautam * 40b56e9a7SVivek Gautam * Copyright (C) 2013 Samsung Electronics Co., Ltd. 50b56e9a7SVivek Gautam * Author: Kamil Debski <k.debski@samsung.com> 60b56e9a7SVivek Gautam * 70b56e9a7SVivek Gautam * This program is free software; you can redistribute it and/or modify 80b56e9a7SVivek Gautam * it under the terms of the GNU General Public License version 2 as 90b56e9a7SVivek Gautam * published by the Free Software Foundation. 100b56e9a7SVivek Gautam */ 110b56e9a7SVivek Gautam 120b56e9a7SVivek Gautam #include <linux/delay.h> 130b56e9a7SVivek Gautam #include <linux/io.h> 140b56e9a7SVivek Gautam #include <linux/phy/phy.h> 150b56e9a7SVivek Gautam #include <linux/regmap.h> 160b56e9a7SVivek Gautam #include "phy-samsung-usb2.h" 170b56e9a7SVivek Gautam 180b56e9a7SVivek Gautam /* Exynos USB PHY registers */ 190b56e9a7SVivek Gautam 200b56e9a7SVivek Gautam /* PHY power control */ 210b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR 0x0 220b56e9a7SVivek Gautam 230b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND BIT(0) 240b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY0_PWR BIT(3) 250b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR BIT(4) 260b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY0_SLEEP BIT(5) 270b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY0 ( \ 280b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND | \ 290b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY0_PWR | \ 300b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR | \ 310b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY0_SLEEP) 320b56e9a7SVivek Gautam 330b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND BIT(6) 340b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY1_PWR BIT(7) 350b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY1_SLEEP BIT(8) 360b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY1 ( \ 370b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND | \ 380b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY1_PWR | \ 390b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY1_SLEEP) 400b56e9a7SVivek Gautam 410b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC0_SUSPEND BIT(9) 420b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC0_PWR BIT(10) 430b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC0_SLEEP BIT(11) 440b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC0 ( \ 450b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_HSIC0_SUSPEND | \ 460b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_HSIC0_PWR | \ 470b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_HSIC0_SLEEP) 480b56e9a7SVivek Gautam 490b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC1_SUSPEND BIT(12) 500b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC1_PWR BIT(13) 510b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC1_SLEEP BIT(14) 520b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC1 ( \ 530b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_HSIC1_SUSPEND | \ 540b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_HSIC1_PWR | \ 550b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_HSIC1_SLEEP) 560b56e9a7SVivek Gautam 570b56e9a7SVivek Gautam /* PHY clock control */ 580b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK 0x4 590b56e9a7SVivek Gautam 600b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK (0x7 << 0) 610b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET 0 620b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6 (0x0 << 0) 630b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ (0x1 << 0) 640b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0) 650b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2 (0x3 << 0) 660b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ (0x4 << 0) 670b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ (0x5 << 0) 680b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ (0x7 << 0) 690b56e9a7SVivek Gautam 700b56e9a7SVivek Gautam #define EXYNOS_3250_UPHYCLK_REFCLKSEL (0x2 << 8) 710b56e9a7SVivek Gautam 720b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHY0_ID_PULLUP BIT(3) 730b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHY0_COMMON_ON BIT(4) 740b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON BIT(7) 750b56e9a7SVivek Gautam 760b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_MASK (0x7f << 10) 770b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_OFFSET 10 780b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_12MHZ (0x24 << 10) 790b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_15MHZ (0x1c << 10) 800b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_16MHZ (0x1a << 10) 810b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_19MHZ2 (0x15 << 10) 820b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_20MHZ (0x14 << 10) 830b56e9a7SVivek Gautam 840b56e9a7SVivek Gautam /* PHY reset control */ 850b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYRST 0x8 860b56e9a7SVivek Gautam 870b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_PHY0 BIT(0) 880b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_OTG_HLINK BIT(1) 890b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_OTG_PHYLINK BIT(2) 900b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HOST_PHY BIT(3) 910b56e9a7SVivek Gautam /* The following bit defines are presented in the 920b56e9a7SVivek Gautam * order taken from the Exynos4412 reference manual. 930b56e9a7SVivek Gautam * 940b56e9a7SVivek Gautam * During experiments with the hardware and debugging 950b56e9a7SVivek Gautam * it was determined that the hardware behaves contrary 960b56e9a7SVivek Gautam * to the manual. 970b56e9a7SVivek Gautam * 980b56e9a7SVivek Gautam * The following bit values were chaned accordingly to the 990b56e9a7SVivek Gautam * results of real hardware experiments. 1000b56e9a7SVivek Gautam */ 1010b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_PHY1 BIT(4) 1020b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HSIC0 BIT(6) 1030b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HSIC1 BIT(5) 1040b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HOST_LINK_ALL BIT(7) 1050b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HOST_LINK_P0 BIT(10) 1060b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HOST_LINK_P1 BIT(9) 1070b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HOST_LINK_P2 BIT(8) 1080b56e9a7SVivek Gautam 1090b56e9a7SVivek Gautam /* Isolation, configured in the power management unit */ 1100b56e9a7SVivek Gautam #define EXYNOS_4x12_USB_ISOL_OFFSET 0x704 1110b56e9a7SVivek Gautam #define EXYNOS_4x12_USB_ISOL_OTG BIT(0) 1120b56e9a7SVivek Gautam #define EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET 0x708 1130b56e9a7SVivek Gautam #define EXYNOS_4x12_USB_ISOL_HSIC0 BIT(0) 1140b56e9a7SVivek Gautam #define EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET 0x70c 1150b56e9a7SVivek Gautam #define EXYNOS_4x12_USB_ISOL_HSIC1 BIT(0) 1160b56e9a7SVivek Gautam 1170b56e9a7SVivek Gautam /* Mode switching SUB Device <-> Host */ 1180b56e9a7SVivek Gautam #define EXYNOS_4x12_MODE_SWITCH_OFFSET 0x21c 1190b56e9a7SVivek Gautam #define EXYNOS_4x12_MODE_SWITCH_MASK 1 1200b56e9a7SVivek Gautam #define EXYNOS_4x12_MODE_SWITCH_DEVICE 0 1210b56e9a7SVivek Gautam #define EXYNOS_4x12_MODE_SWITCH_HOST 1 1220b56e9a7SVivek Gautam 1230b56e9a7SVivek Gautam enum exynos4x12_phy_id { 1240b56e9a7SVivek Gautam EXYNOS4x12_DEVICE, 1250b56e9a7SVivek Gautam EXYNOS4x12_HOST, 1260b56e9a7SVivek Gautam EXYNOS4x12_HSIC0, 1270b56e9a7SVivek Gautam EXYNOS4x12_HSIC1, 1280b56e9a7SVivek Gautam EXYNOS4x12_NUM_PHYS, 1290b56e9a7SVivek Gautam }; 1300b56e9a7SVivek Gautam 1310b56e9a7SVivek Gautam /* 1320b56e9a7SVivek Gautam * exynos4x12_rate_to_clk() converts the supplied clock rate to the value that 1330b56e9a7SVivek Gautam * can be written to the phy register. 1340b56e9a7SVivek Gautam */ 1350b56e9a7SVivek Gautam static int exynos4x12_rate_to_clk(unsigned long rate, u32 *reg) 1360b56e9a7SVivek Gautam { 1370b56e9a7SVivek Gautam /* EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK */ 1380b56e9a7SVivek Gautam 1390b56e9a7SVivek Gautam switch (rate) { 1400b56e9a7SVivek Gautam case 9600 * KHZ: 1410b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6; 1420b56e9a7SVivek Gautam break; 1430b56e9a7SVivek Gautam case 10 * MHZ: 1440b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ; 1450b56e9a7SVivek Gautam break; 1460b56e9a7SVivek Gautam case 12 * MHZ: 1470b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ; 1480b56e9a7SVivek Gautam break; 1490b56e9a7SVivek Gautam case 19200 * KHZ: 1500b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2; 1510b56e9a7SVivek Gautam break; 1520b56e9a7SVivek Gautam case 20 * MHZ: 1530b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ; 1540b56e9a7SVivek Gautam break; 1550b56e9a7SVivek Gautam case 24 * MHZ: 1560b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ; 1570b56e9a7SVivek Gautam break; 1580b56e9a7SVivek Gautam case 50 * MHZ: 1590b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ; 1600b56e9a7SVivek Gautam break; 1610b56e9a7SVivek Gautam default: 1620b56e9a7SVivek Gautam return -EINVAL; 1630b56e9a7SVivek Gautam } 1640b56e9a7SVivek Gautam 1650b56e9a7SVivek Gautam return 0; 1660b56e9a7SVivek Gautam } 1670b56e9a7SVivek Gautam 1680b56e9a7SVivek Gautam static void exynos4x12_isol(struct samsung_usb2_phy_instance *inst, bool on) 1690b56e9a7SVivek Gautam { 1700b56e9a7SVivek Gautam struct samsung_usb2_phy_driver *drv = inst->drv; 1710b56e9a7SVivek Gautam u32 offset; 1720b56e9a7SVivek Gautam u32 mask; 1730b56e9a7SVivek Gautam 1740b56e9a7SVivek Gautam switch (inst->cfg->id) { 1750b56e9a7SVivek Gautam case EXYNOS4x12_DEVICE: 1760b56e9a7SVivek Gautam case EXYNOS4x12_HOST: 1770b56e9a7SVivek Gautam offset = EXYNOS_4x12_USB_ISOL_OFFSET; 1780b56e9a7SVivek Gautam mask = EXYNOS_4x12_USB_ISOL_OTG; 1790b56e9a7SVivek Gautam break; 1800b56e9a7SVivek Gautam case EXYNOS4x12_HSIC0: 1810b56e9a7SVivek Gautam offset = EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET; 1820b56e9a7SVivek Gautam mask = EXYNOS_4x12_USB_ISOL_HSIC0; 1830b56e9a7SVivek Gautam break; 1840b56e9a7SVivek Gautam case EXYNOS4x12_HSIC1: 1850b56e9a7SVivek Gautam offset = EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET; 1860b56e9a7SVivek Gautam mask = EXYNOS_4x12_USB_ISOL_HSIC1; 1870b56e9a7SVivek Gautam break; 1880b56e9a7SVivek Gautam default: 1890b56e9a7SVivek Gautam return; 1900b56e9a7SVivek Gautam } 1910b56e9a7SVivek Gautam 1920b56e9a7SVivek Gautam regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask); 1930b56e9a7SVivek Gautam } 1940b56e9a7SVivek Gautam 1950b56e9a7SVivek Gautam static void exynos4x12_setup_clk(struct samsung_usb2_phy_instance *inst) 1960b56e9a7SVivek Gautam { 1970b56e9a7SVivek Gautam struct samsung_usb2_phy_driver *drv = inst->drv; 1980b56e9a7SVivek Gautam u32 clk; 1990b56e9a7SVivek Gautam 2000b56e9a7SVivek Gautam clk = readl(drv->reg_phy + EXYNOS_4x12_UPHYCLK); 2010b56e9a7SVivek Gautam clk &= ~EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK; 2020b56e9a7SVivek Gautam 2030b56e9a7SVivek Gautam if (drv->cfg->has_refclk_sel) 2040b56e9a7SVivek Gautam clk = EXYNOS_3250_UPHYCLK_REFCLKSEL; 2050b56e9a7SVivek Gautam 2060b56e9a7SVivek Gautam clk |= drv->ref_reg_val << EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET; 2070b56e9a7SVivek Gautam clk |= EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON; 2080b56e9a7SVivek Gautam writel(clk, drv->reg_phy + EXYNOS_4x12_UPHYCLK); 2090b56e9a7SVivek Gautam } 2100b56e9a7SVivek Gautam 2110b56e9a7SVivek Gautam static void exynos4x12_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on) 2120b56e9a7SVivek Gautam { 2130b56e9a7SVivek Gautam struct samsung_usb2_phy_driver *drv = inst->drv; 2140b56e9a7SVivek Gautam u32 rstbits = 0; 2150b56e9a7SVivek Gautam u32 phypwr = 0; 2160b56e9a7SVivek Gautam u32 rst; 2170b56e9a7SVivek Gautam u32 pwr; 2180b56e9a7SVivek Gautam 2190b56e9a7SVivek Gautam switch (inst->cfg->id) { 2200b56e9a7SVivek Gautam case EXYNOS4x12_DEVICE: 2210b56e9a7SVivek Gautam phypwr = EXYNOS_4x12_UPHYPWR_PHY0; 2220b56e9a7SVivek Gautam rstbits = EXYNOS_4x12_URSTCON_PHY0; 2230b56e9a7SVivek Gautam break; 2240b56e9a7SVivek Gautam case EXYNOS4x12_HOST: 2250b56e9a7SVivek Gautam phypwr = EXYNOS_4x12_UPHYPWR_PHY1; 2260b56e9a7SVivek Gautam rstbits = EXYNOS_4x12_URSTCON_HOST_PHY | 2270b56e9a7SVivek Gautam EXYNOS_4x12_URSTCON_PHY1 | 2280b56e9a7SVivek Gautam EXYNOS_4x12_URSTCON_HOST_LINK_P0; 2290b56e9a7SVivek Gautam break; 2300b56e9a7SVivek Gautam case EXYNOS4x12_HSIC0: 2310b56e9a7SVivek Gautam phypwr = EXYNOS_4x12_UPHYPWR_HSIC0; 2320b56e9a7SVivek Gautam rstbits = EXYNOS_4x12_URSTCON_HSIC0 | 2330b56e9a7SVivek Gautam EXYNOS_4x12_URSTCON_HOST_LINK_P1; 2340b56e9a7SVivek Gautam break; 2350b56e9a7SVivek Gautam case EXYNOS4x12_HSIC1: 2360b56e9a7SVivek Gautam phypwr = EXYNOS_4x12_UPHYPWR_HSIC1; 2370b56e9a7SVivek Gautam rstbits = EXYNOS_4x12_URSTCON_HSIC1 | 2380b56e9a7SVivek Gautam EXYNOS_4x12_URSTCON_HOST_LINK_P1; 2390b56e9a7SVivek Gautam break; 2400b56e9a7SVivek Gautam } 2410b56e9a7SVivek Gautam 2420b56e9a7SVivek Gautam if (on) { 2430b56e9a7SVivek Gautam pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR); 2440b56e9a7SVivek Gautam pwr &= ~phypwr; 2450b56e9a7SVivek Gautam writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR); 2460b56e9a7SVivek Gautam 2470b56e9a7SVivek Gautam rst = readl(drv->reg_phy + EXYNOS_4x12_UPHYRST); 2480b56e9a7SVivek Gautam rst |= rstbits; 2490b56e9a7SVivek Gautam writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST); 2500b56e9a7SVivek Gautam udelay(10); 2510b56e9a7SVivek Gautam rst &= ~rstbits; 2520b56e9a7SVivek Gautam writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST); 2530b56e9a7SVivek Gautam /* The following delay is necessary for the reset sequence to be 2540b56e9a7SVivek Gautam * completed */ 2550b56e9a7SVivek Gautam udelay(80); 2560b56e9a7SVivek Gautam } else { 2570b56e9a7SVivek Gautam pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR); 2580b56e9a7SVivek Gautam pwr |= phypwr; 2590b56e9a7SVivek Gautam writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR); 2600b56e9a7SVivek Gautam } 2610b56e9a7SVivek Gautam } 2620b56e9a7SVivek Gautam 2630b56e9a7SVivek Gautam static void exynos4x12_power_on_int(struct samsung_usb2_phy_instance *inst) 2640b56e9a7SVivek Gautam { 2650b56e9a7SVivek Gautam if (inst->int_cnt++ > 0) 2660b56e9a7SVivek Gautam return; 2670b56e9a7SVivek Gautam 2680b56e9a7SVivek Gautam exynos4x12_setup_clk(inst); 2690b56e9a7SVivek Gautam exynos4x12_isol(inst, 0); 2700b56e9a7SVivek Gautam exynos4x12_phy_pwr(inst, 1); 2710b56e9a7SVivek Gautam } 2720b56e9a7SVivek Gautam 2730b56e9a7SVivek Gautam static int exynos4x12_power_on(struct samsung_usb2_phy_instance *inst) 2740b56e9a7SVivek Gautam { 2750b56e9a7SVivek Gautam struct samsung_usb2_phy_driver *drv = inst->drv; 2760b56e9a7SVivek Gautam 2770b56e9a7SVivek Gautam if (inst->ext_cnt++ > 0) 2780b56e9a7SVivek Gautam return 0; 2790b56e9a7SVivek Gautam 2800b56e9a7SVivek Gautam if (inst->cfg->id == EXYNOS4x12_HOST) { 2810b56e9a7SVivek Gautam regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET, 2820b56e9a7SVivek Gautam EXYNOS_4x12_MODE_SWITCH_MASK, 2830b56e9a7SVivek Gautam EXYNOS_4x12_MODE_SWITCH_HOST); 2840b56e9a7SVivek Gautam exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_DEVICE]); 2850b56e9a7SVivek Gautam } 2860b56e9a7SVivek Gautam 2870b56e9a7SVivek Gautam if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch) 2880b56e9a7SVivek Gautam regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET, 2890b56e9a7SVivek Gautam EXYNOS_4x12_MODE_SWITCH_MASK, 2900b56e9a7SVivek Gautam EXYNOS_4x12_MODE_SWITCH_DEVICE); 2910b56e9a7SVivek Gautam 2920b56e9a7SVivek Gautam if (inst->cfg->id == EXYNOS4x12_HSIC0 || 2930b56e9a7SVivek Gautam inst->cfg->id == EXYNOS4x12_HSIC1) { 2940b56e9a7SVivek Gautam exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_DEVICE]); 2950b56e9a7SVivek Gautam exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_HOST]); 2960b56e9a7SVivek Gautam } 2970b56e9a7SVivek Gautam 2980b56e9a7SVivek Gautam exynos4x12_power_on_int(inst); 2990b56e9a7SVivek Gautam 3000b56e9a7SVivek Gautam return 0; 3010b56e9a7SVivek Gautam } 3020b56e9a7SVivek Gautam 3030b56e9a7SVivek Gautam static void exynos4x12_power_off_int(struct samsung_usb2_phy_instance *inst) 3040b56e9a7SVivek Gautam { 3050b56e9a7SVivek Gautam if (inst->int_cnt-- > 1) 3060b56e9a7SVivek Gautam return; 3070b56e9a7SVivek Gautam 3080b56e9a7SVivek Gautam exynos4x12_isol(inst, 1); 3090b56e9a7SVivek Gautam exynos4x12_phy_pwr(inst, 0); 3100b56e9a7SVivek Gautam } 3110b56e9a7SVivek Gautam 3120b56e9a7SVivek Gautam static int exynos4x12_power_off(struct samsung_usb2_phy_instance *inst) 3130b56e9a7SVivek Gautam { 3140b56e9a7SVivek Gautam struct samsung_usb2_phy_driver *drv = inst->drv; 3150b56e9a7SVivek Gautam 3160b56e9a7SVivek Gautam if (inst->ext_cnt-- > 1) 3170b56e9a7SVivek Gautam return 0; 3180b56e9a7SVivek Gautam 3190b56e9a7SVivek Gautam if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch) 3200b56e9a7SVivek Gautam regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET, 3210b56e9a7SVivek Gautam EXYNOS_4x12_MODE_SWITCH_MASK, 3220b56e9a7SVivek Gautam EXYNOS_4x12_MODE_SWITCH_HOST); 3230b56e9a7SVivek Gautam 3240b56e9a7SVivek Gautam if (inst->cfg->id == EXYNOS4x12_HOST) 3250b56e9a7SVivek Gautam exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_DEVICE]); 3260b56e9a7SVivek Gautam 3270b56e9a7SVivek Gautam if (inst->cfg->id == EXYNOS4x12_HSIC0 || 3280b56e9a7SVivek Gautam inst->cfg->id == EXYNOS4x12_HSIC1) { 3290b56e9a7SVivek Gautam exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_DEVICE]); 3300b56e9a7SVivek Gautam exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_HOST]); 3310b56e9a7SVivek Gautam } 3320b56e9a7SVivek Gautam 3330b56e9a7SVivek Gautam exynos4x12_power_off_int(inst); 3340b56e9a7SVivek Gautam 3350b56e9a7SVivek Gautam return 0; 3360b56e9a7SVivek Gautam } 3370b56e9a7SVivek Gautam 3380b56e9a7SVivek Gautam 3390b56e9a7SVivek Gautam static const struct samsung_usb2_common_phy exynos4x12_phys[] = { 3400b56e9a7SVivek Gautam { 3410b56e9a7SVivek Gautam .label = "device", 3420b56e9a7SVivek Gautam .id = EXYNOS4x12_DEVICE, 3430b56e9a7SVivek Gautam .power_on = exynos4x12_power_on, 3440b56e9a7SVivek Gautam .power_off = exynos4x12_power_off, 3450b56e9a7SVivek Gautam }, 3460b56e9a7SVivek Gautam { 3470b56e9a7SVivek Gautam .label = "host", 3480b56e9a7SVivek Gautam .id = EXYNOS4x12_HOST, 3490b56e9a7SVivek Gautam .power_on = exynos4x12_power_on, 3500b56e9a7SVivek Gautam .power_off = exynos4x12_power_off, 3510b56e9a7SVivek Gautam }, 3520b56e9a7SVivek Gautam { 3530b56e9a7SVivek Gautam .label = "hsic0", 3540b56e9a7SVivek Gautam .id = EXYNOS4x12_HSIC0, 3550b56e9a7SVivek Gautam .power_on = exynos4x12_power_on, 3560b56e9a7SVivek Gautam .power_off = exynos4x12_power_off, 3570b56e9a7SVivek Gautam }, 3580b56e9a7SVivek Gautam { 3590b56e9a7SVivek Gautam .label = "hsic1", 3600b56e9a7SVivek Gautam .id = EXYNOS4x12_HSIC1, 3610b56e9a7SVivek Gautam .power_on = exynos4x12_power_on, 3620b56e9a7SVivek Gautam .power_off = exynos4x12_power_off, 3630b56e9a7SVivek Gautam }, 3640b56e9a7SVivek Gautam }; 3650b56e9a7SVivek Gautam 3660b56e9a7SVivek Gautam const struct samsung_usb2_phy_config exynos3250_usb2_phy_config = { 3670b56e9a7SVivek Gautam .has_refclk_sel = 1, 3680b56e9a7SVivek Gautam .num_phys = 1, 3690b56e9a7SVivek Gautam .phys = exynos4x12_phys, 3700b56e9a7SVivek Gautam .rate_to_clk = exynos4x12_rate_to_clk, 3710b56e9a7SVivek Gautam }; 3720b56e9a7SVivek Gautam 3730b56e9a7SVivek Gautam const struct samsung_usb2_phy_config exynos4x12_usb2_phy_config = { 3740b56e9a7SVivek Gautam .has_mode_switch = 1, 3750b56e9a7SVivek Gautam .num_phys = EXYNOS4x12_NUM_PHYS, 3760b56e9a7SVivek Gautam .phys = exynos4x12_phys, 3770b56e9a7SVivek Gautam .rate_to_clk = exynos4x12_rate_to_clk, 3780b56e9a7SVivek Gautam }; 379