1d2912cb1SThomas Gleixner // SPDX-License-Identifier: GPL-2.0-only
20b56e9a7SVivek Gautam /*
30b56e9a7SVivek Gautam * Samsung SoC USB 1.1/2.0 PHY driver - Exynos 4x12 support
40b56e9a7SVivek Gautam *
50b56e9a7SVivek Gautam * Copyright (C) 2013 Samsung Electronics Co., Ltd.
60b56e9a7SVivek Gautam * Author: Kamil Debski <k.debski@samsung.com>
70b56e9a7SVivek Gautam */
80b56e9a7SVivek Gautam
90b56e9a7SVivek Gautam #include <linux/delay.h>
100b56e9a7SVivek Gautam #include <linux/io.h>
110b56e9a7SVivek Gautam #include <linux/phy/phy.h>
120b56e9a7SVivek Gautam #include <linux/regmap.h>
130b56e9a7SVivek Gautam #include "phy-samsung-usb2.h"
140b56e9a7SVivek Gautam
150b56e9a7SVivek Gautam /* Exynos USB PHY registers */
160b56e9a7SVivek Gautam
170b56e9a7SVivek Gautam /* PHY power control */
180b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR 0x0
190b56e9a7SVivek Gautam
200b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND BIT(0)
210b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY0_PWR BIT(3)
220b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR BIT(4)
230b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY0_SLEEP BIT(5)
240b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY0 ( \
250b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY0_SUSPEND | \
260b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY0_PWR | \
270b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY0_OTG_PWR | \
280b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY0_SLEEP)
290b56e9a7SVivek Gautam
300b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND BIT(6)
310b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY1_PWR BIT(7)
320b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY1_SLEEP BIT(8)
330b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_PHY1 ( \
340b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY1_SUSPEND | \
350b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY1_PWR | \
360b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_PHY1_SLEEP)
370b56e9a7SVivek Gautam
380b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC0_SUSPEND BIT(9)
390b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC0_PWR BIT(10)
400b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC0_SLEEP BIT(11)
410b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC0 ( \
420b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_HSIC0_SUSPEND | \
430b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_HSIC0_PWR | \
440b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_HSIC0_SLEEP)
450b56e9a7SVivek Gautam
460b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC1_SUSPEND BIT(12)
470b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC1_PWR BIT(13)
480b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC1_SLEEP BIT(14)
490b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYPWR_HSIC1 ( \
500b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_HSIC1_SUSPEND | \
510b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_HSIC1_PWR | \
520b56e9a7SVivek Gautam EXYNOS_4x12_UPHYPWR_HSIC1_SLEEP)
530b56e9a7SVivek Gautam
540b56e9a7SVivek Gautam /* PHY clock control */
550b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK 0x4
560b56e9a7SVivek Gautam
570b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK (0x7 << 0)
580b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET 0
590b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6 (0x0 << 0)
600b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ (0x1 << 0)
610b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ (0x2 << 0)
620b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2 (0x3 << 0)
630b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ (0x4 << 0)
640b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ (0x5 << 0)
650b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ (0x7 << 0)
660b56e9a7SVivek Gautam
670b56e9a7SVivek Gautam #define EXYNOS_3250_UPHYCLK_REFCLKSEL (0x2 << 8)
680b56e9a7SVivek Gautam
690b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHY0_ID_PULLUP BIT(3)
700b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHY0_COMMON_ON BIT(4)
710b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON BIT(7)
720b56e9a7SVivek Gautam
730b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_MASK (0x7f << 10)
740b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_OFFSET 10
750b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_12MHZ (0x24 << 10)
760b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_15MHZ (0x1c << 10)
770b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_16MHZ (0x1a << 10)
780b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_19MHZ2 (0x15 << 10)
790b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYCLK_HSIC_REFCLK_20MHZ (0x14 << 10)
800b56e9a7SVivek Gautam
810b56e9a7SVivek Gautam /* PHY reset control */
820b56e9a7SVivek Gautam #define EXYNOS_4x12_UPHYRST 0x8
830b56e9a7SVivek Gautam
840b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_PHY0 BIT(0)
850b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_OTG_HLINK BIT(1)
860b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_OTG_PHYLINK BIT(2)
870b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HOST_PHY BIT(3)
880b56e9a7SVivek Gautam /* The following bit defines are presented in the
890b56e9a7SVivek Gautam * order taken from the Exynos4412 reference manual.
900b56e9a7SVivek Gautam *
910b56e9a7SVivek Gautam * During experiments with the hardware and debugging
920b56e9a7SVivek Gautam * it was determined that the hardware behaves contrary
930b56e9a7SVivek Gautam * to the manual.
940b56e9a7SVivek Gautam *
950b56e9a7SVivek Gautam * The following bit values were chaned accordingly to the
960b56e9a7SVivek Gautam * results of real hardware experiments.
970b56e9a7SVivek Gautam */
980b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_PHY1 BIT(4)
990b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HSIC0 BIT(6)
1000b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HSIC1 BIT(5)
1010b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HOST_LINK_ALL BIT(7)
1020b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HOST_LINK_P0 BIT(10)
1030b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HOST_LINK_P1 BIT(9)
1040b56e9a7SVivek Gautam #define EXYNOS_4x12_URSTCON_HOST_LINK_P2 BIT(8)
1050b56e9a7SVivek Gautam
1060b56e9a7SVivek Gautam /* Isolation, configured in the power management unit */
1070b56e9a7SVivek Gautam #define EXYNOS_4x12_USB_ISOL_OFFSET 0x704
1080b56e9a7SVivek Gautam #define EXYNOS_4x12_USB_ISOL_OTG BIT(0)
1090b56e9a7SVivek Gautam #define EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET 0x708
1100b56e9a7SVivek Gautam #define EXYNOS_4x12_USB_ISOL_HSIC0 BIT(0)
1110b56e9a7SVivek Gautam #define EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET 0x70c
1120b56e9a7SVivek Gautam #define EXYNOS_4x12_USB_ISOL_HSIC1 BIT(0)
1130b56e9a7SVivek Gautam
1140b56e9a7SVivek Gautam /* Mode switching SUB Device <-> Host */
1150b56e9a7SVivek Gautam #define EXYNOS_4x12_MODE_SWITCH_OFFSET 0x21c
1160b56e9a7SVivek Gautam #define EXYNOS_4x12_MODE_SWITCH_MASK 1
1170b56e9a7SVivek Gautam #define EXYNOS_4x12_MODE_SWITCH_DEVICE 0
1180b56e9a7SVivek Gautam #define EXYNOS_4x12_MODE_SWITCH_HOST 1
1190b56e9a7SVivek Gautam
1200b56e9a7SVivek Gautam enum exynos4x12_phy_id {
1210b56e9a7SVivek Gautam EXYNOS4x12_DEVICE,
1220b56e9a7SVivek Gautam EXYNOS4x12_HOST,
1230b56e9a7SVivek Gautam EXYNOS4x12_HSIC0,
1240b56e9a7SVivek Gautam EXYNOS4x12_HSIC1,
1250b56e9a7SVivek Gautam EXYNOS4x12_NUM_PHYS,
1260b56e9a7SVivek Gautam };
1270b56e9a7SVivek Gautam
1280b56e9a7SVivek Gautam /*
1290b56e9a7SVivek Gautam * exynos4x12_rate_to_clk() converts the supplied clock rate to the value that
1300b56e9a7SVivek Gautam * can be written to the phy register.
1310b56e9a7SVivek Gautam */
exynos4x12_rate_to_clk(unsigned long rate,u32 * reg)1320b56e9a7SVivek Gautam static int exynos4x12_rate_to_clk(unsigned long rate, u32 *reg)
1330b56e9a7SVivek Gautam {
1340b56e9a7SVivek Gautam /* EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK */
1350b56e9a7SVivek Gautam
1360b56e9a7SVivek Gautam switch (rate) {
1370b56e9a7SVivek Gautam case 9600 * KHZ:
1380b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_9MHZ6;
1390b56e9a7SVivek Gautam break;
1400b56e9a7SVivek Gautam case 10 * MHZ:
1410b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_10MHZ;
1420b56e9a7SVivek Gautam break;
1430b56e9a7SVivek Gautam case 12 * MHZ:
1440b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_12MHZ;
1450b56e9a7SVivek Gautam break;
1460b56e9a7SVivek Gautam case 19200 * KHZ:
1470b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_19MHZ2;
1480b56e9a7SVivek Gautam break;
1490b56e9a7SVivek Gautam case 20 * MHZ:
1500b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_20MHZ;
1510b56e9a7SVivek Gautam break;
1520b56e9a7SVivek Gautam case 24 * MHZ:
1530b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_24MHZ;
1540b56e9a7SVivek Gautam break;
1550b56e9a7SVivek Gautam case 50 * MHZ:
1560b56e9a7SVivek Gautam *reg = EXYNOS_4x12_UPHYCLK_PHYFSEL_50MHZ;
1570b56e9a7SVivek Gautam break;
1580b56e9a7SVivek Gautam default:
1590b56e9a7SVivek Gautam return -EINVAL;
1600b56e9a7SVivek Gautam }
1610b56e9a7SVivek Gautam
1620b56e9a7SVivek Gautam return 0;
1630b56e9a7SVivek Gautam }
1640b56e9a7SVivek Gautam
exynos4x12_isol(struct samsung_usb2_phy_instance * inst,bool on)1650b56e9a7SVivek Gautam static void exynos4x12_isol(struct samsung_usb2_phy_instance *inst, bool on)
1660b56e9a7SVivek Gautam {
1670b56e9a7SVivek Gautam struct samsung_usb2_phy_driver *drv = inst->drv;
1680b56e9a7SVivek Gautam u32 offset;
1690b56e9a7SVivek Gautam u32 mask;
1700b56e9a7SVivek Gautam
1710b56e9a7SVivek Gautam switch (inst->cfg->id) {
1720b56e9a7SVivek Gautam case EXYNOS4x12_DEVICE:
1730b56e9a7SVivek Gautam case EXYNOS4x12_HOST:
1740b56e9a7SVivek Gautam offset = EXYNOS_4x12_USB_ISOL_OFFSET;
1750b56e9a7SVivek Gautam mask = EXYNOS_4x12_USB_ISOL_OTG;
1760b56e9a7SVivek Gautam break;
1770b56e9a7SVivek Gautam case EXYNOS4x12_HSIC0:
1780b56e9a7SVivek Gautam offset = EXYNOS_4x12_USB_ISOL_HSIC0_OFFSET;
1790b56e9a7SVivek Gautam mask = EXYNOS_4x12_USB_ISOL_HSIC0;
1800b56e9a7SVivek Gautam break;
1810b56e9a7SVivek Gautam case EXYNOS4x12_HSIC1:
1820b56e9a7SVivek Gautam offset = EXYNOS_4x12_USB_ISOL_HSIC1_OFFSET;
1830b56e9a7SVivek Gautam mask = EXYNOS_4x12_USB_ISOL_HSIC1;
1840b56e9a7SVivek Gautam break;
1850b56e9a7SVivek Gautam default:
1860b56e9a7SVivek Gautam return;
1870b56e9a7SVivek Gautam }
1880b56e9a7SVivek Gautam
1890b56e9a7SVivek Gautam regmap_update_bits(drv->reg_pmu, offset, mask, on ? 0 : mask);
1900b56e9a7SVivek Gautam }
1910b56e9a7SVivek Gautam
exynos4x12_setup_clk(struct samsung_usb2_phy_instance * inst)1920b56e9a7SVivek Gautam static void exynos4x12_setup_clk(struct samsung_usb2_phy_instance *inst)
1930b56e9a7SVivek Gautam {
1940b56e9a7SVivek Gautam struct samsung_usb2_phy_driver *drv = inst->drv;
1950b56e9a7SVivek Gautam u32 clk;
1960b56e9a7SVivek Gautam
1970b56e9a7SVivek Gautam clk = readl(drv->reg_phy + EXYNOS_4x12_UPHYCLK);
1980b56e9a7SVivek Gautam clk &= ~EXYNOS_4x12_UPHYCLK_PHYFSEL_MASK;
1990b56e9a7SVivek Gautam
2000b56e9a7SVivek Gautam if (drv->cfg->has_refclk_sel)
2010b56e9a7SVivek Gautam clk = EXYNOS_3250_UPHYCLK_REFCLKSEL;
2020b56e9a7SVivek Gautam
2030b56e9a7SVivek Gautam clk |= drv->ref_reg_val << EXYNOS_4x12_UPHYCLK_PHYFSEL_OFFSET;
2040b56e9a7SVivek Gautam clk |= EXYNOS_4x12_UPHYCLK_PHY1_COMMON_ON;
2050b56e9a7SVivek Gautam writel(clk, drv->reg_phy + EXYNOS_4x12_UPHYCLK);
2060b56e9a7SVivek Gautam }
2070b56e9a7SVivek Gautam
exynos4x12_phy_pwr(struct samsung_usb2_phy_instance * inst,bool on)2080b56e9a7SVivek Gautam static void exynos4x12_phy_pwr(struct samsung_usb2_phy_instance *inst, bool on)
2090b56e9a7SVivek Gautam {
2100b56e9a7SVivek Gautam struct samsung_usb2_phy_driver *drv = inst->drv;
2110b56e9a7SVivek Gautam u32 rstbits = 0;
2120b56e9a7SVivek Gautam u32 phypwr = 0;
2130b56e9a7SVivek Gautam u32 rst;
2140b56e9a7SVivek Gautam u32 pwr;
2150b56e9a7SVivek Gautam
2160b56e9a7SVivek Gautam switch (inst->cfg->id) {
2170b56e9a7SVivek Gautam case EXYNOS4x12_DEVICE:
2180b56e9a7SVivek Gautam phypwr = EXYNOS_4x12_UPHYPWR_PHY0;
2190b56e9a7SVivek Gautam rstbits = EXYNOS_4x12_URSTCON_PHY0;
2200b56e9a7SVivek Gautam break;
2210b56e9a7SVivek Gautam case EXYNOS4x12_HOST:
2220b56e9a7SVivek Gautam phypwr = EXYNOS_4x12_UPHYPWR_PHY1;
2230b56e9a7SVivek Gautam rstbits = EXYNOS_4x12_URSTCON_HOST_PHY |
2240b56e9a7SVivek Gautam EXYNOS_4x12_URSTCON_PHY1 |
2250b56e9a7SVivek Gautam EXYNOS_4x12_URSTCON_HOST_LINK_P0;
2260b56e9a7SVivek Gautam break;
2270b56e9a7SVivek Gautam case EXYNOS4x12_HSIC0:
2280b56e9a7SVivek Gautam phypwr = EXYNOS_4x12_UPHYPWR_HSIC0;
2290b56e9a7SVivek Gautam rstbits = EXYNOS_4x12_URSTCON_HSIC0 |
2300b56e9a7SVivek Gautam EXYNOS_4x12_URSTCON_HOST_LINK_P1;
2310b56e9a7SVivek Gautam break;
2320b56e9a7SVivek Gautam case EXYNOS4x12_HSIC1:
2330b56e9a7SVivek Gautam phypwr = EXYNOS_4x12_UPHYPWR_HSIC1;
2340b56e9a7SVivek Gautam rstbits = EXYNOS_4x12_URSTCON_HSIC1 |
2350b56e9a7SVivek Gautam EXYNOS_4x12_URSTCON_HOST_LINK_P1;
2360b56e9a7SVivek Gautam break;
2370b56e9a7SVivek Gautam }
2380b56e9a7SVivek Gautam
2390b56e9a7SVivek Gautam if (on) {
2400b56e9a7SVivek Gautam pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR);
2410b56e9a7SVivek Gautam pwr &= ~phypwr;
2420b56e9a7SVivek Gautam writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR);
2430b56e9a7SVivek Gautam
2440b56e9a7SVivek Gautam rst = readl(drv->reg_phy + EXYNOS_4x12_UPHYRST);
2450b56e9a7SVivek Gautam rst |= rstbits;
2460b56e9a7SVivek Gautam writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST);
2470b56e9a7SVivek Gautam udelay(10);
2480b56e9a7SVivek Gautam rst &= ~rstbits;
2490b56e9a7SVivek Gautam writel(rst, drv->reg_phy + EXYNOS_4x12_UPHYRST);
2500b56e9a7SVivek Gautam /* The following delay is necessary for the reset sequence to be
2510b56e9a7SVivek Gautam * completed */
2520b56e9a7SVivek Gautam udelay(80);
2530b56e9a7SVivek Gautam } else {
2540b56e9a7SVivek Gautam pwr = readl(drv->reg_phy + EXYNOS_4x12_UPHYPWR);
2550b56e9a7SVivek Gautam pwr |= phypwr;
2560b56e9a7SVivek Gautam writel(pwr, drv->reg_phy + EXYNOS_4x12_UPHYPWR);
2570b56e9a7SVivek Gautam }
2580b56e9a7SVivek Gautam }
2590b56e9a7SVivek Gautam
exynos4x12_power_on_int(struct samsung_usb2_phy_instance * inst)2600b56e9a7SVivek Gautam static void exynos4x12_power_on_int(struct samsung_usb2_phy_instance *inst)
2610b56e9a7SVivek Gautam {
2620b56e9a7SVivek Gautam if (inst->int_cnt++ > 0)
2630b56e9a7SVivek Gautam return;
2640b56e9a7SVivek Gautam
2650b56e9a7SVivek Gautam exynos4x12_setup_clk(inst);
2660b56e9a7SVivek Gautam exynos4x12_isol(inst, 0);
2670b56e9a7SVivek Gautam exynos4x12_phy_pwr(inst, 1);
2680b56e9a7SVivek Gautam }
2690b56e9a7SVivek Gautam
exynos4x12_power_on(struct samsung_usb2_phy_instance * inst)2700b56e9a7SVivek Gautam static int exynos4x12_power_on(struct samsung_usb2_phy_instance *inst)
2710b56e9a7SVivek Gautam {
2720b56e9a7SVivek Gautam struct samsung_usb2_phy_driver *drv = inst->drv;
2730b56e9a7SVivek Gautam
2740b56e9a7SVivek Gautam if (inst->ext_cnt++ > 0)
2750b56e9a7SVivek Gautam return 0;
2760b56e9a7SVivek Gautam
2770b56e9a7SVivek Gautam if (inst->cfg->id == EXYNOS4x12_HOST) {
2780b56e9a7SVivek Gautam regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET,
2790b56e9a7SVivek Gautam EXYNOS_4x12_MODE_SWITCH_MASK,
2800b56e9a7SVivek Gautam EXYNOS_4x12_MODE_SWITCH_HOST);
2810b56e9a7SVivek Gautam exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_DEVICE]);
2820b56e9a7SVivek Gautam }
2830b56e9a7SVivek Gautam
2840b56e9a7SVivek Gautam if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch)
2850b56e9a7SVivek Gautam regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET,
2860b56e9a7SVivek Gautam EXYNOS_4x12_MODE_SWITCH_MASK,
2870b56e9a7SVivek Gautam EXYNOS_4x12_MODE_SWITCH_DEVICE);
2880b56e9a7SVivek Gautam
2890b56e9a7SVivek Gautam if (inst->cfg->id == EXYNOS4x12_HSIC0 ||
2900b56e9a7SVivek Gautam inst->cfg->id == EXYNOS4x12_HSIC1) {
2910b56e9a7SVivek Gautam exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_DEVICE]);
2920b56e9a7SVivek Gautam exynos4x12_power_on_int(&drv->instances[EXYNOS4x12_HOST]);
2930b56e9a7SVivek Gautam }
2940b56e9a7SVivek Gautam
2950b56e9a7SVivek Gautam exynos4x12_power_on_int(inst);
2960b56e9a7SVivek Gautam
2970b56e9a7SVivek Gautam return 0;
2980b56e9a7SVivek Gautam }
2990b56e9a7SVivek Gautam
exynos4x12_power_off_int(struct samsung_usb2_phy_instance * inst)3000b56e9a7SVivek Gautam static void exynos4x12_power_off_int(struct samsung_usb2_phy_instance *inst)
3010b56e9a7SVivek Gautam {
3020b56e9a7SVivek Gautam if (inst->int_cnt-- > 1)
3030b56e9a7SVivek Gautam return;
3040b56e9a7SVivek Gautam
3050b56e9a7SVivek Gautam exynos4x12_isol(inst, 1);
3060b56e9a7SVivek Gautam exynos4x12_phy_pwr(inst, 0);
3070b56e9a7SVivek Gautam }
3080b56e9a7SVivek Gautam
exynos4x12_power_off(struct samsung_usb2_phy_instance * inst)3090b56e9a7SVivek Gautam static int exynos4x12_power_off(struct samsung_usb2_phy_instance *inst)
3100b56e9a7SVivek Gautam {
3110b56e9a7SVivek Gautam struct samsung_usb2_phy_driver *drv = inst->drv;
3120b56e9a7SVivek Gautam
3130b56e9a7SVivek Gautam if (inst->ext_cnt-- > 1)
3140b56e9a7SVivek Gautam return 0;
3150b56e9a7SVivek Gautam
3160b56e9a7SVivek Gautam if (inst->cfg->id == EXYNOS4x12_DEVICE && drv->cfg->has_mode_switch)
3170b56e9a7SVivek Gautam regmap_update_bits(drv->reg_sys, EXYNOS_4x12_MODE_SWITCH_OFFSET,
3180b56e9a7SVivek Gautam EXYNOS_4x12_MODE_SWITCH_MASK,
3190b56e9a7SVivek Gautam EXYNOS_4x12_MODE_SWITCH_HOST);
3200b56e9a7SVivek Gautam
3210b56e9a7SVivek Gautam if (inst->cfg->id == EXYNOS4x12_HOST)
3220b56e9a7SVivek Gautam exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_DEVICE]);
3230b56e9a7SVivek Gautam
3240b56e9a7SVivek Gautam if (inst->cfg->id == EXYNOS4x12_HSIC0 ||
3250b56e9a7SVivek Gautam inst->cfg->id == EXYNOS4x12_HSIC1) {
3260b56e9a7SVivek Gautam exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_DEVICE]);
3270b56e9a7SVivek Gautam exynos4x12_power_off_int(&drv->instances[EXYNOS4x12_HOST]);
3280b56e9a7SVivek Gautam }
3290b56e9a7SVivek Gautam
3300b56e9a7SVivek Gautam exynos4x12_power_off_int(inst);
3310b56e9a7SVivek Gautam
3320b56e9a7SVivek Gautam return 0;
3330b56e9a7SVivek Gautam }
3340b56e9a7SVivek Gautam
3350b56e9a7SVivek Gautam
3360b56e9a7SVivek Gautam static const struct samsung_usb2_common_phy exynos4x12_phys[] = {
3370b56e9a7SVivek Gautam {
3380b56e9a7SVivek Gautam .label = "device",
3390b56e9a7SVivek Gautam .id = EXYNOS4x12_DEVICE,
3400b56e9a7SVivek Gautam .power_on = exynos4x12_power_on,
3410b56e9a7SVivek Gautam .power_off = exynos4x12_power_off,
3420b56e9a7SVivek Gautam },
3430b56e9a7SVivek Gautam {
3440b56e9a7SVivek Gautam .label = "host",
3450b56e9a7SVivek Gautam .id = EXYNOS4x12_HOST,
3460b56e9a7SVivek Gautam .power_on = exynos4x12_power_on,
3470b56e9a7SVivek Gautam .power_off = exynos4x12_power_off,
3480b56e9a7SVivek Gautam },
3490b56e9a7SVivek Gautam {
3500b56e9a7SVivek Gautam .label = "hsic0",
3510b56e9a7SVivek Gautam .id = EXYNOS4x12_HSIC0,
3520b56e9a7SVivek Gautam .power_on = exynos4x12_power_on,
3530b56e9a7SVivek Gautam .power_off = exynos4x12_power_off,
3540b56e9a7SVivek Gautam },
3550b56e9a7SVivek Gautam {
3560b56e9a7SVivek Gautam .label = "hsic1",
3570b56e9a7SVivek Gautam .id = EXYNOS4x12_HSIC1,
3580b56e9a7SVivek Gautam .power_on = exynos4x12_power_on,
3590b56e9a7SVivek Gautam .power_off = exynos4x12_power_off,
3600b56e9a7SVivek Gautam },
3610b56e9a7SVivek Gautam };
3620b56e9a7SVivek Gautam
3630b56e9a7SVivek Gautam const struct samsung_usb2_phy_config exynos3250_usb2_phy_config = {
3640b56e9a7SVivek Gautam .has_refclk_sel = 1,
3650b56e9a7SVivek Gautam .num_phys = 1,
3660b56e9a7SVivek Gautam .phys = exynos4x12_phys,
3670b56e9a7SVivek Gautam .rate_to_clk = exynos4x12_rate_to_clk,
3680b56e9a7SVivek Gautam };
3690b56e9a7SVivek Gautam
3700b56e9a7SVivek Gautam const struct samsung_usb2_phy_config exynos4x12_usb2_phy_config = {
3710b56e9a7SVivek Gautam .has_mode_switch = 1,
3720b56e9a7SVivek Gautam .num_phys = EXYNOS4x12_NUM_PHYS,
3730b56e9a7SVivek Gautam .phys = exynos4x12_phys,
3740b56e9a7SVivek Gautam .rate_to_clk = exynos4x12_rate_to_clk,
3750b56e9a7SVivek Gautam };
376