1 /*
2  * Rockchip PCIe PHY driver
3  *
4  * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
5  * Copyright (C) 2016 ROCKCHIP, Inc.
6  *
7  * This program is free software; you can redistribute it and/or modify
8  * it under the terms of the GNU General Public License as published by
9  * the Free Software Foundation; either version 2 of the License.
10  *
11  * This program is distributed in the hope that it will be useful,
12  * but WITHOUT ANY WARRANTY; without even the implied warranty of
13  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14  * GNU General Public License for more details.
15  */
16 
17 #include <linux/clk.h>
18 #include <linux/delay.h>
19 #include <linux/io.h>
20 #include <linux/mfd/syscon.h>
21 #include <linux/module.h>
22 #include <linux/of.h>
23 #include <linux/of_address.h>
24 #include <linux/of_platform.h>
25 #include <linux/phy/phy.h>
26 #include <linux/platform_device.h>
27 #include <linux/regmap.h>
28 #include <linux/reset.h>
29 
30 /*
31  * The higher 16-bit of this register is used for write protection
32  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
33  */
34 #define HIWORD_UPDATE(val, mask, shift) \
35 		((val) << (shift) | (mask) << ((shift) + 16))
36 
37 #define PHY_MAX_LANE_NUM      4
38 #define PHY_CFG_DATA_SHIFT    7
39 #define PHY_CFG_ADDR_SHIFT    1
40 #define PHY_CFG_DATA_MASK     0xf
41 #define PHY_CFG_ADDR_MASK     0x3f
42 #define PHY_CFG_RD_MASK       0x3ff
43 #define PHY_CFG_WR_ENABLE     1
44 #define PHY_CFG_WR_DISABLE    1
45 #define PHY_CFG_WR_SHIFT      0
46 #define PHY_CFG_WR_MASK       1
47 #define PHY_CFG_PLL_LOCK      0x10
48 #define PHY_CFG_CLK_TEST      0x10
49 #define PHY_CFG_CLK_SCC       0x12
50 #define PHY_CFG_SEPE_RATE     BIT(3)
51 #define PHY_CFG_PLL_100M      BIT(3)
52 #define PHY_PLL_LOCKED        BIT(9)
53 #define PHY_PLL_OUTPUT        BIT(10)
54 #define PHY_LANE_A_STATUS     0x30
55 #define PHY_LANE_B_STATUS     0x31
56 #define PHY_LANE_C_STATUS     0x32
57 #define PHY_LANE_D_STATUS     0x33
58 #define PHY_LANE_RX_DET_SHIFT 11
59 #define PHY_LANE_RX_DET_TH    0x1
60 #define PHY_LANE_IDLE_OFF     0x1
61 #define PHY_LANE_IDLE_MASK    0x1
62 #define PHY_LANE_IDLE_A_SHIFT 3
63 #define PHY_LANE_IDLE_B_SHIFT 4
64 #define PHY_LANE_IDLE_C_SHIFT 5
65 #define PHY_LANE_IDLE_D_SHIFT 6
66 
67 struct rockchip_pcie_data {
68 	unsigned int pcie_conf;
69 	unsigned int pcie_status;
70 	unsigned int pcie_laneoff;
71 };
72 
73 struct rockchip_pcie_phy {
74 	struct rockchip_pcie_data *phy_data;
75 	struct regmap *reg_base;
76 	struct phy_pcie_instance {
77 		struct phy *phy;
78 		u32 index;
79 	} phys[PHY_MAX_LANE_NUM];
80 	struct mutex pcie_mutex;
81 	struct reset_control *phy_rst;
82 	struct clk *clk_pciephy_ref;
83 	int pwr_cnt;
84 	int init_cnt;
85 };
86 
87 static struct rockchip_pcie_phy *to_pcie_phy(struct phy_pcie_instance *inst)
88 {
89 	return container_of(inst, struct rockchip_pcie_phy,
90 					phys[inst->index]);
91 }
92 
93 static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev,
94 					      struct of_phandle_args *args)
95 {
96 	struct rockchip_pcie_phy *rk_phy = dev_get_drvdata(dev);
97 
98 	if (args->args_count == 0)
99 		return rk_phy->phys[0].phy;
100 
101 	if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM))
102 		return ERR_PTR(-ENODEV);
103 
104 	return rk_phy->phys[args->args[0]].phy;
105 }
106 
107 
108 static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy,
109 			      u32 addr, u32 data)
110 {
111 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
112 		     HIWORD_UPDATE(data,
113 				   PHY_CFG_DATA_MASK,
114 				   PHY_CFG_DATA_SHIFT) |
115 		     HIWORD_UPDATE(addr,
116 				   PHY_CFG_ADDR_MASK,
117 				   PHY_CFG_ADDR_SHIFT));
118 	udelay(1);
119 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
120 		     HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
121 				   PHY_CFG_WR_MASK,
122 				   PHY_CFG_WR_SHIFT));
123 	udelay(1);
124 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
125 		     HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
126 				   PHY_CFG_WR_MASK,
127 				   PHY_CFG_WR_SHIFT));
128 }
129 
130 static inline u32 phy_rd_cfg(struct rockchip_pcie_phy *rk_phy,
131 			     u32 addr)
132 {
133 	u32 val;
134 
135 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
136 		     HIWORD_UPDATE(addr,
137 				   PHY_CFG_RD_MASK,
138 				   PHY_CFG_ADDR_SHIFT));
139 	regmap_read(rk_phy->reg_base,
140 		    rk_phy->phy_data->pcie_status,
141 		    &val);
142 	return val;
143 }
144 
145 static int rockchip_pcie_phy_power_off(struct phy *phy)
146 {
147 	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
148 	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
149 	int err = 0;
150 
151 	mutex_lock(&rk_phy->pcie_mutex);
152 
153 	regmap_write(rk_phy->reg_base,
154 		     rk_phy->phy_data->pcie_laneoff,
155 		     HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
156 				   PHY_LANE_IDLE_MASK,
157 				   PHY_LANE_IDLE_A_SHIFT + inst->index));
158 
159 	if (--rk_phy->pwr_cnt)
160 		goto err_out;
161 
162 	err = reset_control_assert(rk_phy->phy_rst);
163 	if (err) {
164 		dev_err(&phy->dev, "assert phy_rst err %d\n", err);
165 		goto err_restore;
166 	}
167 
168 err_out:
169 	mutex_unlock(&rk_phy->pcie_mutex);
170 	return 0;
171 
172 err_restore:
173 	rk_phy->pwr_cnt++;
174 	regmap_write(rk_phy->reg_base,
175 		     rk_phy->phy_data->pcie_laneoff,
176 		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
177 				   PHY_LANE_IDLE_MASK,
178 				   PHY_LANE_IDLE_A_SHIFT + inst->index));
179 	mutex_unlock(&rk_phy->pcie_mutex);
180 	return err;
181 }
182 
183 static int rockchip_pcie_phy_power_on(struct phy *phy)
184 {
185 	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
186 	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
187 	int err = 0;
188 	u32 status;
189 	unsigned long timeout;
190 
191 	mutex_lock(&rk_phy->pcie_mutex);
192 
193 	if (rk_phy->pwr_cnt++)
194 		goto err_out;
195 
196 	err = reset_control_deassert(rk_phy->phy_rst);
197 	if (err) {
198 		dev_err(&phy->dev, "deassert phy_rst err %d\n", err);
199 		goto err_pwr_cnt;
200 	}
201 
202 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
203 		     HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
204 				   PHY_CFG_ADDR_MASK,
205 				   PHY_CFG_ADDR_SHIFT));
206 
207 	regmap_write(rk_phy->reg_base,
208 		     rk_phy->phy_data->pcie_laneoff,
209 		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
210 				   PHY_LANE_IDLE_MASK,
211 				   PHY_LANE_IDLE_A_SHIFT + inst->index));
212 
213 	/*
214 	 * No documented timeout value for phy operation below,
215 	 * so we make it large enough here. And we use loop-break
216 	 * method which should not be harmful.
217 	 */
218 	timeout = jiffies + msecs_to_jiffies(1000);
219 
220 	err = -EINVAL;
221 	while (time_before(jiffies, timeout)) {
222 		regmap_read(rk_phy->reg_base,
223 			    rk_phy->phy_data->pcie_status,
224 			    &status);
225 		if (status & PHY_PLL_LOCKED) {
226 			dev_dbg(&phy->dev, "pll locked!\n");
227 			err = 0;
228 			break;
229 		}
230 		msleep(20);
231 	}
232 
233 	if (err) {
234 		dev_err(&phy->dev, "pll lock timeout!\n");
235 		goto err_pll_lock;
236 	}
237 
238 	phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
239 	phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
240 
241 	err = -ETIMEDOUT;
242 	while (time_before(jiffies, timeout)) {
243 		regmap_read(rk_phy->reg_base,
244 			    rk_phy->phy_data->pcie_status,
245 			    &status);
246 		if (!(status & PHY_PLL_OUTPUT)) {
247 			dev_dbg(&phy->dev, "pll output enable done!\n");
248 			err = 0;
249 			break;
250 		}
251 		msleep(20);
252 	}
253 
254 	if (err) {
255 		dev_err(&phy->dev, "pll output enable timeout!\n");
256 		goto err_pll_lock;
257 	}
258 
259 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
260 		     HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
261 				   PHY_CFG_ADDR_MASK,
262 				   PHY_CFG_ADDR_SHIFT));
263 	err = -EINVAL;
264 	while (time_before(jiffies, timeout)) {
265 		regmap_read(rk_phy->reg_base,
266 			    rk_phy->phy_data->pcie_status,
267 			    &status);
268 		if (status & PHY_PLL_LOCKED) {
269 			dev_dbg(&phy->dev, "pll relocked!\n");
270 			err = 0;
271 			break;
272 		}
273 		msleep(20);
274 	}
275 
276 	if (err) {
277 		dev_err(&phy->dev, "pll relock timeout!\n");
278 		goto err_pll_lock;
279 	}
280 
281 err_out:
282 	mutex_unlock(&rk_phy->pcie_mutex);
283 	return 0;
284 
285 err_pll_lock:
286 	reset_control_assert(rk_phy->phy_rst);
287 err_pwr_cnt:
288 	rk_phy->pwr_cnt--;
289 	mutex_unlock(&rk_phy->pcie_mutex);
290 	return err;
291 }
292 
293 static int rockchip_pcie_phy_init(struct phy *phy)
294 {
295 	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
296 	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
297 	int err = 0;
298 
299 	mutex_lock(&rk_phy->pcie_mutex);
300 
301 	if (rk_phy->init_cnt++)
302 		goto err_out;
303 
304 	err = clk_prepare_enable(rk_phy->clk_pciephy_ref);
305 	if (err) {
306 		dev_err(&phy->dev, "Fail to enable pcie ref clock.\n");
307 		goto err_refclk;
308 	}
309 
310 	err = reset_control_assert(rk_phy->phy_rst);
311 	if (err) {
312 		dev_err(&phy->dev, "assert phy_rst err %d\n", err);
313 		goto err_reset;
314 	}
315 
316 err_out:
317 	mutex_unlock(&rk_phy->pcie_mutex);
318 	return 0;
319 
320 err_reset:
321 
322 	clk_disable_unprepare(rk_phy->clk_pciephy_ref);
323 err_refclk:
324 	rk_phy->init_cnt--;
325 	mutex_unlock(&rk_phy->pcie_mutex);
326 	return err;
327 }
328 
329 static int rockchip_pcie_phy_exit(struct phy *phy)
330 {
331 	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
332 	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
333 
334 	mutex_lock(&rk_phy->pcie_mutex);
335 
336 	if (--rk_phy->init_cnt)
337 		goto err_init_cnt;
338 
339 	clk_disable_unprepare(rk_phy->clk_pciephy_ref);
340 
341 err_init_cnt:
342 	mutex_unlock(&rk_phy->pcie_mutex);
343 	return 0;
344 }
345 
346 static const struct phy_ops ops = {
347 	.init		= rockchip_pcie_phy_init,
348 	.exit		= rockchip_pcie_phy_exit,
349 	.power_on	= rockchip_pcie_phy_power_on,
350 	.power_off	= rockchip_pcie_phy_power_off,
351 	.owner		= THIS_MODULE,
352 };
353 
354 static const struct rockchip_pcie_data rk3399_pcie_data = {
355 	.pcie_conf = 0xe220,
356 	.pcie_status = 0xe2a4,
357 	.pcie_laneoff = 0xe214,
358 };
359 
360 static const struct of_device_id rockchip_pcie_phy_dt_ids[] = {
361 	{
362 		.compatible = "rockchip,rk3399-pcie-phy",
363 		.data = &rk3399_pcie_data,
364 	},
365 	{}
366 };
367 
368 MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids);
369 
370 static int rockchip_pcie_phy_probe(struct platform_device *pdev)
371 {
372 	struct device *dev = &pdev->dev;
373 	struct rockchip_pcie_phy *rk_phy;
374 	struct phy_provider *phy_provider;
375 	struct regmap *grf;
376 	const struct of_device_id *of_id;
377 	int i;
378 	u32 phy_num;
379 
380 	grf = syscon_node_to_regmap(dev->parent->of_node);
381 	if (IS_ERR(grf)) {
382 		dev_err(dev, "Cannot find GRF syscon\n");
383 		return PTR_ERR(grf);
384 	}
385 
386 	rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
387 	if (!rk_phy)
388 		return -ENOMEM;
389 
390 	of_id = of_match_device(rockchip_pcie_phy_dt_ids, &pdev->dev);
391 	if (!of_id)
392 		return -EINVAL;
393 
394 	rk_phy->phy_data = (struct rockchip_pcie_data *)of_id->data;
395 	rk_phy->reg_base = grf;
396 
397 	mutex_init(&rk_phy->pcie_mutex);
398 
399 	rk_phy->phy_rst = devm_reset_control_get(dev, "phy");
400 	if (IS_ERR(rk_phy->phy_rst)) {
401 		if (PTR_ERR(rk_phy->phy_rst) != -EPROBE_DEFER)
402 			dev_err(dev,
403 				"missing phy property for reset controller\n");
404 		return PTR_ERR(rk_phy->phy_rst);
405 	}
406 
407 	rk_phy->clk_pciephy_ref = devm_clk_get(dev, "refclk");
408 	if (IS_ERR(rk_phy->clk_pciephy_ref)) {
409 		dev_err(dev, "refclk not found.\n");
410 		return PTR_ERR(rk_phy->clk_pciephy_ref);
411 	}
412 
413 	/* parse #phy-cells to see if it's legacy PHY model */
414 	if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num))
415 		return -ENOENT;
416 
417 	phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM;
418 	dev_dbg(dev, "phy number is %d\n", phy_num);
419 
420 	for (i = 0; i < phy_num; i++) {
421 		rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops);
422 		if (IS_ERR(rk_phy->phys[i].phy)) {
423 			dev_err(dev, "failed to create PHY%d\n", i);
424 			return PTR_ERR(rk_phy->phys[i].phy);
425 		}
426 		rk_phy->phys[i].index = i;
427 		phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]);
428 	}
429 
430 	platform_set_drvdata(pdev, rk_phy);
431 	phy_provider = devm_of_phy_provider_register(dev,
432 					rockchip_pcie_phy_of_xlate);
433 
434 	return PTR_ERR_OR_ZERO(phy_provider);
435 }
436 
437 static struct platform_driver rockchip_pcie_driver = {
438 	.probe		= rockchip_pcie_phy_probe,
439 	.driver		= {
440 		.name	= "rockchip-pcie-phy",
441 		.of_match_table = rockchip_pcie_phy_dt_ids,
442 	},
443 };
444 
445 module_platform_driver(rockchip_pcie_driver);
446 
447 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
448 MODULE_DESCRIPTION("Rockchip PCIe PHY driver");
449 MODULE_LICENSE("GPL v2");
450