1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * Rockchip PCIe PHY driver
4  *
5  * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com>
6  * Copyright (C) 2016 ROCKCHIP, Inc.
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/io.h>
12 #include <linux/mfd/syscon.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/of_platform.h>
17 #include <linux/phy/phy.h>
18 #include <linux/platform_device.h>
19 #include <linux/regmap.h>
20 #include <linux/reset.h>
21 
22 /*
23  * The higher 16-bit of this register is used for write protection
24  * only if BIT(x + 16) set to 1 the BIT(x) can be written.
25  */
26 #define HIWORD_UPDATE(val, mask, shift) \
27 		((val) << (shift) | (mask) << ((shift) + 16))
28 
29 #define PHY_MAX_LANE_NUM      4
30 #define PHY_CFG_DATA_SHIFT    7
31 #define PHY_CFG_ADDR_SHIFT    1
32 #define PHY_CFG_DATA_MASK     0xf
33 #define PHY_CFG_ADDR_MASK     0x3f
34 #define PHY_CFG_RD_MASK       0x3ff
35 #define PHY_CFG_WR_ENABLE     1
36 #define PHY_CFG_WR_DISABLE    1
37 #define PHY_CFG_WR_SHIFT      0
38 #define PHY_CFG_WR_MASK       1
39 #define PHY_CFG_PLL_LOCK      0x10
40 #define PHY_CFG_CLK_TEST      0x10
41 #define PHY_CFG_CLK_SCC       0x12
42 #define PHY_CFG_SEPE_RATE     BIT(3)
43 #define PHY_CFG_PLL_100M      BIT(3)
44 #define PHY_PLL_LOCKED        BIT(9)
45 #define PHY_PLL_OUTPUT        BIT(10)
46 #define PHY_LANE_A_STATUS     0x30
47 #define PHY_LANE_B_STATUS     0x31
48 #define PHY_LANE_C_STATUS     0x32
49 #define PHY_LANE_D_STATUS     0x33
50 #define PHY_LANE_RX_DET_SHIFT 11
51 #define PHY_LANE_RX_DET_TH    0x1
52 #define PHY_LANE_IDLE_OFF     0x1
53 #define PHY_LANE_IDLE_MASK    0x1
54 #define PHY_LANE_IDLE_A_SHIFT 3
55 #define PHY_LANE_IDLE_B_SHIFT 4
56 #define PHY_LANE_IDLE_C_SHIFT 5
57 #define PHY_LANE_IDLE_D_SHIFT 6
58 
59 struct rockchip_pcie_data {
60 	unsigned int pcie_conf;
61 	unsigned int pcie_status;
62 	unsigned int pcie_laneoff;
63 };
64 
65 struct rockchip_pcie_phy {
66 	struct rockchip_pcie_data *phy_data;
67 	struct regmap *reg_base;
68 	struct phy_pcie_instance {
69 		struct phy *phy;
70 		u32 index;
71 	} phys[PHY_MAX_LANE_NUM];
72 	struct mutex pcie_mutex;
73 	struct reset_control *phy_rst;
74 	struct clk *clk_pciephy_ref;
75 	int pwr_cnt;
76 	int init_cnt;
77 };
78 
79 static struct rockchip_pcie_phy *to_pcie_phy(struct phy_pcie_instance *inst)
80 {
81 	return container_of(inst, struct rockchip_pcie_phy,
82 					phys[inst->index]);
83 }
84 
85 static struct phy *rockchip_pcie_phy_of_xlate(struct device *dev,
86 					      struct of_phandle_args *args)
87 {
88 	struct rockchip_pcie_phy *rk_phy = dev_get_drvdata(dev);
89 
90 	if (args->args_count == 0)
91 		return rk_phy->phys[0].phy;
92 
93 	if (WARN_ON(args->args[0] >= PHY_MAX_LANE_NUM))
94 		return ERR_PTR(-ENODEV);
95 
96 	return rk_phy->phys[args->args[0]].phy;
97 }
98 
99 
100 static inline void phy_wr_cfg(struct rockchip_pcie_phy *rk_phy,
101 			      u32 addr, u32 data)
102 {
103 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
104 		     HIWORD_UPDATE(data,
105 				   PHY_CFG_DATA_MASK,
106 				   PHY_CFG_DATA_SHIFT) |
107 		     HIWORD_UPDATE(addr,
108 				   PHY_CFG_ADDR_MASK,
109 				   PHY_CFG_ADDR_SHIFT));
110 	udelay(1);
111 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
112 		     HIWORD_UPDATE(PHY_CFG_WR_ENABLE,
113 				   PHY_CFG_WR_MASK,
114 				   PHY_CFG_WR_SHIFT));
115 	udelay(1);
116 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
117 		     HIWORD_UPDATE(PHY_CFG_WR_DISABLE,
118 				   PHY_CFG_WR_MASK,
119 				   PHY_CFG_WR_SHIFT));
120 }
121 
122 static int rockchip_pcie_phy_power_off(struct phy *phy)
123 {
124 	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
125 	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
126 	int err = 0;
127 
128 	mutex_lock(&rk_phy->pcie_mutex);
129 
130 	regmap_write(rk_phy->reg_base,
131 		     rk_phy->phy_data->pcie_laneoff,
132 		     HIWORD_UPDATE(PHY_LANE_IDLE_OFF,
133 				   PHY_LANE_IDLE_MASK,
134 				   PHY_LANE_IDLE_A_SHIFT + inst->index));
135 
136 	if (--rk_phy->pwr_cnt)
137 		goto err_out;
138 
139 	err = reset_control_assert(rk_phy->phy_rst);
140 	if (err) {
141 		dev_err(&phy->dev, "assert phy_rst err %d\n", err);
142 		goto err_restore;
143 	}
144 
145 err_out:
146 	mutex_unlock(&rk_phy->pcie_mutex);
147 	return 0;
148 
149 err_restore:
150 	rk_phy->pwr_cnt++;
151 	regmap_write(rk_phy->reg_base,
152 		     rk_phy->phy_data->pcie_laneoff,
153 		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
154 				   PHY_LANE_IDLE_MASK,
155 				   PHY_LANE_IDLE_A_SHIFT + inst->index));
156 	mutex_unlock(&rk_phy->pcie_mutex);
157 	return err;
158 }
159 
160 static int rockchip_pcie_phy_power_on(struct phy *phy)
161 {
162 	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
163 	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
164 	int err = 0;
165 	u32 status;
166 	unsigned long timeout;
167 
168 	mutex_lock(&rk_phy->pcie_mutex);
169 
170 	if (rk_phy->pwr_cnt++)
171 		goto err_out;
172 
173 	err = reset_control_deassert(rk_phy->phy_rst);
174 	if (err) {
175 		dev_err(&phy->dev, "deassert phy_rst err %d\n", err);
176 		goto err_pwr_cnt;
177 	}
178 
179 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
180 		     HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
181 				   PHY_CFG_ADDR_MASK,
182 				   PHY_CFG_ADDR_SHIFT));
183 
184 	regmap_write(rk_phy->reg_base,
185 		     rk_phy->phy_data->pcie_laneoff,
186 		     HIWORD_UPDATE(!PHY_LANE_IDLE_OFF,
187 				   PHY_LANE_IDLE_MASK,
188 				   PHY_LANE_IDLE_A_SHIFT + inst->index));
189 
190 	/*
191 	 * No documented timeout value for phy operation below,
192 	 * so we make it large enough here. And we use loop-break
193 	 * method which should not be harmful.
194 	 */
195 	timeout = jiffies + msecs_to_jiffies(1000);
196 
197 	err = -EINVAL;
198 	while (time_before(jiffies, timeout)) {
199 		regmap_read(rk_phy->reg_base,
200 			    rk_phy->phy_data->pcie_status,
201 			    &status);
202 		if (status & PHY_PLL_LOCKED) {
203 			dev_dbg(&phy->dev, "pll locked!\n");
204 			err = 0;
205 			break;
206 		}
207 		msleep(20);
208 	}
209 
210 	if (err) {
211 		dev_err(&phy->dev, "pll lock timeout!\n");
212 		goto err_pll_lock;
213 	}
214 
215 	phy_wr_cfg(rk_phy, PHY_CFG_CLK_TEST, PHY_CFG_SEPE_RATE);
216 	phy_wr_cfg(rk_phy, PHY_CFG_CLK_SCC, PHY_CFG_PLL_100M);
217 
218 	err = -ETIMEDOUT;
219 	while (time_before(jiffies, timeout)) {
220 		regmap_read(rk_phy->reg_base,
221 			    rk_phy->phy_data->pcie_status,
222 			    &status);
223 		if (!(status & PHY_PLL_OUTPUT)) {
224 			dev_dbg(&phy->dev, "pll output enable done!\n");
225 			err = 0;
226 			break;
227 		}
228 		msleep(20);
229 	}
230 
231 	if (err) {
232 		dev_err(&phy->dev, "pll output enable timeout!\n");
233 		goto err_pll_lock;
234 	}
235 
236 	regmap_write(rk_phy->reg_base, rk_phy->phy_data->pcie_conf,
237 		     HIWORD_UPDATE(PHY_CFG_PLL_LOCK,
238 				   PHY_CFG_ADDR_MASK,
239 				   PHY_CFG_ADDR_SHIFT));
240 	err = -EINVAL;
241 	while (time_before(jiffies, timeout)) {
242 		regmap_read(rk_phy->reg_base,
243 			    rk_phy->phy_data->pcie_status,
244 			    &status);
245 		if (status & PHY_PLL_LOCKED) {
246 			dev_dbg(&phy->dev, "pll relocked!\n");
247 			err = 0;
248 			break;
249 		}
250 		msleep(20);
251 	}
252 
253 	if (err) {
254 		dev_err(&phy->dev, "pll relock timeout!\n");
255 		goto err_pll_lock;
256 	}
257 
258 err_out:
259 	mutex_unlock(&rk_phy->pcie_mutex);
260 	return 0;
261 
262 err_pll_lock:
263 	reset_control_assert(rk_phy->phy_rst);
264 err_pwr_cnt:
265 	rk_phy->pwr_cnt--;
266 	mutex_unlock(&rk_phy->pcie_mutex);
267 	return err;
268 }
269 
270 static int rockchip_pcie_phy_init(struct phy *phy)
271 {
272 	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
273 	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
274 	int err = 0;
275 
276 	mutex_lock(&rk_phy->pcie_mutex);
277 
278 	if (rk_phy->init_cnt++)
279 		goto err_out;
280 
281 	err = clk_prepare_enable(rk_phy->clk_pciephy_ref);
282 	if (err) {
283 		dev_err(&phy->dev, "Fail to enable pcie ref clock.\n");
284 		goto err_refclk;
285 	}
286 
287 	err = reset_control_assert(rk_phy->phy_rst);
288 	if (err) {
289 		dev_err(&phy->dev, "assert phy_rst err %d\n", err);
290 		goto err_reset;
291 	}
292 
293 err_out:
294 	mutex_unlock(&rk_phy->pcie_mutex);
295 	return 0;
296 
297 err_reset:
298 
299 	clk_disable_unprepare(rk_phy->clk_pciephy_ref);
300 err_refclk:
301 	rk_phy->init_cnt--;
302 	mutex_unlock(&rk_phy->pcie_mutex);
303 	return err;
304 }
305 
306 static int rockchip_pcie_phy_exit(struct phy *phy)
307 {
308 	struct phy_pcie_instance *inst = phy_get_drvdata(phy);
309 	struct rockchip_pcie_phy *rk_phy = to_pcie_phy(inst);
310 
311 	mutex_lock(&rk_phy->pcie_mutex);
312 
313 	if (--rk_phy->init_cnt)
314 		goto err_init_cnt;
315 
316 	clk_disable_unprepare(rk_phy->clk_pciephy_ref);
317 
318 err_init_cnt:
319 	mutex_unlock(&rk_phy->pcie_mutex);
320 	return 0;
321 }
322 
323 static const struct phy_ops ops = {
324 	.init		= rockchip_pcie_phy_init,
325 	.exit		= rockchip_pcie_phy_exit,
326 	.power_on	= rockchip_pcie_phy_power_on,
327 	.power_off	= rockchip_pcie_phy_power_off,
328 	.owner		= THIS_MODULE,
329 };
330 
331 static const struct rockchip_pcie_data rk3399_pcie_data = {
332 	.pcie_conf = 0xe220,
333 	.pcie_status = 0xe2a4,
334 	.pcie_laneoff = 0xe214,
335 };
336 
337 static const struct of_device_id rockchip_pcie_phy_dt_ids[] = {
338 	{
339 		.compatible = "rockchip,rk3399-pcie-phy",
340 		.data = &rk3399_pcie_data,
341 	},
342 	{}
343 };
344 
345 MODULE_DEVICE_TABLE(of, rockchip_pcie_phy_dt_ids);
346 
347 static int rockchip_pcie_phy_probe(struct platform_device *pdev)
348 {
349 	struct device *dev = &pdev->dev;
350 	struct rockchip_pcie_phy *rk_phy;
351 	struct phy_provider *phy_provider;
352 	struct regmap *grf;
353 	const struct of_device_id *of_id;
354 	int i;
355 	u32 phy_num;
356 
357 	grf = syscon_node_to_regmap(dev->parent->of_node);
358 	if (IS_ERR(grf)) {
359 		dev_err(dev, "Cannot find GRF syscon\n");
360 		return PTR_ERR(grf);
361 	}
362 
363 	rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL);
364 	if (!rk_phy)
365 		return -ENOMEM;
366 
367 	of_id = of_match_device(rockchip_pcie_phy_dt_ids, &pdev->dev);
368 	if (!of_id)
369 		return -EINVAL;
370 
371 	rk_phy->phy_data = (struct rockchip_pcie_data *)of_id->data;
372 	rk_phy->reg_base = grf;
373 
374 	mutex_init(&rk_phy->pcie_mutex);
375 
376 	rk_phy->phy_rst = devm_reset_control_get(dev, "phy");
377 	if (IS_ERR(rk_phy->phy_rst)) {
378 		if (PTR_ERR(rk_phy->phy_rst) != -EPROBE_DEFER)
379 			dev_err(dev,
380 				"missing phy property for reset controller\n");
381 		return PTR_ERR(rk_phy->phy_rst);
382 	}
383 
384 	rk_phy->clk_pciephy_ref = devm_clk_get(dev, "refclk");
385 	if (IS_ERR(rk_phy->clk_pciephy_ref)) {
386 		dev_err(dev, "refclk not found.\n");
387 		return PTR_ERR(rk_phy->clk_pciephy_ref);
388 	}
389 
390 	/* parse #phy-cells to see if it's legacy PHY model */
391 	if (of_property_read_u32(dev->of_node, "#phy-cells", &phy_num))
392 		return -ENOENT;
393 
394 	phy_num = (phy_num == 0) ? 1 : PHY_MAX_LANE_NUM;
395 	dev_dbg(dev, "phy number is %d\n", phy_num);
396 
397 	for (i = 0; i < phy_num; i++) {
398 		rk_phy->phys[i].phy = devm_phy_create(dev, dev->of_node, &ops);
399 		if (IS_ERR(rk_phy->phys[i].phy)) {
400 			dev_err(dev, "failed to create PHY%d\n", i);
401 			return PTR_ERR(rk_phy->phys[i].phy);
402 		}
403 		rk_phy->phys[i].index = i;
404 		phy_set_drvdata(rk_phy->phys[i].phy, &rk_phy->phys[i]);
405 	}
406 
407 	platform_set_drvdata(pdev, rk_phy);
408 	phy_provider = devm_of_phy_provider_register(dev,
409 					rockchip_pcie_phy_of_xlate);
410 
411 	return PTR_ERR_OR_ZERO(phy_provider);
412 }
413 
414 static struct platform_driver rockchip_pcie_driver = {
415 	.probe		= rockchip_pcie_phy_probe,
416 	.driver		= {
417 		.name	= "rockchip-pcie-phy",
418 		.of_match_table = rockchip_pcie_phy_dt_ids,
419 	},
420 };
421 
422 module_platform_driver(rockchip_pcie_driver);
423 
424 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>");
425 MODULE_DESCRIPTION("Rockchip PCIe PHY driver");
426 MODULE_LICENSE("GPL v2");
427