1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Rockchip PIPE USB3.0 PCIE SATA Combo Phy driver 4 * 5 * Copyright (C) 2021 Rockchip Electronics Co., Ltd. 6 */ 7 8 #include <dt-bindings/phy/phy.h> 9 #include <linux/clk.h> 10 #include <linux/mfd/syscon.h> 11 #include <linux/of_device.h> 12 #include <linux/phy/phy.h> 13 #include <linux/regmap.h> 14 #include <linux/reset.h> 15 #include <linux/units.h> 16 17 #define BIT_WRITEABLE_SHIFT 16 18 #define REF_CLOCK_24MHz (24 * HZ_PER_MHZ) 19 #define REF_CLOCK_25MHz (25 * HZ_PER_MHZ) 20 #define REF_CLOCK_100MHz (100 * HZ_PER_MHZ) 21 22 /* COMBO PHY REG */ 23 #define PHYREG6 0x14 24 #define PHYREG6_PLL_DIV_MASK GENMASK(7, 6) 25 #define PHYREG6_PLL_DIV_SHIFT 6 26 #define PHYREG6_PLL_DIV_2 1 27 28 #define PHYREG7 0x18 29 #define PHYREG7_TX_RTERM_MASK GENMASK(7, 4) 30 #define PHYREG7_TX_RTERM_SHIFT 4 31 #define PHYREG7_TX_RTERM_50OHM 8 32 #define PHYREG7_RX_RTERM_MASK GENMASK(3, 0) 33 #define PHYREG7_RX_RTERM_SHIFT 0 34 #define PHYREG7_RX_RTERM_44OHM 15 35 36 #define PHYREG8 0x1C 37 #define PHYREG8_SSC_EN BIT(4) 38 39 #define PHYREG11 0x28 40 #define PHYREG11_SU_TRIM_0_7 0xF0 41 42 #define PHYREG12 0x2C 43 #define PHYREG12_PLL_LPF_ADJ_VALUE 4 44 45 #define PHYREG13 0x30 46 #define PHYREG13_RESISTER_MASK GENMASK(5, 4) 47 #define PHYREG13_RESISTER_SHIFT 0x4 48 #define PHYREG13_RESISTER_HIGH_Z 3 49 #define PHYREG13_CKRCV_AMP0 BIT(7) 50 51 #define PHYREG14 0x34 52 #define PHYREG14_CKRCV_AMP1 BIT(0) 53 54 #define PHYREG15 0x38 55 #define PHYREG15_CTLE_EN BIT(0) 56 #define PHYREG15_SSC_CNT_MASK GENMASK(7, 6) 57 #define PHYREG15_SSC_CNT_SHIFT 6 58 #define PHYREG15_SSC_CNT_VALUE 1 59 60 #define PHYREG16 0x3C 61 #define PHYREG16_SSC_CNT_VALUE 0x5f 62 63 #define PHYREG18 0x44 64 #define PHYREG18_PLL_LOOP 0x32 65 66 #define PHYREG32 0x7C 67 #define PHYREG32_SSC_MASK GENMASK(7, 4) 68 #define PHYREG32_SSC_DIR_SHIFT 4 69 #define PHYREG32_SSC_UPWARD 0 70 #define PHYREG32_SSC_DOWNWARD 1 71 #define PHYREG32_SSC_OFFSET_SHIFT 6 72 #define PHYREG32_SSC_OFFSET_500PPM 1 73 74 #define PHYREG33 0x80 75 #define PHYREG33_PLL_KVCO_MASK GENMASK(4, 2) 76 #define PHYREG33_PLL_KVCO_SHIFT 2 77 #define PHYREG33_PLL_KVCO_VALUE 2 78 79 struct rockchip_combphy_priv; 80 81 struct combphy_reg { 82 u16 offset; 83 u16 bitend; 84 u16 bitstart; 85 u16 disable; 86 u16 enable; 87 }; 88 89 struct rockchip_combphy_grfcfg { 90 struct combphy_reg pcie_mode_set; 91 struct combphy_reg usb_mode_set; 92 struct combphy_reg sgmii_mode_set; 93 struct combphy_reg qsgmii_mode_set; 94 struct combphy_reg pipe_rxterm_set; 95 struct combphy_reg pipe_txelec_set; 96 struct combphy_reg pipe_txcomp_set; 97 struct combphy_reg pipe_clk_25m; 98 struct combphy_reg pipe_clk_100m; 99 struct combphy_reg pipe_phymode_sel; 100 struct combphy_reg pipe_rate_sel; 101 struct combphy_reg pipe_rxterm_sel; 102 struct combphy_reg pipe_txelec_sel; 103 struct combphy_reg pipe_txcomp_sel; 104 struct combphy_reg pipe_clk_ext; 105 struct combphy_reg pipe_sel_usb; 106 struct combphy_reg pipe_sel_qsgmii; 107 struct combphy_reg pipe_phy_status; 108 struct combphy_reg con0_for_pcie; 109 struct combphy_reg con1_for_pcie; 110 struct combphy_reg con2_for_pcie; 111 struct combphy_reg con3_for_pcie; 112 struct combphy_reg con0_for_sata; 113 struct combphy_reg con1_for_sata; 114 struct combphy_reg con2_for_sata; 115 struct combphy_reg con3_for_sata; 116 struct combphy_reg pipe_con0_for_sata; 117 struct combphy_reg pipe_xpcs_phy_ready; 118 }; 119 120 struct rockchip_combphy_cfg { 121 const struct rockchip_combphy_grfcfg *grfcfg; 122 int (*combphy_cfg)(struct rockchip_combphy_priv *priv); 123 }; 124 125 struct rockchip_combphy_priv { 126 u8 type; 127 void __iomem *mmio; 128 int num_clks; 129 struct clk_bulk_data *clks; 130 struct device *dev; 131 struct regmap *pipe_grf; 132 struct regmap *phy_grf; 133 struct phy *phy; 134 struct reset_control *phy_rst; 135 const struct rockchip_combphy_cfg *cfg; 136 bool enable_ssc; 137 bool ext_refclk; 138 struct clk *refclk; 139 }; 140 141 static void rockchip_combphy_updatel(struct rockchip_combphy_priv *priv, 142 int mask, int val, int reg) 143 { 144 unsigned int temp; 145 146 temp = readl(priv->mmio + reg); 147 temp = (temp & ~(mask)) | val; 148 writel(temp, priv->mmio + reg); 149 } 150 151 static int rockchip_combphy_param_write(struct regmap *base, 152 const struct combphy_reg *reg, bool en) 153 { 154 u32 val, mask, tmp; 155 156 tmp = en ? reg->enable : reg->disable; 157 mask = GENMASK(reg->bitend, reg->bitstart); 158 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 159 160 return regmap_write(base, reg->offset, val); 161 } 162 163 static u32 rockchip_combphy_is_ready(struct rockchip_combphy_priv *priv) 164 { 165 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 166 u32 mask, val; 167 168 mask = GENMASK(cfg->pipe_phy_status.bitend, 169 cfg->pipe_phy_status.bitstart); 170 171 regmap_read(priv->phy_grf, cfg->pipe_phy_status.offset, &val); 172 val = (val & mask) >> cfg->pipe_phy_status.bitstart; 173 174 return val; 175 } 176 177 static int rockchip_combphy_init(struct phy *phy) 178 { 179 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); 180 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 181 u32 val; 182 int ret; 183 184 ret = clk_bulk_prepare_enable(priv->num_clks, priv->clks); 185 if (ret) { 186 dev_err(priv->dev, "failed to enable clks\n"); 187 return ret; 188 } 189 190 switch (priv->type) { 191 case PHY_TYPE_PCIE: 192 case PHY_TYPE_USB3: 193 case PHY_TYPE_SATA: 194 case PHY_TYPE_SGMII: 195 case PHY_TYPE_QSGMII: 196 if (priv->cfg->combphy_cfg) 197 ret = priv->cfg->combphy_cfg(priv); 198 break; 199 default: 200 dev_err(priv->dev, "incompatible PHY type\n"); 201 ret = -EINVAL; 202 break; 203 } 204 205 if (ret) { 206 dev_err(priv->dev, "failed to init phy for phy type %x\n", priv->type); 207 goto err_clk; 208 } 209 210 ret = reset_control_deassert(priv->phy_rst); 211 if (ret) 212 goto err_clk; 213 214 if (priv->type == PHY_TYPE_USB3) { 215 ret = readx_poll_timeout_atomic(rockchip_combphy_is_ready, 216 priv, val, 217 val == cfg->pipe_phy_status.enable, 218 10, 1000); 219 if (ret) 220 dev_warn(priv->dev, "wait phy status ready timeout\n"); 221 } 222 223 return 0; 224 225 err_clk: 226 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); 227 228 return ret; 229 } 230 231 static int rockchip_combphy_exit(struct phy *phy) 232 { 233 struct rockchip_combphy_priv *priv = phy_get_drvdata(phy); 234 235 clk_bulk_disable_unprepare(priv->num_clks, priv->clks); 236 reset_control_assert(priv->phy_rst); 237 238 return 0; 239 } 240 241 static const struct phy_ops rochchip_combphy_ops = { 242 .init = rockchip_combphy_init, 243 .exit = rockchip_combphy_exit, 244 .owner = THIS_MODULE, 245 }; 246 247 static struct phy *rockchip_combphy_xlate(struct device *dev, struct of_phandle_args *args) 248 { 249 struct rockchip_combphy_priv *priv = dev_get_drvdata(dev); 250 251 if (args->args_count != 1) { 252 dev_err(dev, "invalid number of arguments\n"); 253 return ERR_PTR(-EINVAL); 254 } 255 256 if (priv->type != PHY_NONE && priv->type != args->args[0]) 257 dev_warn(dev, "phy type select %d overwriting type %d\n", 258 args->args[0], priv->type); 259 260 priv->type = args->args[0]; 261 262 return priv->phy; 263 } 264 265 static int rockchip_combphy_parse_dt(struct device *dev, struct rockchip_combphy_priv *priv) 266 { 267 int i; 268 269 priv->num_clks = devm_clk_bulk_get_all(dev, &priv->clks); 270 if (priv->num_clks < 1) 271 return -EINVAL; 272 273 priv->refclk = NULL; 274 for (i = 0; i < priv->num_clks; i++) { 275 if (!strncmp(priv->clks[i].id, "ref", 3)) { 276 priv->refclk = priv->clks[i].clk; 277 break; 278 } 279 } 280 281 if (!priv->refclk) { 282 dev_err(dev, "no refclk found\n"); 283 return -EINVAL; 284 } 285 286 priv->pipe_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-grf"); 287 if (IS_ERR(priv->pipe_grf)) { 288 dev_err(dev, "failed to find peri_ctrl pipe-grf regmap\n"); 289 return PTR_ERR(priv->pipe_grf); 290 } 291 292 priv->phy_grf = syscon_regmap_lookup_by_phandle(dev->of_node, "rockchip,pipe-phy-grf"); 293 if (IS_ERR(priv->phy_grf)) { 294 dev_err(dev, "failed to find peri_ctrl pipe-phy-grf regmap\n"); 295 return PTR_ERR(priv->phy_grf); 296 } 297 298 priv->enable_ssc = device_property_present(dev, "rockchip,enable-ssc"); 299 300 priv->ext_refclk = device_property_present(dev, "rockchip,ext-refclk"); 301 302 priv->phy_rst = devm_reset_control_array_get_exclusive(dev); 303 if (IS_ERR(priv->phy_rst)) 304 return dev_err_probe(dev, PTR_ERR(priv->phy_rst), "failed to get phy reset\n"); 305 306 return 0; 307 } 308 309 static int rockchip_combphy_probe(struct platform_device *pdev) 310 { 311 struct phy_provider *phy_provider; 312 struct device *dev = &pdev->dev; 313 struct rockchip_combphy_priv *priv; 314 const struct rockchip_combphy_cfg *phy_cfg; 315 struct resource *res; 316 int ret; 317 318 phy_cfg = of_device_get_match_data(dev); 319 if (!phy_cfg) { 320 dev_err(dev, "no OF match data provided\n"); 321 return -EINVAL; 322 } 323 324 priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL); 325 if (!priv) 326 return -ENOMEM; 327 328 priv->mmio = devm_platform_get_and_ioremap_resource(pdev, 0, &res); 329 if (IS_ERR(priv->mmio)) { 330 ret = PTR_ERR(priv->mmio); 331 return ret; 332 } 333 334 priv->dev = dev; 335 priv->type = PHY_NONE; 336 priv->cfg = phy_cfg; 337 338 ret = rockchip_combphy_parse_dt(dev, priv); 339 if (ret) 340 return ret; 341 342 ret = reset_control_assert(priv->phy_rst); 343 if (ret) { 344 dev_err(dev, "failed to reset phy\n"); 345 return ret; 346 } 347 348 priv->phy = devm_phy_create(dev, NULL, &rochchip_combphy_ops); 349 if (IS_ERR(priv->phy)) { 350 dev_err(dev, "failed to create combphy\n"); 351 return PTR_ERR(priv->phy); 352 } 353 354 dev_set_drvdata(dev, priv); 355 phy_set_drvdata(priv->phy, priv); 356 357 phy_provider = devm_of_phy_provider_register(dev, rockchip_combphy_xlate); 358 359 return PTR_ERR_OR_ZERO(phy_provider); 360 } 361 362 static int rk3568_combphy_cfg(struct rockchip_combphy_priv *priv) 363 { 364 const struct rockchip_combphy_grfcfg *cfg = priv->cfg->grfcfg; 365 unsigned long rate; 366 u32 val; 367 368 switch (priv->type) { 369 case PHY_TYPE_PCIE: 370 /* Set SSC downward spread spectrum. */ 371 rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, 372 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, 373 PHYREG32); 374 375 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_pcie, true); 376 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_pcie, true); 377 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_pcie, true); 378 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_pcie, true); 379 break; 380 381 case PHY_TYPE_USB3: 382 /* Set SSC downward spread spectrum. */ 383 rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, 384 PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT, 385 PHYREG32); 386 387 /* Enable adaptive CTLE for USB3.0 Rx. */ 388 val = readl(priv->mmio + PHYREG15); 389 val |= PHYREG15_CTLE_EN; 390 writel(val, priv->mmio + PHYREG15); 391 392 /* Set PLL KVCO fine tuning signals. */ 393 rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, 394 PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT, 395 PHYREG33); 396 397 /* Enable controlling random jitter. */ 398 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); 399 400 /* Set PLL input clock divider 1/2. */ 401 rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, 402 PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT, 403 PHYREG6); 404 405 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); 406 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); 407 408 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_usb, true); 409 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txcomp_sel, false); 410 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_txelec_sel, false); 411 rockchip_combphy_param_write(priv->phy_grf, &cfg->usb_mode_set, true); 412 break; 413 414 case PHY_TYPE_SATA: 415 /* Enable adaptive CTLE for SATA Rx. */ 416 val = readl(priv->mmio + PHYREG15); 417 val |= PHYREG15_CTLE_EN; 418 writel(val, priv->mmio + PHYREG15); 419 /* 420 * Set tx_rterm=50ohm and rx_rterm=44ohm for SATA. 421 * 0: 60ohm, 8: 50ohm 15: 44ohm (by step abort 1ohm) 422 */ 423 val = PHYREG7_TX_RTERM_50OHM << PHYREG7_TX_RTERM_SHIFT; 424 val |= PHYREG7_RX_RTERM_44OHM << PHYREG7_RX_RTERM_SHIFT; 425 writel(val, priv->mmio + PHYREG7); 426 427 rockchip_combphy_param_write(priv->phy_grf, &cfg->con0_for_sata, true); 428 rockchip_combphy_param_write(priv->phy_grf, &cfg->con1_for_sata, true); 429 rockchip_combphy_param_write(priv->phy_grf, &cfg->con2_for_sata, true); 430 rockchip_combphy_param_write(priv->phy_grf, &cfg->con3_for_sata, true); 431 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_con0_for_sata, true); 432 break; 433 434 case PHY_TYPE_SGMII: 435 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 436 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 437 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 438 rockchip_combphy_param_write(priv->phy_grf, &cfg->sgmii_mode_set, true); 439 break; 440 441 case PHY_TYPE_QSGMII: 442 rockchip_combphy_param_write(priv->pipe_grf, &cfg->pipe_xpcs_phy_ready, true); 443 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_phymode_sel, true); 444 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_rate_sel, true); 445 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_sel_qsgmii, true); 446 rockchip_combphy_param_write(priv->phy_grf, &cfg->qsgmii_mode_set, true); 447 break; 448 449 default: 450 dev_err(priv->dev, "incompatible PHY type\n"); 451 return -EINVAL; 452 } 453 454 rate = clk_get_rate(priv->refclk); 455 456 switch (rate) { 457 case REF_CLOCK_24MHz: 458 if (priv->type == PHY_TYPE_USB3 || priv->type == PHY_TYPE_SATA) { 459 /* Set ssc_cnt[9:0]=0101111101 & 31.5KHz. */ 460 val = PHYREG15_SSC_CNT_VALUE << PHYREG15_SSC_CNT_SHIFT; 461 rockchip_combphy_updatel(priv, PHYREG15_SSC_CNT_MASK, 462 val, PHYREG15); 463 464 writel(PHYREG16_SSC_CNT_VALUE, priv->mmio + PHYREG16); 465 } 466 break; 467 468 case REF_CLOCK_25MHz: 469 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_25m, true); 470 break; 471 472 case REF_CLOCK_100MHz: 473 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_100m, true); 474 if (priv->type == PHY_TYPE_PCIE) { 475 /* PLL KVCO fine tuning. */ 476 val = PHYREG33_PLL_KVCO_VALUE << PHYREG33_PLL_KVCO_SHIFT; 477 rockchip_combphy_updatel(priv, PHYREG33_PLL_KVCO_MASK, 478 val, PHYREG33); 479 480 /* Enable controlling random jitter. */ 481 writel(PHYREG12_PLL_LPF_ADJ_VALUE, priv->mmio + PHYREG12); 482 483 val = PHYREG6_PLL_DIV_2 << PHYREG6_PLL_DIV_SHIFT; 484 rockchip_combphy_updatel(priv, PHYREG6_PLL_DIV_MASK, 485 val, PHYREG6); 486 487 writel(PHYREG18_PLL_LOOP, priv->mmio + PHYREG18); 488 writel(PHYREG11_SU_TRIM_0_7, priv->mmio + PHYREG11); 489 } else if (priv->type == PHY_TYPE_SATA) { 490 /* downward spread spectrum +500ppm */ 491 val = PHYREG32_SSC_DOWNWARD << PHYREG32_SSC_DIR_SHIFT; 492 val |= PHYREG32_SSC_OFFSET_500PPM << PHYREG32_SSC_OFFSET_SHIFT; 493 rockchip_combphy_updatel(priv, PHYREG32_SSC_MASK, val, PHYREG32); 494 } 495 break; 496 497 default: 498 dev_err(priv->dev, "unsupported rate: %lu\n", rate); 499 return -EINVAL; 500 } 501 502 if (priv->ext_refclk) { 503 rockchip_combphy_param_write(priv->phy_grf, &cfg->pipe_clk_ext, true); 504 if (priv->type == PHY_TYPE_PCIE && rate == REF_CLOCK_100MHz) { 505 val = PHYREG13_RESISTER_HIGH_Z << PHYREG13_RESISTER_SHIFT; 506 val |= PHYREG13_CKRCV_AMP0; 507 rockchip_combphy_updatel(priv, PHYREG13_RESISTER_MASK, val, PHYREG13); 508 509 val = readl(priv->mmio + PHYREG14); 510 val |= PHYREG14_CKRCV_AMP1; 511 writel(val, priv->mmio + PHYREG14); 512 } 513 } 514 515 if (priv->enable_ssc) { 516 val = readl(priv->mmio + PHYREG8); 517 val |= PHYREG8_SSC_EN; 518 writel(val, priv->mmio + PHYREG8); 519 } 520 521 return 0; 522 } 523 524 static const struct rockchip_combphy_grfcfg rk3568_combphy_grfcfgs = { 525 /* pipe-phy-grf */ 526 .pcie_mode_set = { 0x0000, 5, 0, 0x00, 0x11 }, 527 .usb_mode_set = { 0x0000, 5, 0, 0x00, 0x04 }, 528 .sgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x01 }, 529 .qsgmii_mode_set = { 0x0000, 5, 0, 0x00, 0x21 }, 530 .pipe_rxterm_set = { 0x0000, 12, 12, 0x00, 0x01 }, 531 .pipe_txelec_set = { 0x0004, 1, 1, 0x00, 0x01 }, 532 .pipe_txcomp_set = { 0x0004, 4, 4, 0x00, 0x01 }, 533 .pipe_clk_25m = { 0x0004, 14, 13, 0x00, 0x01 }, 534 .pipe_clk_100m = { 0x0004, 14, 13, 0x00, 0x02 }, 535 .pipe_phymode_sel = { 0x0008, 1, 1, 0x00, 0x01 }, 536 .pipe_rate_sel = { 0x0008, 2, 2, 0x00, 0x01 }, 537 .pipe_rxterm_sel = { 0x0008, 8, 8, 0x00, 0x01 }, 538 .pipe_txelec_sel = { 0x0008, 12, 12, 0x00, 0x01 }, 539 .pipe_txcomp_sel = { 0x0008, 15, 15, 0x00, 0x01 }, 540 .pipe_clk_ext = { 0x000c, 9, 8, 0x02, 0x01 }, 541 .pipe_sel_usb = { 0x000c, 14, 13, 0x00, 0x01 }, 542 .pipe_sel_qsgmii = { 0x000c, 15, 13, 0x00, 0x07 }, 543 .pipe_phy_status = { 0x0034, 6, 6, 0x01, 0x00 }, 544 .con0_for_pcie = { 0x0000, 15, 0, 0x00, 0x1000 }, 545 .con1_for_pcie = { 0x0004, 15, 0, 0x00, 0x0000 }, 546 .con2_for_pcie = { 0x0008, 15, 0, 0x00, 0x0101 }, 547 .con3_for_pcie = { 0x000c, 15, 0, 0x00, 0x0200 }, 548 .con0_for_sata = { 0x0000, 15, 0, 0x00, 0x0119 }, 549 .con1_for_sata = { 0x0004, 15, 0, 0x00, 0x0040 }, 550 .con2_for_sata = { 0x0008, 15, 0, 0x00, 0x80c3 }, 551 .con3_for_sata = { 0x000c, 15, 0, 0x00, 0x4407 }, 552 /* pipe-grf */ 553 .pipe_con0_for_sata = { 0x0000, 15, 0, 0x00, 0x2220 }, 554 .pipe_xpcs_phy_ready = { 0x0040, 2, 2, 0x00, 0x01 }, 555 }; 556 557 static const struct rockchip_combphy_cfg rk3568_combphy_cfgs = { 558 .grfcfg = &rk3568_combphy_grfcfgs, 559 .combphy_cfg = rk3568_combphy_cfg, 560 }; 561 562 static const struct of_device_id rockchip_combphy_of_match[] = { 563 { 564 .compatible = "rockchip,rk3568-naneng-combphy", 565 .data = &rk3568_combphy_cfgs, 566 }, 567 { }, 568 }; 569 MODULE_DEVICE_TABLE(of, rockchip_combphy_of_match); 570 571 static struct platform_driver rockchip_combphy_driver = { 572 .probe = rockchip_combphy_probe, 573 .driver = { 574 .name = "rockchip-naneng-combphy", 575 .of_match_table = rockchip_combphy_of_match, 576 }, 577 }; 578 module_platform_driver(rockchip_combphy_driver); 579 580 MODULE_DESCRIPTION("Rockchip NANENG COMBPHY driver"); 581 MODULE_LICENSE("GPL v2"); 582