1 /* 2 * Rockchip USB2.0 PHY with Innosilicon IP block driver 3 * 4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/clk-provider.h> 19 #include <linux/delay.h> 20 #include <linux/extcon-provider.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/gpio/consumer.h> 24 #include <linux/jiffies.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/mutex.h> 28 #include <linux/of.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/of_platform.h> 32 #include <linux/phy/phy.h> 33 #include <linux/platform_device.h> 34 #include <linux/power_supply.h> 35 #include <linux/regmap.h> 36 #include <linux/mfd/syscon.h> 37 #include <linux/usb/of.h> 38 #include <linux/usb/otg.h> 39 40 #define BIT_WRITEABLE_SHIFT 16 41 #define SCHEDULE_DELAY (60 * HZ) 42 #define OTG_SCHEDULE_DELAY (2 * HZ) 43 44 enum rockchip_usb2phy_port_id { 45 USB2PHY_PORT_OTG, 46 USB2PHY_PORT_HOST, 47 USB2PHY_NUM_PORTS, 48 }; 49 50 enum rockchip_usb2phy_host_state { 51 PHY_STATE_HS_ONLINE = 0, 52 PHY_STATE_DISCONNECT = 1, 53 PHY_STATE_CONNECT = 2, 54 PHY_STATE_FS_LS_ONLINE = 4, 55 }; 56 57 /** 58 * enum usb_chg_state - Different states involved in USB charger detection. 59 * @USB_CHG_STATE_UNDEFINED: USB charger is not connected or detection 60 * process is not yet started. 61 * @USB_CHG_STATE_WAIT_FOR_DCD: Waiting for Data pins contact. 62 * @USB_CHG_STATE_DCD_DONE: Data pin contact is detected. 63 * @USB_CHG_STATE_PRIMARY_DONE: Primary detection is completed (Detects 64 * between SDP and DCP/CDP). 65 * @USB_CHG_STATE_SECONDARY_DONE: Secondary detection is completed (Detects 66 * between DCP and CDP). 67 * @USB_CHG_STATE_DETECTED: USB charger type is determined. 68 */ 69 enum usb_chg_state { 70 USB_CHG_STATE_UNDEFINED = 0, 71 USB_CHG_STATE_WAIT_FOR_DCD, 72 USB_CHG_STATE_DCD_DONE, 73 USB_CHG_STATE_PRIMARY_DONE, 74 USB_CHG_STATE_SECONDARY_DONE, 75 USB_CHG_STATE_DETECTED, 76 }; 77 78 static const unsigned int rockchip_usb2phy_extcon_cable[] = { 79 EXTCON_USB, 80 EXTCON_USB_HOST, 81 EXTCON_CHG_USB_SDP, 82 EXTCON_CHG_USB_CDP, 83 EXTCON_CHG_USB_DCP, 84 EXTCON_CHG_USB_SLOW, 85 EXTCON_NONE, 86 }; 87 88 struct usb2phy_reg { 89 unsigned int offset; 90 unsigned int bitend; 91 unsigned int bitstart; 92 unsigned int disable; 93 unsigned int enable; 94 }; 95 96 /** 97 * struct rockchip_chg_det_reg - usb charger detect registers 98 * @cp_det: charging port detected successfully. 99 * @dcp_det: dedicated charging port detected successfully. 100 * @dp_det: assert data pin connect successfully. 101 * @idm_sink_en: open dm sink curren. 102 * @idp_sink_en: open dp sink current. 103 * @idp_src_en: open dm source current. 104 * @rdm_pdwn_en: open dm pull down resistor. 105 * @vdm_src_en: open dm voltage source. 106 * @vdp_src_en: open dp voltage source. 107 * @opmode: utmi operational mode. 108 */ 109 struct rockchip_chg_det_reg { 110 struct usb2phy_reg cp_det; 111 struct usb2phy_reg dcp_det; 112 struct usb2phy_reg dp_det; 113 struct usb2phy_reg idm_sink_en; 114 struct usb2phy_reg idp_sink_en; 115 struct usb2phy_reg idp_src_en; 116 struct usb2phy_reg rdm_pdwn_en; 117 struct usb2phy_reg vdm_src_en; 118 struct usb2phy_reg vdp_src_en; 119 struct usb2phy_reg opmode; 120 }; 121 122 /** 123 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration. 124 * @phy_sus: phy suspend register. 125 * @bvalid_det_en: vbus valid rise detection enable register. 126 * @bvalid_det_st: vbus valid rise detection status register. 127 * @bvalid_det_clr: vbus valid rise detection clear register. 128 * @ls_det_en: linestate detection enable register. 129 * @ls_det_st: linestate detection state register. 130 * @ls_det_clr: linestate detection clear register. 131 * @utmi_avalid: utmi vbus avalid status register. 132 * @utmi_bvalid: utmi vbus bvalid status register. 133 * @utmi_ls: utmi linestate state register. 134 * @utmi_hstdet: utmi host disconnect register. 135 */ 136 struct rockchip_usb2phy_port_cfg { 137 struct usb2phy_reg phy_sus; 138 struct usb2phy_reg bvalid_det_en; 139 struct usb2phy_reg bvalid_det_st; 140 struct usb2phy_reg bvalid_det_clr; 141 struct usb2phy_reg ls_det_en; 142 struct usb2phy_reg ls_det_st; 143 struct usb2phy_reg ls_det_clr; 144 struct usb2phy_reg utmi_avalid; 145 struct usb2phy_reg utmi_bvalid; 146 struct usb2phy_reg utmi_ls; 147 struct usb2phy_reg utmi_hstdet; 148 }; 149 150 /** 151 * struct rockchip_usb2phy_cfg - usb-phy configuration. 152 * @reg: the address offset of grf for usb-phy config. 153 * @num_ports: specify how many ports that the phy has. 154 * @clkout_ctl: keep on/turn off output clk of phy. 155 * @port_cfgs: usb-phy port configurations. 156 * @chg_det: charger detection registers. 157 */ 158 struct rockchip_usb2phy_cfg { 159 unsigned int reg; 160 unsigned int num_ports; 161 struct usb2phy_reg clkout_ctl; 162 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 163 const struct rockchip_chg_det_reg chg_det; 164 }; 165 166 /** 167 * struct rockchip_usb2phy_port - usb-phy port data. 168 * @phy: generic phy. 169 * @port_id: flag for otg port or host port. 170 * @suspended: phy suspended flag. 171 * @vbus_attached: otg device vbus status. 172 * @bvalid_irq: IRQ number assigned for vbus valid rise detection. 173 * @ls_irq: IRQ number assigned for linestate detection. 174 * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate 175 * irqs to one irq in otg-port. 176 * @mutex: for register updating in sm_work. 177 * @chg_work: charge detect work. 178 * @otg_sm_work: OTG state machine work. 179 * @sm_work: HOST state machine work. 180 * @port_cfg: port register configuration, assigned by driver data. 181 * @event_nb: hold event notification callback. 182 * @state: define OTG enumeration states before device reset. 183 * @mode: the dr_mode of the controller. 184 */ 185 struct rockchip_usb2phy_port { 186 struct phy *phy; 187 unsigned int port_id; 188 bool suspended; 189 bool vbus_attached; 190 int bvalid_irq; 191 int ls_irq; 192 int otg_mux_irq; 193 struct mutex mutex; 194 struct delayed_work chg_work; 195 struct delayed_work otg_sm_work; 196 struct delayed_work sm_work; 197 const struct rockchip_usb2phy_port_cfg *port_cfg; 198 struct notifier_block event_nb; 199 enum usb_otg_state state; 200 enum usb_dr_mode mode; 201 }; 202 203 /** 204 * struct rockchip_usb2phy - usb2.0 phy driver data. 205 * @dev: pointer to device. 206 * @grf: General Register Files regmap. 207 * @usbgrf: USB General Register Files regmap. 208 * @clk: clock struct of phy input clk. 209 * @clk480m: clock struct of phy output clk. 210 * @clk480m_hw: clock struct of phy output clk management. 211 * @chg_state: states involved in USB charger detection. 212 * @chg_type: USB charger types. 213 * @dcd_retries: The retry count used to track Data contact 214 * detection process. 215 * @edev: extcon device for notification registration 216 * @phy_cfg: phy register configuration, assigned by driver data. 217 * @ports: phy port instance. 218 */ 219 struct rockchip_usb2phy { 220 struct device *dev; 221 struct regmap *grf; 222 struct regmap *usbgrf; 223 struct clk *clk; 224 struct clk *clk480m; 225 struct clk_hw clk480m_hw; 226 enum usb_chg_state chg_state; 227 enum power_supply_type chg_type; 228 u8 dcd_retries; 229 struct extcon_dev *edev; 230 const struct rockchip_usb2phy_cfg *phy_cfg; 231 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS]; 232 }; 233 234 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) 235 { 236 return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf; 237 } 238 239 static inline int property_enable(struct regmap *base, 240 const struct usb2phy_reg *reg, bool en) 241 { 242 unsigned int val, mask, tmp; 243 244 tmp = en ? reg->enable : reg->disable; 245 mask = GENMASK(reg->bitend, reg->bitstart); 246 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 247 248 return regmap_write(base, reg->offset, val); 249 } 250 251 static inline bool property_enabled(struct regmap *base, 252 const struct usb2phy_reg *reg) 253 { 254 int ret; 255 unsigned int tmp, orig; 256 unsigned int mask = GENMASK(reg->bitend, reg->bitstart); 257 258 ret = regmap_read(base, reg->offset, &orig); 259 if (ret) 260 return false; 261 262 tmp = (orig & mask) >> reg->bitstart; 263 return tmp == reg->enable; 264 } 265 266 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw) 267 { 268 struct rockchip_usb2phy *rphy = 269 container_of(hw, struct rockchip_usb2phy, clk480m_hw); 270 struct regmap *base = get_reg_base(rphy); 271 int ret; 272 273 /* turn on 480m clk output if it is off */ 274 if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) { 275 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true); 276 if (ret) 277 return ret; 278 279 /* waiting for the clk become stable */ 280 usleep_range(1200, 1300); 281 } 282 283 return 0; 284 } 285 286 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw) 287 { 288 struct rockchip_usb2phy *rphy = 289 container_of(hw, struct rockchip_usb2phy, clk480m_hw); 290 struct regmap *base = get_reg_base(rphy); 291 292 /* turn off 480m clk output */ 293 property_enable(base, &rphy->phy_cfg->clkout_ctl, false); 294 } 295 296 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw) 297 { 298 struct rockchip_usb2phy *rphy = 299 container_of(hw, struct rockchip_usb2phy, clk480m_hw); 300 struct regmap *base = get_reg_base(rphy); 301 302 return property_enabled(base, &rphy->phy_cfg->clkout_ctl); 303 } 304 305 static unsigned long 306 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw, 307 unsigned long parent_rate) 308 { 309 return 480000000; 310 } 311 312 static const struct clk_ops rockchip_usb2phy_clkout_ops = { 313 .prepare = rockchip_usb2phy_clk480m_prepare, 314 .unprepare = rockchip_usb2phy_clk480m_unprepare, 315 .is_prepared = rockchip_usb2phy_clk480m_prepared, 316 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate, 317 }; 318 319 static void rockchip_usb2phy_clk480m_unregister(void *data) 320 { 321 struct rockchip_usb2phy *rphy = data; 322 323 of_clk_del_provider(rphy->dev->of_node); 324 clk_unregister(rphy->clk480m); 325 } 326 327 static int 328 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy) 329 { 330 struct device_node *node = rphy->dev->of_node; 331 struct clk_init_data init; 332 const char *clk_name; 333 int ret; 334 335 init.flags = 0; 336 init.name = "clk_usbphy_480m"; 337 init.ops = &rockchip_usb2phy_clkout_ops; 338 339 /* optional override of the clockname */ 340 of_property_read_string(node, "clock-output-names", &init.name); 341 342 if (rphy->clk) { 343 clk_name = __clk_get_name(rphy->clk); 344 init.parent_names = &clk_name; 345 init.num_parents = 1; 346 } else { 347 init.parent_names = NULL; 348 init.num_parents = 0; 349 } 350 351 rphy->clk480m_hw.init = &init; 352 353 /* register the clock */ 354 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw); 355 if (IS_ERR(rphy->clk480m)) { 356 ret = PTR_ERR(rphy->clk480m); 357 goto err_ret; 358 } 359 360 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m); 361 if (ret < 0) 362 goto err_clk_provider; 363 364 ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister, 365 rphy); 366 if (ret < 0) 367 goto err_unreg_action; 368 369 return 0; 370 371 err_unreg_action: 372 of_clk_del_provider(node); 373 err_clk_provider: 374 clk_unregister(rphy->clk480m); 375 err_ret: 376 return ret; 377 } 378 379 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy) 380 { 381 int ret; 382 struct device_node *node = rphy->dev->of_node; 383 struct extcon_dev *edev; 384 385 if (of_property_read_bool(node, "extcon")) { 386 edev = extcon_get_edev_by_phandle(rphy->dev, 0); 387 if (IS_ERR(edev)) { 388 if (PTR_ERR(edev) != -EPROBE_DEFER) 389 dev_err(rphy->dev, "Invalid or missing extcon\n"); 390 return PTR_ERR(edev); 391 } 392 } else { 393 /* Initialize extcon device */ 394 edev = devm_extcon_dev_allocate(rphy->dev, 395 rockchip_usb2phy_extcon_cable); 396 397 if (IS_ERR(edev)) 398 return -ENOMEM; 399 400 ret = devm_extcon_dev_register(rphy->dev, edev); 401 if (ret) { 402 dev_err(rphy->dev, "failed to register extcon device\n"); 403 return ret; 404 } 405 } 406 407 rphy->edev = edev; 408 409 return 0; 410 } 411 412 static int rockchip_usb2phy_init(struct phy *phy) 413 { 414 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 415 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); 416 int ret = 0; 417 418 mutex_lock(&rport->mutex); 419 420 if (rport->port_id == USB2PHY_PORT_OTG) { 421 if (rport->mode != USB_DR_MODE_HOST && 422 rport->mode != USB_DR_MODE_UNKNOWN) { 423 /* clear bvalid status and enable bvalid detect irq */ 424 ret = property_enable(rphy->grf, 425 &rport->port_cfg->bvalid_det_clr, 426 true); 427 if (ret) 428 goto out; 429 430 ret = property_enable(rphy->grf, 431 &rport->port_cfg->bvalid_det_en, 432 true); 433 if (ret) 434 goto out; 435 436 schedule_delayed_work(&rport->otg_sm_work, 437 OTG_SCHEDULE_DELAY * 3); 438 } else { 439 /* If OTG works in host only mode, do nothing. */ 440 dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode); 441 } 442 } else if (rport->port_id == USB2PHY_PORT_HOST) { 443 /* clear linestate and enable linestate detect irq */ 444 ret = property_enable(rphy->grf, 445 &rport->port_cfg->ls_det_clr, true); 446 if (ret) 447 goto out; 448 449 ret = property_enable(rphy->grf, 450 &rport->port_cfg->ls_det_en, true); 451 if (ret) 452 goto out; 453 454 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY); 455 } 456 457 out: 458 mutex_unlock(&rport->mutex); 459 return ret; 460 } 461 462 static int rockchip_usb2phy_power_on(struct phy *phy) 463 { 464 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 465 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); 466 struct regmap *base = get_reg_base(rphy); 467 int ret; 468 469 dev_dbg(&rport->phy->dev, "port power on\n"); 470 471 if (!rport->suspended) 472 return 0; 473 474 ret = clk_prepare_enable(rphy->clk480m); 475 if (ret) 476 return ret; 477 478 ret = property_enable(base, &rport->port_cfg->phy_sus, false); 479 if (ret) 480 return ret; 481 482 /* waiting for the utmi_clk to become stable */ 483 usleep_range(1500, 2000); 484 485 rport->suspended = false; 486 return 0; 487 } 488 489 static int rockchip_usb2phy_power_off(struct phy *phy) 490 { 491 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 492 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); 493 struct regmap *base = get_reg_base(rphy); 494 int ret; 495 496 dev_dbg(&rport->phy->dev, "port power off\n"); 497 498 if (rport->suspended) 499 return 0; 500 501 ret = property_enable(base, &rport->port_cfg->phy_sus, true); 502 if (ret) 503 return ret; 504 505 rport->suspended = true; 506 clk_disable_unprepare(rphy->clk480m); 507 508 return 0; 509 } 510 511 static int rockchip_usb2phy_exit(struct phy *phy) 512 { 513 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 514 515 if (rport->port_id == USB2PHY_PORT_OTG && 516 rport->mode != USB_DR_MODE_HOST && 517 rport->mode != USB_DR_MODE_UNKNOWN) { 518 cancel_delayed_work_sync(&rport->otg_sm_work); 519 cancel_delayed_work_sync(&rport->chg_work); 520 } else if (rport->port_id == USB2PHY_PORT_HOST) 521 cancel_delayed_work_sync(&rport->sm_work); 522 523 return 0; 524 } 525 526 static const struct phy_ops rockchip_usb2phy_ops = { 527 .init = rockchip_usb2phy_init, 528 .exit = rockchip_usb2phy_exit, 529 .power_on = rockchip_usb2phy_power_on, 530 .power_off = rockchip_usb2phy_power_off, 531 .owner = THIS_MODULE, 532 }; 533 534 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work) 535 { 536 struct rockchip_usb2phy_port *rport = 537 container_of(work, struct rockchip_usb2phy_port, 538 otg_sm_work.work); 539 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 540 static unsigned int cable; 541 unsigned long delay; 542 bool vbus_attach, sch_work, notify_charger; 543 544 vbus_attach = property_enabled(rphy->grf, 545 &rport->port_cfg->utmi_bvalid); 546 547 sch_work = false; 548 notify_charger = false; 549 delay = OTG_SCHEDULE_DELAY; 550 dev_dbg(&rport->phy->dev, "%s otg sm work\n", 551 usb_otg_state_string(rport->state)); 552 553 switch (rport->state) { 554 case OTG_STATE_UNDEFINED: 555 rport->state = OTG_STATE_B_IDLE; 556 if (!vbus_attach) 557 rockchip_usb2phy_power_off(rport->phy); 558 /* fall through */ 559 case OTG_STATE_B_IDLE: 560 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) { 561 dev_dbg(&rport->phy->dev, "usb otg host connect\n"); 562 rport->state = OTG_STATE_A_HOST; 563 rockchip_usb2phy_power_on(rport->phy); 564 return; 565 } else if (vbus_attach) { 566 dev_dbg(&rport->phy->dev, "vbus_attach\n"); 567 switch (rphy->chg_state) { 568 case USB_CHG_STATE_UNDEFINED: 569 schedule_delayed_work(&rport->chg_work, 0); 570 return; 571 case USB_CHG_STATE_DETECTED: 572 switch (rphy->chg_type) { 573 case POWER_SUPPLY_TYPE_USB: 574 dev_dbg(&rport->phy->dev, "sdp cable is connected\n"); 575 rockchip_usb2phy_power_on(rport->phy); 576 rport->state = OTG_STATE_B_PERIPHERAL; 577 notify_charger = true; 578 sch_work = true; 579 cable = EXTCON_CHG_USB_SDP; 580 break; 581 case POWER_SUPPLY_TYPE_USB_DCP: 582 dev_dbg(&rport->phy->dev, "dcp cable is connected\n"); 583 rockchip_usb2phy_power_off(rport->phy); 584 notify_charger = true; 585 sch_work = true; 586 cable = EXTCON_CHG_USB_DCP; 587 break; 588 case POWER_SUPPLY_TYPE_USB_CDP: 589 dev_dbg(&rport->phy->dev, "cdp cable is connected\n"); 590 rockchip_usb2phy_power_on(rport->phy); 591 rport->state = OTG_STATE_B_PERIPHERAL; 592 notify_charger = true; 593 sch_work = true; 594 cable = EXTCON_CHG_USB_CDP; 595 break; 596 default: 597 break; 598 } 599 break; 600 default: 601 break; 602 } 603 } else { 604 notify_charger = true; 605 rphy->chg_state = USB_CHG_STATE_UNDEFINED; 606 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; 607 } 608 609 if (rport->vbus_attached != vbus_attach) { 610 rport->vbus_attached = vbus_attach; 611 612 if (notify_charger && rphy->edev) { 613 extcon_set_state_sync(rphy->edev, 614 cable, vbus_attach); 615 if (cable == EXTCON_CHG_USB_SDP) 616 extcon_set_state_sync(rphy->edev, 617 EXTCON_USB, 618 vbus_attach); 619 } 620 } 621 break; 622 case OTG_STATE_B_PERIPHERAL: 623 if (!vbus_attach) { 624 dev_dbg(&rport->phy->dev, "usb disconnect\n"); 625 rphy->chg_state = USB_CHG_STATE_UNDEFINED; 626 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; 627 rport->state = OTG_STATE_B_IDLE; 628 delay = 0; 629 rockchip_usb2phy_power_off(rport->phy); 630 } 631 sch_work = true; 632 break; 633 case OTG_STATE_A_HOST: 634 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) { 635 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n"); 636 rport->state = OTG_STATE_B_IDLE; 637 rockchip_usb2phy_power_off(rport->phy); 638 } 639 break; 640 default: 641 break; 642 } 643 644 if (sch_work) 645 schedule_delayed_work(&rport->otg_sm_work, delay); 646 } 647 648 static const char *chg_to_string(enum power_supply_type chg_type) 649 { 650 switch (chg_type) { 651 case POWER_SUPPLY_TYPE_USB: 652 return "USB_SDP_CHARGER"; 653 case POWER_SUPPLY_TYPE_USB_DCP: 654 return "USB_DCP_CHARGER"; 655 case POWER_SUPPLY_TYPE_USB_CDP: 656 return "USB_CDP_CHARGER"; 657 default: 658 return "INVALID_CHARGER"; 659 } 660 } 661 662 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 663 bool en) 664 { 665 struct regmap *base = get_reg_base(rphy); 666 667 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 668 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 669 } 670 671 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 672 bool en) 673 { 674 struct regmap *base = get_reg_base(rphy); 675 676 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 677 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 678 } 679 680 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 681 bool en) 682 { 683 struct regmap *base = get_reg_base(rphy); 684 685 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 686 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 687 } 688 689 #define CHG_DCD_POLL_TIME (100 * HZ / 1000) 690 #define CHG_DCD_MAX_RETRIES 6 691 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000) 692 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000) 693 static void rockchip_chg_detect_work(struct work_struct *work) 694 { 695 struct rockchip_usb2phy_port *rport = 696 container_of(work, struct rockchip_usb2phy_port, chg_work.work); 697 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 698 struct regmap *base = get_reg_base(rphy); 699 bool is_dcd, tmout, vout; 700 unsigned long delay; 701 702 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n", 703 rphy->chg_state); 704 switch (rphy->chg_state) { 705 case USB_CHG_STATE_UNDEFINED: 706 if (!rport->suspended) 707 rockchip_usb2phy_power_off(rport->phy); 708 /* put the controller in non-driving mode */ 709 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 710 /* Start DCD processing stage 1 */ 711 rockchip_chg_enable_dcd(rphy, true); 712 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD; 713 rphy->dcd_retries = 0; 714 delay = CHG_DCD_POLL_TIME; 715 break; 716 case USB_CHG_STATE_WAIT_FOR_DCD: 717 /* get data contact detection status */ 718 is_dcd = property_enabled(rphy->grf, 719 &rphy->phy_cfg->chg_det.dp_det); 720 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES; 721 /* stage 2 */ 722 if (is_dcd || tmout) { 723 /* stage 4 */ 724 /* Turn off DCD circuitry */ 725 rockchip_chg_enable_dcd(rphy, false); 726 /* Voltage Source on DP, Probe on DM */ 727 rockchip_chg_enable_primary_det(rphy, true); 728 delay = CHG_PRIMARY_DET_TIME; 729 rphy->chg_state = USB_CHG_STATE_DCD_DONE; 730 } else { 731 /* stage 3 */ 732 delay = CHG_DCD_POLL_TIME; 733 } 734 break; 735 case USB_CHG_STATE_DCD_DONE: 736 vout = property_enabled(rphy->grf, 737 &rphy->phy_cfg->chg_det.cp_det); 738 rockchip_chg_enable_primary_det(rphy, false); 739 if (vout) { 740 /* Voltage Source on DM, Probe on DP */ 741 rockchip_chg_enable_secondary_det(rphy, true); 742 delay = CHG_SECONDARY_DET_TIME; 743 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE; 744 } else { 745 if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) { 746 /* floating charger found */ 747 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP; 748 rphy->chg_state = USB_CHG_STATE_DETECTED; 749 delay = 0; 750 } else { 751 rphy->chg_type = POWER_SUPPLY_TYPE_USB; 752 rphy->chg_state = USB_CHG_STATE_DETECTED; 753 delay = 0; 754 } 755 } 756 break; 757 case USB_CHG_STATE_PRIMARY_DONE: 758 vout = property_enabled(rphy->grf, 759 &rphy->phy_cfg->chg_det.dcp_det); 760 /* Turn off voltage source */ 761 rockchip_chg_enable_secondary_det(rphy, false); 762 if (vout) 763 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP; 764 else 765 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP; 766 /* fall through */ 767 case USB_CHG_STATE_SECONDARY_DONE: 768 rphy->chg_state = USB_CHG_STATE_DETECTED; 769 delay = 0; 770 /* fall through */ 771 case USB_CHG_STATE_DETECTED: 772 /* put the controller in normal mode */ 773 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 774 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); 775 dev_info(&rport->phy->dev, "charger = %s\n", 776 chg_to_string(rphy->chg_type)); 777 return; 778 default: 779 return; 780 } 781 782 schedule_delayed_work(&rport->chg_work, delay); 783 } 784 785 /* 786 * The function manage host-phy port state and suspend/resume phy port 787 * to save power. 788 * 789 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether 790 * devices is disconnect or not. Besides, we do not need care it is FS/LS 791 * disconnected or HS disconnected, actually, we just only need get the 792 * device is disconnected at last through rearm the delayed work, 793 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case. 794 * 795 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke 796 * some clk related APIs, so do not invoke it from interrupt context directly. 797 */ 798 static void rockchip_usb2phy_sm_work(struct work_struct *work) 799 { 800 struct rockchip_usb2phy_port *rport = 801 container_of(work, struct rockchip_usb2phy_port, sm_work.work); 802 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 803 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend - 804 rport->port_cfg->utmi_hstdet.bitstart + 1; 805 unsigned int ul, uhd, state; 806 unsigned int ul_mask, uhd_mask; 807 int ret; 808 809 mutex_lock(&rport->mutex); 810 811 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul); 812 if (ret < 0) 813 goto next_schedule; 814 815 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd); 816 if (ret < 0) 817 goto next_schedule; 818 819 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend, 820 rport->port_cfg->utmi_hstdet.bitstart); 821 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend, 822 rport->port_cfg->utmi_ls.bitstart); 823 824 /* stitch on utmi_ls and utmi_hstdet as phy state */ 825 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) | 826 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh); 827 828 switch (state) { 829 case PHY_STATE_HS_ONLINE: 830 dev_dbg(&rport->phy->dev, "HS online\n"); 831 break; 832 case PHY_STATE_FS_LS_ONLINE: 833 /* 834 * For FS/LS device, the online state share with connect state 835 * from utmi_ls and utmi_hstdet register, so we distinguish 836 * them via suspended flag. 837 * 838 * Plus, there are two cases, one is D- Line pull-up, and D+ 839 * line pull-down, the state is 4; another is D+ line pull-up, 840 * and D- line pull-down, the state is 2. 841 */ 842 if (!rport->suspended) { 843 /* D- line pull-up, D+ line pull-down */ 844 dev_dbg(&rport->phy->dev, "FS/LS online\n"); 845 break; 846 } 847 /* fall through */ 848 case PHY_STATE_CONNECT: 849 if (rport->suspended) { 850 dev_dbg(&rport->phy->dev, "Connected\n"); 851 rockchip_usb2phy_power_on(rport->phy); 852 rport->suspended = false; 853 } else { 854 /* D+ line pull-up, D- line pull-down */ 855 dev_dbg(&rport->phy->dev, "FS/LS online\n"); 856 } 857 break; 858 case PHY_STATE_DISCONNECT: 859 if (!rport->suspended) { 860 dev_dbg(&rport->phy->dev, "Disconnected\n"); 861 rockchip_usb2phy_power_off(rport->phy); 862 rport->suspended = true; 863 } 864 865 /* 866 * activate the linestate detection to get the next device 867 * plug-in irq. 868 */ 869 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true); 870 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true); 871 872 /* 873 * we don't need to rearm the delayed work when the phy port 874 * is suspended. 875 */ 876 mutex_unlock(&rport->mutex); 877 return; 878 default: 879 dev_dbg(&rport->phy->dev, "unknown phy state\n"); 880 break; 881 } 882 883 next_schedule: 884 mutex_unlock(&rport->mutex); 885 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY); 886 } 887 888 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data) 889 { 890 struct rockchip_usb2phy_port *rport = data; 891 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 892 893 if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st)) 894 return IRQ_NONE; 895 896 mutex_lock(&rport->mutex); 897 898 /* disable linestate detect irq and clear its status */ 899 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false); 900 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true); 901 902 mutex_unlock(&rport->mutex); 903 904 /* 905 * In this case for host phy port, a new device is plugged in, 906 * meanwhile, if the phy port is suspended, we need rearm the work to 907 * resume it and mange its states; otherwise, we do nothing about that. 908 */ 909 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST) 910 rockchip_usb2phy_sm_work(&rport->sm_work.work); 911 912 return IRQ_HANDLED; 913 } 914 915 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data) 916 { 917 struct rockchip_usb2phy_port *rport = data; 918 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 919 920 if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st)) 921 return IRQ_NONE; 922 923 mutex_lock(&rport->mutex); 924 925 /* clear bvalid detect irq pending status */ 926 property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true); 927 928 mutex_unlock(&rport->mutex); 929 930 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); 931 932 return IRQ_HANDLED; 933 } 934 935 static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data) 936 { 937 struct rockchip_usb2phy_port *rport = data; 938 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 939 940 if (property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st)) 941 return rockchip_usb2phy_bvalid_irq(irq, data); 942 else 943 return IRQ_NONE; 944 } 945 946 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy, 947 struct rockchip_usb2phy_port *rport, 948 struct device_node *child_np) 949 { 950 int ret; 951 952 rport->port_id = USB2PHY_PORT_HOST; 953 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 954 rport->suspended = true; 955 956 mutex_init(&rport->mutex); 957 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work); 958 959 rport->ls_irq = of_irq_get_byname(child_np, "linestate"); 960 if (rport->ls_irq < 0) { 961 dev_err(rphy->dev, "no linestate irq provided\n"); 962 return rport->ls_irq; 963 } 964 965 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL, 966 rockchip_usb2phy_linestate_irq, 967 IRQF_ONESHOT, 968 "rockchip_usb2phy", rport); 969 if (ret) { 970 dev_err(rphy->dev, "failed to request linestate irq handle\n"); 971 return ret; 972 } 973 974 return 0; 975 } 976 977 static int rockchip_otg_event(struct notifier_block *nb, 978 unsigned long event, void *ptr) 979 { 980 struct rockchip_usb2phy_port *rport = 981 container_of(nb, struct rockchip_usb2phy_port, event_nb); 982 983 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY); 984 985 return NOTIFY_DONE; 986 } 987 988 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, 989 struct rockchip_usb2phy_port *rport, 990 struct device_node *child_np) 991 { 992 int ret; 993 994 rport->port_id = USB2PHY_PORT_OTG; 995 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 996 rport->state = OTG_STATE_UNDEFINED; 997 998 /* 999 * set suspended flag to true, but actually don't 1000 * put phy in suspend mode, it aims to enable usb 1001 * phy and clock in power_on() called by usb controller 1002 * driver during probe. 1003 */ 1004 rport->suspended = true; 1005 rport->vbus_attached = false; 1006 1007 mutex_init(&rport->mutex); 1008 1009 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1); 1010 if (rport->mode == USB_DR_MODE_HOST || 1011 rport->mode == USB_DR_MODE_UNKNOWN) { 1012 ret = 0; 1013 goto out; 1014 } 1015 1016 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work); 1017 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work); 1018 1019 /* 1020 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate 1021 * interrupts muxed together, so probe the otg-mux interrupt first, 1022 * if not found, then look for the regular interrupts one by one. 1023 */ 1024 rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux"); 1025 if (rport->otg_mux_irq > 0) { 1026 ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq, 1027 NULL, 1028 rockchip_usb2phy_otg_mux_irq, 1029 IRQF_ONESHOT, 1030 "rockchip_usb2phy_otg", 1031 rport); 1032 if (ret) { 1033 dev_err(rphy->dev, 1034 "failed to request otg-mux irq handle\n"); 1035 goto out; 1036 } 1037 } else { 1038 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid"); 1039 if (rport->bvalid_irq < 0) { 1040 dev_err(rphy->dev, "no vbus valid irq provided\n"); 1041 ret = rport->bvalid_irq; 1042 goto out; 1043 } 1044 1045 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, 1046 NULL, 1047 rockchip_usb2phy_bvalid_irq, 1048 IRQF_ONESHOT, 1049 "rockchip_usb2phy_bvalid", 1050 rport); 1051 if (ret) { 1052 dev_err(rphy->dev, 1053 "failed to request otg-bvalid irq handle\n"); 1054 goto out; 1055 } 1056 } 1057 1058 if (!IS_ERR(rphy->edev)) { 1059 rport->event_nb.notifier_call = rockchip_otg_event; 1060 1061 ret = devm_extcon_register_notifier(rphy->dev, rphy->edev, 1062 EXTCON_USB_HOST, &rport->event_nb); 1063 if (ret) 1064 dev_err(rphy->dev, "register USB HOST notifier failed\n"); 1065 } 1066 1067 out: 1068 return ret; 1069 } 1070 1071 static int rockchip_usb2phy_probe(struct platform_device *pdev) 1072 { 1073 struct device *dev = &pdev->dev; 1074 struct device_node *np = dev->of_node; 1075 struct device_node *child_np; 1076 struct phy_provider *provider; 1077 struct rockchip_usb2phy *rphy; 1078 const struct rockchip_usb2phy_cfg *phy_cfgs; 1079 const struct of_device_id *match; 1080 unsigned int reg; 1081 int index, ret; 1082 1083 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL); 1084 if (!rphy) 1085 return -ENOMEM; 1086 1087 match = of_match_device(dev->driver->of_match_table, dev); 1088 if (!match || !match->data) { 1089 dev_err(dev, "phy configs are not assigned!\n"); 1090 return -EINVAL; 1091 } 1092 1093 if (!dev->parent || !dev->parent->of_node) 1094 return -EINVAL; 1095 1096 rphy->grf = syscon_node_to_regmap(dev->parent->of_node); 1097 if (IS_ERR(rphy->grf)) 1098 return PTR_ERR(rphy->grf); 1099 1100 if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) { 1101 rphy->usbgrf = 1102 syscon_regmap_lookup_by_phandle(dev->of_node, 1103 "rockchip,usbgrf"); 1104 if (IS_ERR(rphy->usbgrf)) 1105 return PTR_ERR(rphy->usbgrf); 1106 } else { 1107 rphy->usbgrf = NULL; 1108 } 1109 1110 if (of_property_read_u32(np, "reg", ®)) { 1111 dev_err(dev, "the reg property is not assigned in %pOFn node\n", 1112 np); 1113 return -EINVAL; 1114 } 1115 1116 rphy->dev = dev; 1117 phy_cfgs = match->data; 1118 rphy->chg_state = USB_CHG_STATE_UNDEFINED; 1119 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; 1120 platform_set_drvdata(pdev, rphy); 1121 1122 ret = rockchip_usb2phy_extcon_register(rphy); 1123 if (ret) 1124 return ret; 1125 1126 /* find out a proper config which can be matched with dt. */ 1127 index = 0; 1128 while (phy_cfgs[index].reg) { 1129 if (phy_cfgs[index].reg == reg) { 1130 rphy->phy_cfg = &phy_cfgs[index]; 1131 break; 1132 } 1133 1134 ++index; 1135 } 1136 1137 if (!rphy->phy_cfg) { 1138 dev_err(dev, "no phy-config can be matched with %pOFn node\n", 1139 np); 1140 return -EINVAL; 1141 } 1142 1143 rphy->clk = of_clk_get_by_name(np, "phyclk"); 1144 if (!IS_ERR(rphy->clk)) { 1145 clk_prepare_enable(rphy->clk); 1146 } else { 1147 dev_info(&pdev->dev, "no phyclk specified\n"); 1148 rphy->clk = NULL; 1149 } 1150 1151 ret = rockchip_usb2phy_clk480m_register(rphy); 1152 if (ret) { 1153 dev_err(dev, "failed to register 480m output clock\n"); 1154 goto disable_clks; 1155 } 1156 1157 index = 0; 1158 for_each_available_child_of_node(np, child_np) { 1159 struct rockchip_usb2phy_port *rport = &rphy->ports[index]; 1160 struct phy *phy; 1161 1162 /* This driver aims to support both otg-port and host-port */ 1163 if (!of_node_name_eq(child_np, "host-port") && 1164 !of_node_name_eq(child_np, "otg-port")) 1165 goto next_child; 1166 1167 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops); 1168 if (IS_ERR(phy)) { 1169 dev_err(dev, "failed to create phy\n"); 1170 ret = PTR_ERR(phy); 1171 goto put_child; 1172 } 1173 1174 rport->phy = phy; 1175 phy_set_drvdata(rport->phy, rport); 1176 1177 /* initialize otg/host port separately */ 1178 if (of_node_name_eq(child_np, "host-port")) { 1179 ret = rockchip_usb2phy_host_port_init(rphy, rport, 1180 child_np); 1181 if (ret) 1182 goto put_child; 1183 } else { 1184 ret = rockchip_usb2phy_otg_port_init(rphy, rport, 1185 child_np); 1186 if (ret) 1187 goto put_child; 1188 } 1189 1190 next_child: 1191 /* to prevent out of boundary */ 1192 if (++index >= rphy->phy_cfg->num_ports) 1193 break; 1194 } 1195 1196 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1197 return PTR_ERR_OR_ZERO(provider); 1198 1199 put_child: 1200 of_node_put(child_np); 1201 disable_clks: 1202 if (rphy->clk) { 1203 clk_disable_unprepare(rphy->clk); 1204 clk_put(rphy->clk); 1205 } 1206 return ret; 1207 } 1208 1209 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = { 1210 { 1211 .reg = 0x760, 1212 .num_ports = 2, 1213 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 1214 .port_cfgs = { 1215 [USB2PHY_PORT_OTG] = { 1216 .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 }, 1217 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1218 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1219 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1220 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1221 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1222 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1223 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 1224 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 1225 }, 1226 [USB2PHY_PORT_HOST] = { 1227 .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 }, 1228 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1229 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1230 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1231 } 1232 }, 1233 .chg_det = { 1234 .opmode = { 0x0760, 3, 0, 5, 1 }, 1235 .cp_det = { 0x0884, 4, 4, 0, 1 }, 1236 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 1237 .dp_det = { 0x0884, 5, 5, 0, 1 }, 1238 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 1239 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 1240 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 1241 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 1242 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 1243 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 1244 }, 1245 }, 1246 { 1247 .reg = 0x800, 1248 .num_ports = 2, 1249 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 1250 .port_cfgs = { 1251 [USB2PHY_PORT_OTG] = { 1252 .phy_sus = { 0x800, 15, 0, 0, 0x1d1 }, 1253 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 1254 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 1255 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 1256 }, 1257 [USB2PHY_PORT_HOST] = { 1258 .phy_sus = { 0x804, 15, 0, 0, 0x1d1 }, 1259 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 1260 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 1261 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 1262 } 1263 }, 1264 }, 1265 { /* sentinel */ } 1266 }; 1267 1268 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 1269 { 1270 .reg = 0x100, 1271 .num_ports = 2, 1272 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1273 .port_cfgs = { 1274 [USB2PHY_PORT_OTG] = { 1275 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 }, 1276 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1277 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1278 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1279 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1280 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1281 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1282 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1283 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1284 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1285 }, 1286 [USB2PHY_PORT_HOST] = { 1287 .phy_sus = { 0x104, 15, 0, 0, 0x1d1 }, 1288 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1289 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1290 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1291 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1292 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1293 } 1294 }, 1295 .chg_det = { 1296 .opmode = { 0x0100, 3, 0, 5, 1 }, 1297 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1298 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1299 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1300 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1301 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1302 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1303 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1304 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1305 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1306 }, 1307 }, 1308 { /* sentinel */ } 1309 }; 1310 1311 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = { 1312 { 1313 .reg = 0x700, 1314 .num_ports = 2, 1315 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 1316 .port_cfgs = { 1317 [USB2PHY_PORT_HOST] = { 1318 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 }, 1319 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1320 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1321 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1322 .utmi_ls = { 0x049c, 14, 13, 0, 1 }, 1323 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 } 1324 } 1325 }, 1326 }, 1327 { /* sentinel */ } 1328 }; 1329 1330 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 1331 { 1332 .reg = 0xe450, 1333 .num_ports = 2, 1334 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 1335 .port_cfgs = { 1336 [USB2PHY_PORT_OTG] = { 1337 .phy_sus = { 0xe454, 1, 0, 2, 1 }, 1338 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1339 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1340 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1341 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1342 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1343 }, 1344 [USB2PHY_PORT_HOST] = { 1345 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 1346 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 1347 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 1348 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 1349 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 1350 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 1351 } 1352 }, 1353 .chg_det = { 1354 .opmode = { 0xe454, 3, 0, 5, 1 }, 1355 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 1356 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 1357 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 1358 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 1359 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 1360 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 1361 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 1362 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 1363 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 1364 }, 1365 }, 1366 { 1367 .reg = 0xe460, 1368 .num_ports = 2, 1369 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 1370 .port_cfgs = { 1371 [USB2PHY_PORT_OTG] = { 1372 .phy_sus = { 0xe464, 1, 0, 2, 1 }, 1373 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1374 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1375 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1376 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1377 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1378 }, 1379 [USB2PHY_PORT_HOST] = { 1380 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 1381 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 1382 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 1383 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 1384 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 1385 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 1386 } 1387 }, 1388 }, 1389 { /* sentinel */ } 1390 }; 1391 1392 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 1393 { 1394 .reg = 0x100, 1395 .num_ports = 2, 1396 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1397 .port_cfgs = { 1398 [USB2PHY_PORT_OTG] = { 1399 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 }, 1400 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1401 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1402 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1403 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1404 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1405 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1406 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1407 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1408 }, 1409 [USB2PHY_PORT_HOST] = { 1410 .phy_sus = { 0x0104, 15, 0, 0, 0x1d1 }, 1411 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1412 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1413 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1414 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1415 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1416 } 1417 }, 1418 .chg_det = { 1419 .opmode = { 0x0100, 3, 0, 5, 1 }, 1420 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1421 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1422 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1423 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1424 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1425 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1426 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1427 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1428 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1429 }, 1430 }, 1431 { /* sentinel */ } 1432 }; 1433 1434 static const struct of_device_id rockchip_usb2phy_dt_match[] = { 1435 { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs }, 1436 { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, 1437 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, 1438 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, 1439 { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs }, 1440 {} 1441 }; 1442 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match); 1443 1444 static struct platform_driver rockchip_usb2phy_driver = { 1445 .probe = rockchip_usb2phy_probe, 1446 .driver = { 1447 .name = "rockchip-usb2phy", 1448 .of_match_table = rockchip_usb2phy_dt_match, 1449 }, 1450 }; 1451 module_platform_driver(rockchip_usb2phy_driver); 1452 1453 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>"); 1454 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver"); 1455 MODULE_LICENSE("GPL v2"); 1456