1 /* 2 * Rockchip USB2.0 PHY with Innosilicon IP block driver 3 * 4 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd 5 * 6 * This program is free software; you can redistribute it and/or modify 7 * it under the terms of the GNU General Public License as published by 8 * the Free Software Foundation; either version 2 of the License, or 9 * (at your option) any later version. 10 * 11 * This program is distributed in the hope that it will be useful, 12 * but WITHOUT ANY WARRANTY; without even the implied warranty of 13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 14 * GNU General Public License for more details. 15 */ 16 17 #include <linux/clk.h> 18 #include <linux/clk-provider.h> 19 #include <linux/delay.h> 20 #include <linux/extcon.h> 21 #include <linux/interrupt.h> 22 #include <linux/io.h> 23 #include <linux/gpio/consumer.h> 24 #include <linux/jiffies.h> 25 #include <linux/kernel.h> 26 #include <linux/module.h> 27 #include <linux/mutex.h> 28 #include <linux/of.h> 29 #include <linux/of_address.h> 30 #include <linux/of_irq.h> 31 #include <linux/of_platform.h> 32 #include <linux/phy/phy.h> 33 #include <linux/platform_device.h> 34 #include <linux/power_supply.h> 35 #include <linux/regmap.h> 36 #include <linux/mfd/syscon.h> 37 #include <linux/usb/of.h> 38 #include <linux/usb/otg.h> 39 40 #define BIT_WRITEABLE_SHIFT 16 41 #define SCHEDULE_DELAY (60 * HZ) 42 #define OTG_SCHEDULE_DELAY (2 * HZ) 43 44 enum rockchip_usb2phy_port_id { 45 USB2PHY_PORT_OTG, 46 USB2PHY_PORT_HOST, 47 USB2PHY_NUM_PORTS, 48 }; 49 50 enum rockchip_usb2phy_host_state { 51 PHY_STATE_HS_ONLINE = 0, 52 PHY_STATE_DISCONNECT = 1, 53 PHY_STATE_CONNECT = 2, 54 PHY_STATE_FS_LS_ONLINE = 4, 55 }; 56 57 /** 58 * Different states involved in USB charger detection. 59 * USB_CHG_STATE_UNDEFINED USB charger is not connected or detection 60 * process is not yet started. 61 * USB_CHG_STATE_WAIT_FOR_DCD Waiting for Data pins contact. 62 * USB_CHG_STATE_DCD_DONE Data pin contact is detected. 63 * USB_CHG_STATE_PRIMARY_DONE Primary detection is completed (Detects 64 * between SDP and DCP/CDP). 65 * USB_CHG_STATE_SECONDARY_DONE Secondary detection is completed (Detects 66 * between DCP and CDP). 67 * USB_CHG_STATE_DETECTED USB charger type is determined. 68 */ 69 enum usb_chg_state { 70 USB_CHG_STATE_UNDEFINED = 0, 71 USB_CHG_STATE_WAIT_FOR_DCD, 72 USB_CHG_STATE_DCD_DONE, 73 USB_CHG_STATE_PRIMARY_DONE, 74 USB_CHG_STATE_SECONDARY_DONE, 75 USB_CHG_STATE_DETECTED, 76 }; 77 78 static const unsigned int rockchip_usb2phy_extcon_cable[] = { 79 EXTCON_USB, 80 EXTCON_USB_HOST, 81 EXTCON_CHG_USB_SDP, 82 EXTCON_CHG_USB_CDP, 83 EXTCON_CHG_USB_DCP, 84 EXTCON_CHG_USB_SLOW, 85 EXTCON_NONE, 86 }; 87 88 struct usb2phy_reg { 89 unsigned int offset; 90 unsigned int bitend; 91 unsigned int bitstart; 92 unsigned int disable; 93 unsigned int enable; 94 }; 95 96 /** 97 * struct rockchip_chg_det_reg: usb charger detect registers 98 * @cp_det: charging port detected successfully. 99 * @dcp_det: dedicated charging port detected successfully. 100 * @dp_det: assert data pin connect successfully. 101 * @idm_sink_en: open dm sink curren. 102 * @idp_sink_en: open dp sink current. 103 * @idp_src_en: open dm source current. 104 * @rdm_pdwn_en: open dm pull down resistor. 105 * @vdm_src_en: open dm voltage source. 106 * @vdp_src_en: open dp voltage source. 107 * @opmode: utmi operational mode. 108 */ 109 struct rockchip_chg_det_reg { 110 struct usb2phy_reg cp_det; 111 struct usb2phy_reg dcp_det; 112 struct usb2phy_reg dp_det; 113 struct usb2phy_reg idm_sink_en; 114 struct usb2phy_reg idp_sink_en; 115 struct usb2phy_reg idp_src_en; 116 struct usb2phy_reg rdm_pdwn_en; 117 struct usb2phy_reg vdm_src_en; 118 struct usb2phy_reg vdp_src_en; 119 struct usb2phy_reg opmode; 120 }; 121 122 /** 123 * struct rockchip_usb2phy_port_cfg: usb-phy port configuration. 124 * @phy_sus: phy suspend register. 125 * @bvalid_det_en: vbus valid rise detection enable register. 126 * @bvalid_det_st: vbus valid rise detection status register. 127 * @bvalid_det_clr: vbus valid rise detection clear register. 128 * @ls_det_en: linestate detection enable register. 129 * @ls_det_st: linestate detection state register. 130 * @ls_det_clr: linestate detection clear register. 131 * @utmi_avalid: utmi vbus avalid status register. 132 * @utmi_bvalid: utmi vbus bvalid status register. 133 * @utmi_ls: utmi linestate state register. 134 * @utmi_hstdet: utmi host disconnect register. 135 */ 136 struct rockchip_usb2phy_port_cfg { 137 struct usb2phy_reg phy_sus; 138 struct usb2phy_reg bvalid_det_en; 139 struct usb2phy_reg bvalid_det_st; 140 struct usb2phy_reg bvalid_det_clr; 141 struct usb2phy_reg ls_det_en; 142 struct usb2phy_reg ls_det_st; 143 struct usb2phy_reg ls_det_clr; 144 struct usb2phy_reg utmi_avalid; 145 struct usb2phy_reg utmi_bvalid; 146 struct usb2phy_reg utmi_ls; 147 struct usb2phy_reg utmi_hstdet; 148 }; 149 150 /** 151 * struct rockchip_usb2phy_cfg: usb-phy configuration. 152 * @reg: the address offset of grf for usb-phy config. 153 * @num_ports: specify how many ports that the phy has. 154 * @clkout_ctl: keep on/turn off output clk of phy. 155 * @chg_det: charger detection registers. 156 */ 157 struct rockchip_usb2phy_cfg { 158 unsigned int reg; 159 unsigned int num_ports; 160 struct usb2phy_reg clkout_ctl; 161 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 162 const struct rockchip_chg_det_reg chg_det; 163 }; 164 165 /** 166 * struct rockchip_usb2phy_port: usb-phy port data. 167 * @port_id: flag for otg port or host port. 168 * @suspended: phy suspended flag. 169 * @utmi_avalid: utmi avalid status usage flag. 170 * true - use avalid to get vbus status 171 * flase - use bvalid to get vbus status 172 * @vbus_attached: otg device vbus status. 173 * @bvalid_irq: IRQ number assigned for vbus valid rise detection. 174 * @ls_irq: IRQ number assigned for linestate detection. 175 * @mutex: for register updating in sm_work. 176 * @chg_work: charge detect work. 177 * @otg_sm_work: OTG state machine work. 178 * @sm_work: HOST state machine work. 179 * @phy_cfg: port register configuration, assigned by driver data. 180 * @event_nb: hold event notification callback. 181 * @state: define OTG enumeration states before device reset. 182 * @mode: the dr_mode of the controller. 183 */ 184 struct rockchip_usb2phy_port { 185 struct phy *phy; 186 unsigned int port_id; 187 bool suspended; 188 bool utmi_avalid; 189 bool vbus_attached; 190 int bvalid_irq; 191 int ls_irq; 192 struct mutex mutex; 193 struct delayed_work chg_work; 194 struct delayed_work otg_sm_work; 195 struct delayed_work sm_work; 196 const struct rockchip_usb2phy_port_cfg *port_cfg; 197 struct notifier_block event_nb; 198 enum usb_otg_state state; 199 enum usb_dr_mode mode; 200 }; 201 202 /** 203 * struct rockchip_usb2phy: usb2.0 phy driver data. 204 * @grf: General Register Files regmap. 205 * @clk: clock struct of phy input clk. 206 * @clk480m: clock struct of phy output clk. 207 * @clk_hw: clock struct of phy output clk management. 208 * @chg_state: states involved in USB charger detection. 209 * @chg_type: USB charger types. 210 * @dcd_retries: The retry count used to track Data contact 211 * detection process. 212 * @edev: extcon device for notification registration 213 * @phy_cfg: phy register configuration, assigned by driver data. 214 * @ports: phy port instance. 215 */ 216 struct rockchip_usb2phy { 217 struct device *dev; 218 struct regmap *grf; 219 struct clk *clk; 220 struct clk *clk480m; 221 struct clk_hw clk480m_hw; 222 enum usb_chg_state chg_state; 223 enum power_supply_type chg_type; 224 u8 dcd_retries; 225 struct extcon_dev *edev; 226 const struct rockchip_usb2phy_cfg *phy_cfg; 227 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS]; 228 }; 229 230 static inline int property_enable(struct rockchip_usb2phy *rphy, 231 const struct usb2phy_reg *reg, bool en) 232 { 233 unsigned int val, mask, tmp; 234 235 tmp = en ? reg->enable : reg->disable; 236 mask = GENMASK(reg->bitend, reg->bitstart); 237 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 238 239 return regmap_write(rphy->grf, reg->offset, val); 240 } 241 242 static inline bool property_enabled(struct rockchip_usb2phy *rphy, 243 const struct usb2phy_reg *reg) 244 { 245 int ret; 246 unsigned int tmp, orig; 247 unsigned int mask = GENMASK(reg->bitend, reg->bitstart); 248 249 ret = regmap_read(rphy->grf, reg->offset, &orig); 250 if (ret) 251 return false; 252 253 tmp = (orig & mask) >> reg->bitstart; 254 return tmp == reg->enable; 255 } 256 257 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw) 258 { 259 struct rockchip_usb2phy *rphy = 260 container_of(hw, struct rockchip_usb2phy, clk480m_hw); 261 int ret; 262 263 /* turn on 480m clk output if it is off */ 264 if (!property_enabled(rphy, &rphy->phy_cfg->clkout_ctl)) { 265 ret = property_enable(rphy, &rphy->phy_cfg->clkout_ctl, true); 266 if (ret) 267 return ret; 268 269 /* waiting for the clk become stable */ 270 usleep_range(1200, 1300); 271 } 272 273 return 0; 274 } 275 276 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw) 277 { 278 struct rockchip_usb2phy *rphy = 279 container_of(hw, struct rockchip_usb2phy, clk480m_hw); 280 281 /* turn off 480m clk output */ 282 property_enable(rphy, &rphy->phy_cfg->clkout_ctl, false); 283 } 284 285 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw) 286 { 287 struct rockchip_usb2phy *rphy = 288 container_of(hw, struct rockchip_usb2phy, clk480m_hw); 289 290 return property_enabled(rphy, &rphy->phy_cfg->clkout_ctl); 291 } 292 293 static unsigned long 294 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw, 295 unsigned long parent_rate) 296 { 297 return 480000000; 298 } 299 300 static const struct clk_ops rockchip_usb2phy_clkout_ops = { 301 .prepare = rockchip_usb2phy_clk480m_prepare, 302 .unprepare = rockchip_usb2phy_clk480m_unprepare, 303 .is_prepared = rockchip_usb2phy_clk480m_prepared, 304 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate, 305 }; 306 307 static void rockchip_usb2phy_clk480m_unregister(void *data) 308 { 309 struct rockchip_usb2phy *rphy = data; 310 311 of_clk_del_provider(rphy->dev->of_node); 312 clk_unregister(rphy->clk480m); 313 } 314 315 static int 316 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy) 317 { 318 struct device_node *node = rphy->dev->of_node; 319 struct clk_init_data init; 320 const char *clk_name; 321 int ret; 322 323 init.flags = 0; 324 init.name = "clk_usbphy_480m"; 325 init.ops = &rockchip_usb2phy_clkout_ops; 326 327 /* optional override of the clockname */ 328 of_property_read_string(node, "clock-output-names", &init.name); 329 330 if (rphy->clk) { 331 clk_name = __clk_get_name(rphy->clk); 332 init.parent_names = &clk_name; 333 init.num_parents = 1; 334 } else { 335 init.parent_names = NULL; 336 init.num_parents = 0; 337 } 338 339 rphy->clk480m_hw.init = &init; 340 341 /* register the clock */ 342 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw); 343 if (IS_ERR(rphy->clk480m)) { 344 ret = PTR_ERR(rphy->clk480m); 345 goto err_ret; 346 } 347 348 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m); 349 if (ret < 0) 350 goto err_clk_provider; 351 352 ret = devm_add_action(rphy->dev, rockchip_usb2phy_clk480m_unregister, 353 rphy); 354 if (ret < 0) 355 goto err_unreg_action; 356 357 return 0; 358 359 err_unreg_action: 360 of_clk_del_provider(node); 361 err_clk_provider: 362 clk_unregister(rphy->clk480m); 363 err_ret: 364 return ret; 365 } 366 367 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy) 368 { 369 int ret; 370 struct device_node *node = rphy->dev->of_node; 371 struct extcon_dev *edev; 372 373 if (of_property_read_bool(node, "extcon")) { 374 edev = extcon_get_edev_by_phandle(rphy->dev, 0); 375 if (IS_ERR(edev)) { 376 if (PTR_ERR(edev) != -EPROBE_DEFER) 377 dev_err(rphy->dev, "Invalid or missing extcon\n"); 378 return PTR_ERR(edev); 379 } 380 } else { 381 /* Initialize extcon device */ 382 edev = devm_extcon_dev_allocate(rphy->dev, 383 rockchip_usb2phy_extcon_cable); 384 385 if (IS_ERR(edev)) 386 return -ENOMEM; 387 388 ret = devm_extcon_dev_register(rphy->dev, edev); 389 if (ret) { 390 dev_err(rphy->dev, "failed to register extcon device\n"); 391 return ret; 392 } 393 } 394 395 rphy->edev = edev; 396 397 return 0; 398 } 399 400 static int rockchip_usb2phy_init(struct phy *phy) 401 { 402 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 403 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); 404 int ret = 0; 405 406 mutex_lock(&rport->mutex); 407 408 if (rport->port_id == USB2PHY_PORT_OTG) { 409 if (rport->mode != USB_DR_MODE_HOST && 410 rport->mode != USB_DR_MODE_UNKNOWN) { 411 /* clear bvalid status and enable bvalid detect irq */ 412 ret = property_enable(rphy, 413 &rport->port_cfg->bvalid_det_clr, 414 true); 415 if (ret) 416 goto out; 417 418 ret = property_enable(rphy, 419 &rport->port_cfg->bvalid_det_en, 420 true); 421 if (ret) 422 goto out; 423 424 schedule_delayed_work(&rport->otg_sm_work, 425 OTG_SCHEDULE_DELAY * 3); 426 } else { 427 /* If OTG works in host only mode, do nothing. */ 428 dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode); 429 } 430 } else if (rport->port_id == USB2PHY_PORT_HOST) { 431 /* clear linestate and enable linestate detect irq */ 432 ret = property_enable(rphy, &rport->port_cfg->ls_det_clr, true); 433 if (ret) 434 goto out; 435 436 ret = property_enable(rphy, &rport->port_cfg->ls_det_en, true); 437 if (ret) 438 goto out; 439 440 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY); 441 } 442 443 out: 444 mutex_unlock(&rport->mutex); 445 return ret; 446 } 447 448 static int rockchip_usb2phy_power_on(struct phy *phy) 449 { 450 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 451 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); 452 int ret; 453 454 dev_dbg(&rport->phy->dev, "port power on\n"); 455 456 if (!rport->suspended) 457 return 0; 458 459 ret = clk_prepare_enable(rphy->clk480m); 460 if (ret) 461 return ret; 462 463 ret = property_enable(rphy, &rport->port_cfg->phy_sus, false); 464 if (ret) 465 return ret; 466 467 /* waiting for the utmi_clk to become stable */ 468 usleep_range(1500, 2000); 469 470 rport->suspended = false; 471 return 0; 472 } 473 474 static int rockchip_usb2phy_power_off(struct phy *phy) 475 { 476 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 477 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); 478 int ret; 479 480 dev_dbg(&rport->phy->dev, "port power off\n"); 481 482 if (rport->suspended) 483 return 0; 484 485 ret = property_enable(rphy, &rport->port_cfg->phy_sus, true); 486 if (ret) 487 return ret; 488 489 rport->suspended = true; 490 clk_disable_unprepare(rphy->clk480m); 491 492 return 0; 493 } 494 495 static int rockchip_usb2phy_exit(struct phy *phy) 496 { 497 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 498 499 if (rport->port_id == USB2PHY_PORT_OTG && 500 rport->mode != USB_DR_MODE_HOST && 501 rport->mode != USB_DR_MODE_UNKNOWN) { 502 cancel_delayed_work_sync(&rport->otg_sm_work); 503 cancel_delayed_work_sync(&rport->chg_work); 504 } else if (rport->port_id == USB2PHY_PORT_HOST) 505 cancel_delayed_work_sync(&rport->sm_work); 506 507 return 0; 508 } 509 510 static const struct phy_ops rockchip_usb2phy_ops = { 511 .init = rockchip_usb2phy_init, 512 .exit = rockchip_usb2phy_exit, 513 .power_on = rockchip_usb2phy_power_on, 514 .power_off = rockchip_usb2phy_power_off, 515 .owner = THIS_MODULE, 516 }; 517 518 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work) 519 { 520 struct rockchip_usb2phy_port *rport = 521 container_of(work, struct rockchip_usb2phy_port, 522 otg_sm_work.work); 523 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 524 static unsigned int cable; 525 unsigned long delay; 526 bool vbus_attach, sch_work, notify_charger; 527 528 if (rport->utmi_avalid) 529 vbus_attach = 530 property_enabled(rphy, &rport->port_cfg->utmi_avalid); 531 else 532 vbus_attach = 533 property_enabled(rphy, &rport->port_cfg->utmi_bvalid); 534 535 sch_work = false; 536 notify_charger = false; 537 delay = OTG_SCHEDULE_DELAY; 538 dev_dbg(&rport->phy->dev, "%s otg sm work\n", 539 usb_otg_state_string(rport->state)); 540 541 switch (rport->state) { 542 case OTG_STATE_UNDEFINED: 543 rport->state = OTG_STATE_B_IDLE; 544 if (!vbus_attach) 545 rockchip_usb2phy_power_off(rport->phy); 546 /* fall through */ 547 case OTG_STATE_B_IDLE: 548 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) > 0) { 549 dev_dbg(&rport->phy->dev, "usb otg host connect\n"); 550 rport->state = OTG_STATE_A_HOST; 551 rockchip_usb2phy_power_on(rport->phy); 552 return; 553 } else if (vbus_attach) { 554 dev_dbg(&rport->phy->dev, "vbus_attach\n"); 555 switch (rphy->chg_state) { 556 case USB_CHG_STATE_UNDEFINED: 557 schedule_delayed_work(&rport->chg_work, 0); 558 return; 559 case USB_CHG_STATE_DETECTED: 560 switch (rphy->chg_type) { 561 case POWER_SUPPLY_TYPE_USB: 562 dev_dbg(&rport->phy->dev, "sdp cable is connected\n"); 563 rockchip_usb2phy_power_on(rport->phy); 564 rport->state = OTG_STATE_B_PERIPHERAL; 565 notify_charger = true; 566 sch_work = true; 567 cable = EXTCON_CHG_USB_SDP; 568 break; 569 case POWER_SUPPLY_TYPE_USB_DCP: 570 dev_dbg(&rport->phy->dev, "dcp cable is connected\n"); 571 rockchip_usb2phy_power_off(rport->phy); 572 notify_charger = true; 573 sch_work = true; 574 cable = EXTCON_CHG_USB_DCP; 575 break; 576 case POWER_SUPPLY_TYPE_USB_CDP: 577 dev_dbg(&rport->phy->dev, "cdp cable is connected\n"); 578 rockchip_usb2phy_power_on(rport->phy); 579 rport->state = OTG_STATE_B_PERIPHERAL; 580 notify_charger = true; 581 sch_work = true; 582 cable = EXTCON_CHG_USB_CDP; 583 break; 584 default: 585 break; 586 } 587 break; 588 default: 589 break; 590 } 591 } else { 592 notify_charger = true; 593 rphy->chg_state = USB_CHG_STATE_UNDEFINED; 594 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; 595 } 596 597 if (rport->vbus_attached != vbus_attach) { 598 rport->vbus_attached = vbus_attach; 599 600 if (notify_charger && rphy->edev) { 601 extcon_set_cable_state_(rphy->edev, 602 cable, vbus_attach); 603 if (cable == EXTCON_CHG_USB_SDP) 604 extcon_set_state_sync(rphy->edev, 605 EXTCON_USB, 606 vbus_attach); 607 } 608 } 609 break; 610 case OTG_STATE_B_PERIPHERAL: 611 if (!vbus_attach) { 612 dev_dbg(&rport->phy->dev, "usb disconnect\n"); 613 rphy->chg_state = USB_CHG_STATE_UNDEFINED; 614 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; 615 rport->state = OTG_STATE_B_IDLE; 616 delay = 0; 617 rockchip_usb2phy_power_off(rport->phy); 618 } 619 sch_work = true; 620 break; 621 case OTG_STATE_A_HOST: 622 if (extcon_get_cable_state_(rphy->edev, EXTCON_USB_HOST) == 0) { 623 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n"); 624 rport->state = OTG_STATE_B_IDLE; 625 rockchip_usb2phy_power_off(rport->phy); 626 } 627 break; 628 default: 629 break; 630 } 631 632 if (sch_work) 633 schedule_delayed_work(&rport->otg_sm_work, delay); 634 } 635 636 static const char *chg_to_string(enum power_supply_type chg_type) 637 { 638 switch (chg_type) { 639 case POWER_SUPPLY_TYPE_USB: 640 return "USB_SDP_CHARGER"; 641 case POWER_SUPPLY_TYPE_USB_DCP: 642 return "USB_DCP_CHARGER"; 643 case POWER_SUPPLY_TYPE_USB_CDP: 644 return "USB_CDP_CHARGER"; 645 default: 646 return "INVALID_CHARGER"; 647 } 648 } 649 650 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 651 bool en) 652 { 653 property_enable(rphy, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 654 property_enable(rphy, &rphy->phy_cfg->chg_det.idp_src_en, en); 655 } 656 657 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 658 bool en) 659 { 660 property_enable(rphy, &rphy->phy_cfg->chg_det.vdp_src_en, en); 661 property_enable(rphy, &rphy->phy_cfg->chg_det.idm_sink_en, en); 662 } 663 664 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 665 bool en) 666 { 667 property_enable(rphy, &rphy->phy_cfg->chg_det.vdm_src_en, en); 668 property_enable(rphy, &rphy->phy_cfg->chg_det.idp_sink_en, en); 669 } 670 671 #define CHG_DCD_POLL_TIME (100 * HZ / 1000) 672 #define CHG_DCD_MAX_RETRIES 6 673 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000) 674 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000) 675 static void rockchip_chg_detect_work(struct work_struct *work) 676 { 677 struct rockchip_usb2phy_port *rport = 678 container_of(work, struct rockchip_usb2phy_port, chg_work.work); 679 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 680 bool is_dcd, tmout, vout; 681 unsigned long delay; 682 683 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n", 684 rphy->chg_state); 685 switch (rphy->chg_state) { 686 case USB_CHG_STATE_UNDEFINED: 687 if (!rport->suspended) 688 rockchip_usb2phy_power_off(rport->phy); 689 /* put the controller in non-driving mode */ 690 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, false); 691 /* Start DCD processing stage 1 */ 692 rockchip_chg_enable_dcd(rphy, true); 693 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD; 694 rphy->dcd_retries = 0; 695 delay = CHG_DCD_POLL_TIME; 696 break; 697 case USB_CHG_STATE_WAIT_FOR_DCD: 698 /* get data contact detection status */ 699 is_dcd = property_enabled(rphy, &rphy->phy_cfg->chg_det.dp_det); 700 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES; 701 /* stage 2 */ 702 if (is_dcd || tmout) { 703 /* stage 4 */ 704 /* Turn off DCD circuitry */ 705 rockchip_chg_enable_dcd(rphy, false); 706 /* Voltage Source on DP, Probe on DM */ 707 rockchip_chg_enable_primary_det(rphy, true); 708 delay = CHG_PRIMARY_DET_TIME; 709 rphy->chg_state = USB_CHG_STATE_DCD_DONE; 710 } else { 711 /* stage 3 */ 712 delay = CHG_DCD_POLL_TIME; 713 } 714 break; 715 case USB_CHG_STATE_DCD_DONE: 716 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.cp_det); 717 rockchip_chg_enable_primary_det(rphy, false); 718 if (vout) { 719 /* Voltage Source on DM, Probe on DP */ 720 rockchip_chg_enable_secondary_det(rphy, true); 721 delay = CHG_SECONDARY_DET_TIME; 722 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE; 723 } else { 724 if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) { 725 /* floating charger found */ 726 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP; 727 rphy->chg_state = USB_CHG_STATE_DETECTED; 728 delay = 0; 729 } else { 730 rphy->chg_type = POWER_SUPPLY_TYPE_USB; 731 rphy->chg_state = USB_CHG_STATE_DETECTED; 732 delay = 0; 733 } 734 } 735 break; 736 case USB_CHG_STATE_PRIMARY_DONE: 737 vout = property_enabled(rphy, &rphy->phy_cfg->chg_det.dcp_det); 738 /* Turn off voltage source */ 739 rockchip_chg_enable_secondary_det(rphy, false); 740 if (vout) 741 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP; 742 else 743 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP; 744 /* fall through */ 745 case USB_CHG_STATE_SECONDARY_DONE: 746 rphy->chg_state = USB_CHG_STATE_DETECTED; 747 delay = 0; 748 /* fall through */ 749 case USB_CHG_STATE_DETECTED: 750 /* put the controller in normal mode */ 751 property_enable(rphy, &rphy->phy_cfg->chg_det.opmode, true); 752 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); 753 dev_info(&rport->phy->dev, "charger = %s\n", 754 chg_to_string(rphy->chg_type)); 755 return; 756 default: 757 return; 758 } 759 760 schedule_delayed_work(&rport->chg_work, delay); 761 } 762 763 /* 764 * The function manage host-phy port state and suspend/resume phy port 765 * to save power. 766 * 767 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether 768 * devices is disconnect or not. Besides, we do not need care it is FS/LS 769 * disconnected or HS disconnected, actually, we just only need get the 770 * device is disconnected at last through rearm the delayed work, 771 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case. 772 * 773 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke 774 * some clk related APIs, so do not invoke it from interrupt context directly. 775 */ 776 static void rockchip_usb2phy_sm_work(struct work_struct *work) 777 { 778 struct rockchip_usb2phy_port *rport = 779 container_of(work, struct rockchip_usb2phy_port, sm_work.work); 780 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 781 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend - 782 rport->port_cfg->utmi_hstdet.bitstart + 1; 783 unsigned int ul, uhd, state; 784 unsigned int ul_mask, uhd_mask; 785 int ret; 786 787 mutex_lock(&rport->mutex); 788 789 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul); 790 if (ret < 0) 791 goto next_schedule; 792 793 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, 794 &uhd); 795 if (ret < 0) 796 goto next_schedule; 797 798 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend, 799 rport->port_cfg->utmi_hstdet.bitstart); 800 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend, 801 rport->port_cfg->utmi_ls.bitstart); 802 803 /* stitch on utmi_ls and utmi_hstdet as phy state */ 804 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) | 805 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh); 806 807 switch (state) { 808 case PHY_STATE_HS_ONLINE: 809 dev_dbg(&rport->phy->dev, "HS online\n"); 810 break; 811 case PHY_STATE_FS_LS_ONLINE: 812 /* 813 * For FS/LS device, the online state share with connect state 814 * from utmi_ls and utmi_hstdet register, so we distinguish 815 * them via suspended flag. 816 * 817 * Plus, there are two cases, one is D- Line pull-up, and D+ 818 * line pull-down, the state is 4; another is D+ line pull-up, 819 * and D- line pull-down, the state is 2. 820 */ 821 if (!rport->suspended) { 822 /* D- line pull-up, D+ line pull-down */ 823 dev_dbg(&rport->phy->dev, "FS/LS online\n"); 824 break; 825 } 826 /* fall through */ 827 case PHY_STATE_CONNECT: 828 if (rport->suspended) { 829 dev_dbg(&rport->phy->dev, "Connected\n"); 830 rockchip_usb2phy_power_on(rport->phy); 831 rport->suspended = false; 832 } else { 833 /* D+ line pull-up, D- line pull-down */ 834 dev_dbg(&rport->phy->dev, "FS/LS online\n"); 835 } 836 break; 837 case PHY_STATE_DISCONNECT: 838 if (!rport->suspended) { 839 dev_dbg(&rport->phy->dev, "Disconnected\n"); 840 rockchip_usb2phy_power_off(rport->phy); 841 rport->suspended = true; 842 } 843 844 /* 845 * activate the linestate detection to get the next device 846 * plug-in irq. 847 */ 848 property_enable(rphy, &rport->port_cfg->ls_det_clr, true); 849 property_enable(rphy, &rport->port_cfg->ls_det_en, true); 850 851 /* 852 * we don't need to rearm the delayed work when the phy port 853 * is suspended. 854 */ 855 mutex_unlock(&rport->mutex); 856 return; 857 default: 858 dev_dbg(&rport->phy->dev, "unknown phy state\n"); 859 break; 860 } 861 862 next_schedule: 863 mutex_unlock(&rport->mutex); 864 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY); 865 } 866 867 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data) 868 { 869 struct rockchip_usb2phy_port *rport = data; 870 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 871 872 if (!property_enabled(rphy, &rport->port_cfg->ls_det_st)) 873 return IRQ_NONE; 874 875 mutex_lock(&rport->mutex); 876 877 /* disable linestate detect irq and clear its status */ 878 property_enable(rphy, &rport->port_cfg->ls_det_en, false); 879 property_enable(rphy, &rport->port_cfg->ls_det_clr, true); 880 881 mutex_unlock(&rport->mutex); 882 883 /* 884 * In this case for host phy port, a new device is plugged in, 885 * meanwhile, if the phy port is suspended, we need rearm the work to 886 * resume it and mange its states; otherwise, we do nothing about that. 887 */ 888 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST) 889 rockchip_usb2phy_sm_work(&rport->sm_work.work); 890 891 return IRQ_HANDLED; 892 } 893 894 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data) 895 { 896 struct rockchip_usb2phy_port *rport = data; 897 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 898 899 if (!property_enabled(rphy, &rport->port_cfg->bvalid_det_st)) 900 return IRQ_NONE; 901 902 mutex_lock(&rport->mutex); 903 904 /* clear bvalid detect irq pending status */ 905 property_enable(rphy, &rport->port_cfg->bvalid_det_clr, true); 906 907 mutex_unlock(&rport->mutex); 908 909 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); 910 911 return IRQ_HANDLED; 912 } 913 914 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy, 915 struct rockchip_usb2phy_port *rport, 916 struct device_node *child_np) 917 { 918 int ret; 919 920 rport->port_id = USB2PHY_PORT_HOST; 921 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 922 rport->suspended = true; 923 924 mutex_init(&rport->mutex); 925 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work); 926 927 rport->ls_irq = of_irq_get_byname(child_np, "linestate"); 928 if (rport->ls_irq < 0) { 929 dev_err(rphy->dev, "no linestate irq provided\n"); 930 return rport->ls_irq; 931 } 932 933 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL, 934 rockchip_usb2phy_linestate_irq, 935 IRQF_ONESHOT, 936 "rockchip_usb2phy", rport); 937 if (ret) { 938 dev_err(rphy->dev, "failed to request linestate irq handle\n"); 939 return ret; 940 } 941 942 return 0; 943 } 944 945 static int rockchip_otg_event(struct notifier_block *nb, 946 unsigned long event, void *ptr) 947 { 948 struct rockchip_usb2phy_port *rport = 949 container_of(nb, struct rockchip_usb2phy_port, event_nb); 950 951 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY); 952 953 return NOTIFY_DONE; 954 } 955 956 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, 957 struct rockchip_usb2phy_port *rport, 958 struct device_node *child_np) 959 { 960 int ret; 961 962 rport->port_id = USB2PHY_PORT_OTG; 963 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 964 rport->state = OTG_STATE_UNDEFINED; 965 966 /* 967 * set suspended flag to true, but actually don't 968 * put phy in suspend mode, it aims to enable usb 969 * phy and clock in power_on() called by usb controller 970 * driver during probe. 971 */ 972 rport->suspended = true; 973 rport->vbus_attached = false; 974 975 mutex_init(&rport->mutex); 976 977 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1); 978 if (rport->mode == USB_DR_MODE_HOST || 979 rport->mode == USB_DR_MODE_UNKNOWN) { 980 ret = 0; 981 goto out; 982 } 983 984 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work); 985 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work); 986 987 rport->utmi_avalid = 988 of_property_read_bool(child_np, "rockchip,utmi-avalid"); 989 990 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid"); 991 if (rport->bvalid_irq < 0) { 992 dev_err(rphy->dev, "no vbus valid irq provided\n"); 993 ret = rport->bvalid_irq; 994 goto out; 995 } 996 997 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, NULL, 998 rockchip_usb2phy_bvalid_irq, 999 IRQF_ONESHOT, 1000 "rockchip_usb2phy_bvalid", rport); 1001 if (ret) { 1002 dev_err(rphy->dev, "failed to request otg-bvalid irq handle\n"); 1003 goto out; 1004 } 1005 1006 if (!IS_ERR(rphy->edev)) { 1007 rport->event_nb.notifier_call = rockchip_otg_event; 1008 1009 ret = extcon_register_notifier(rphy->edev, EXTCON_USB_HOST, 1010 &rport->event_nb); 1011 if (ret) 1012 dev_err(rphy->dev, "register USB HOST notifier failed\n"); 1013 } 1014 1015 out: 1016 return ret; 1017 } 1018 1019 static int rockchip_usb2phy_probe(struct platform_device *pdev) 1020 { 1021 struct device *dev = &pdev->dev; 1022 struct device_node *np = dev->of_node; 1023 struct device_node *child_np; 1024 struct phy_provider *provider; 1025 struct rockchip_usb2phy *rphy; 1026 const struct rockchip_usb2phy_cfg *phy_cfgs; 1027 const struct of_device_id *match; 1028 unsigned int reg; 1029 int index, ret; 1030 1031 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL); 1032 if (!rphy) 1033 return -ENOMEM; 1034 1035 match = of_match_device(dev->driver->of_match_table, dev); 1036 if (!match || !match->data) { 1037 dev_err(dev, "phy configs are not assigned!\n"); 1038 return -EINVAL; 1039 } 1040 1041 if (!dev->parent || !dev->parent->of_node) 1042 return -EINVAL; 1043 1044 rphy->grf = syscon_node_to_regmap(dev->parent->of_node); 1045 if (IS_ERR(rphy->grf)) 1046 return PTR_ERR(rphy->grf); 1047 1048 if (of_property_read_u32(np, "reg", ®)) { 1049 dev_err(dev, "the reg property is not assigned in %s node\n", 1050 np->name); 1051 return -EINVAL; 1052 } 1053 1054 rphy->dev = dev; 1055 phy_cfgs = match->data; 1056 rphy->chg_state = USB_CHG_STATE_UNDEFINED; 1057 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; 1058 platform_set_drvdata(pdev, rphy); 1059 1060 ret = rockchip_usb2phy_extcon_register(rphy); 1061 if (ret) 1062 return ret; 1063 1064 /* find out a proper config which can be matched with dt. */ 1065 index = 0; 1066 while (phy_cfgs[index].reg) { 1067 if (phy_cfgs[index].reg == reg) { 1068 rphy->phy_cfg = &phy_cfgs[index]; 1069 break; 1070 } 1071 1072 ++index; 1073 } 1074 1075 if (!rphy->phy_cfg) { 1076 dev_err(dev, "no phy-config can be matched with %s node\n", 1077 np->name); 1078 return -EINVAL; 1079 } 1080 1081 rphy->clk = of_clk_get_by_name(np, "phyclk"); 1082 if (!IS_ERR(rphy->clk)) { 1083 clk_prepare_enable(rphy->clk); 1084 } else { 1085 dev_info(&pdev->dev, "no phyclk specified\n"); 1086 rphy->clk = NULL; 1087 } 1088 1089 ret = rockchip_usb2phy_clk480m_register(rphy); 1090 if (ret) { 1091 dev_err(dev, "failed to register 480m output clock\n"); 1092 goto disable_clks; 1093 } 1094 1095 index = 0; 1096 for_each_available_child_of_node(np, child_np) { 1097 struct rockchip_usb2phy_port *rport = &rphy->ports[index]; 1098 struct phy *phy; 1099 1100 /* This driver aims to support both otg-port and host-port */ 1101 if (of_node_cmp(child_np->name, "host-port") && 1102 of_node_cmp(child_np->name, "otg-port")) 1103 goto next_child; 1104 1105 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops); 1106 if (IS_ERR(phy)) { 1107 dev_err(dev, "failed to create phy\n"); 1108 ret = PTR_ERR(phy); 1109 goto put_child; 1110 } 1111 1112 rport->phy = phy; 1113 phy_set_drvdata(rport->phy, rport); 1114 1115 /* initialize otg/host port separately */ 1116 if (!of_node_cmp(child_np->name, "host-port")) { 1117 ret = rockchip_usb2phy_host_port_init(rphy, rport, 1118 child_np); 1119 if (ret) 1120 goto put_child; 1121 } else { 1122 ret = rockchip_usb2phy_otg_port_init(rphy, rport, 1123 child_np); 1124 if (ret) 1125 goto put_child; 1126 } 1127 1128 next_child: 1129 /* to prevent out of boundary */ 1130 if (++index >= rphy->phy_cfg->num_ports) 1131 break; 1132 } 1133 1134 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1135 return PTR_ERR_OR_ZERO(provider); 1136 1137 put_child: 1138 of_node_put(child_np); 1139 disable_clks: 1140 if (rphy->clk) { 1141 clk_disable_unprepare(rphy->clk); 1142 clk_put(rphy->clk); 1143 } 1144 return ret; 1145 } 1146 1147 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = { 1148 { 1149 .reg = 0x760, 1150 .num_ports = 2, 1151 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 1152 .port_cfgs = { 1153 [USB2PHY_PORT_OTG] = { 1154 .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 }, 1155 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1156 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1157 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1158 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1159 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1160 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1161 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 1162 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 1163 }, 1164 [USB2PHY_PORT_HOST] = { 1165 .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 }, 1166 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1167 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1168 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1169 } 1170 }, 1171 .chg_det = { 1172 .opmode = { 0x0760, 3, 0, 5, 1 }, 1173 .cp_det = { 0x0884, 4, 4, 0, 1 }, 1174 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 1175 .dp_det = { 0x0884, 5, 5, 0, 1 }, 1176 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 1177 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 1178 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 1179 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 1180 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 1181 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 1182 }, 1183 }, 1184 { 1185 .reg = 0x800, 1186 .num_ports = 2, 1187 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 1188 .port_cfgs = { 1189 [USB2PHY_PORT_OTG] = { 1190 .phy_sus = { 0x800, 15, 0, 0, 0x1d1 }, 1191 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 1192 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 1193 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 1194 }, 1195 [USB2PHY_PORT_HOST] = { 1196 .phy_sus = { 0x804, 15, 0, 0, 0x1d1 }, 1197 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 1198 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 1199 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 1200 } 1201 }, 1202 }, 1203 { /* sentinel */ } 1204 }; 1205 1206 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 1207 { 1208 .reg = 0x100, 1209 .num_ports = 2, 1210 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1211 .port_cfgs = { 1212 [USB2PHY_PORT_OTG] = { 1213 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 }, 1214 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1215 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1216 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1217 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1218 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1219 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1220 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1221 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1222 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1223 }, 1224 [USB2PHY_PORT_HOST] = { 1225 .phy_sus = { 0x104, 15, 0, 0, 0x1d1 }, 1226 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1227 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1228 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1229 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1230 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1231 } 1232 }, 1233 .chg_det = { 1234 .opmode = { 0x0100, 3, 0, 5, 1 }, 1235 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1236 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1237 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1238 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1239 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1240 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1241 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1242 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1243 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1244 }, 1245 }, 1246 { /* sentinel */ } 1247 }; 1248 1249 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = { 1250 { 1251 .reg = 0x700, 1252 .num_ports = 2, 1253 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 1254 .port_cfgs = { 1255 [USB2PHY_PORT_HOST] = { 1256 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 }, 1257 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1258 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1259 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1260 .utmi_ls = { 0x049c, 14, 13, 0, 1 }, 1261 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 } 1262 } 1263 }, 1264 }, 1265 { /* sentinel */ } 1266 }; 1267 1268 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 1269 { 1270 .reg = 0xe450, 1271 .num_ports = 2, 1272 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 1273 .port_cfgs = { 1274 [USB2PHY_PORT_OTG] = { 1275 .phy_sus = { 0xe454, 1, 0, 2, 1 }, 1276 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1277 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1278 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1279 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1280 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1281 }, 1282 [USB2PHY_PORT_HOST] = { 1283 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 1284 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 1285 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 1286 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 1287 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 1288 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 1289 } 1290 }, 1291 .chg_det = { 1292 .opmode = { 0xe454, 3, 0, 5, 1 }, 1293 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 1294 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 1295 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 1296 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 1297 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 1298 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 1299 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 1300 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 1301 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 1302 }, 1303 }, 1304 { 1305 .reg = 0xe460, 1306 .num_ports = 2, 1307 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 1308 .port_cfgs = { 1309 [USB2PHY_PORT_OTG] = { 1310 .phy_sus = { 0xe464, 1, 0, 2, 1 }, 1311 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1312 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1313 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1314 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1315 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1316 }, 1317 [USB2PHY_PORT_HOST] = { 1318 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 1319 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 1320 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 1321 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 1322 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 1323 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 1324 } 1325 }, 1326 }, 1327 { /* sentinel */ } 1328 }; 1329 1330 static const struct of_device_id rockchip_usb2phy_dt_match[] = { 1331 { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs }, 1332 { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, 1333 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, 1334 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, 1335 {} 1336 }; 1337 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match); 1338 1339 static struct platform_driver rockchip_usb2phy_driver = { 1340 .probe = rockchip_usb2phy_probe, 1341 .driver = { 1342 .name = "rockchip-usb2phy", 1343 .of_match_table = rockchip_usb2phy_dt_match, 1344 }, 1345 }; 1346 module_platform_driver(rockchip_usb2phy_driver); 1347 1348 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>"); 1349 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver"); 1350 MODULE_LICENSE("GPL v2"); 1351