1 // SPDX-License-Identifier: GPL-2.0-or-later
2 /*
3  * Rockchip USB2.0 PHY with Innosilicon IP block driver
4  *
5  * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd
6  */
7 
8 #include <linux/clk.h>
9 #include <linux/clk-provider.h>
10 #include <linux/delay.h>
11 #include <linux/extcon-provider.h>
12 #include <linux/interrupt.h>
13 #include <linux/io.h>
14 #include <linux/gpio/consumer.h>
15 #include <linux/jiffies.h>
16 #include <linux/kernel.h>
17 #include <linux/module.h>
18 #include <linux/mutex.h>
19 #include <linux/of.h>
20 #include <linux/of_address.h>
21 #include <linux/of_irq.h>
22 #include <linux/of_platform.h>
23 #include <linux/phy/phy.h>
24 #include <linux/platform_device.h>
25 #include <linux/power_supply.h>
26 #include <linux/regmap.h>
27 #include <linux/mfd/syscon.h>
28 #include <linux/usb/of.h>
29 #include <linux/usb/otg.h>
30 
31 #define BIT_WRITEABLE_SHIFT	16
32 #define SCHEDULE_DELAY		(60 * HZ)
33 #define OTG_SCHEDULE_DELAY	(2 * HZ)
34 
35 enum rockchip_usb2phy_port_id {
36 	USB2PHY_PORT_OTG,
37 	USB2PHY_PORT_HOST,
38 	USB2PHY_NUM_PORTS,
39 };
40 
41 enum rockchip_usb2phy_host_state {
42 	PHY_STATE_HS_ONLINE	= 0,
43 	PHY_STATE_DISCONNECT	= 1,
44 	PHY_STATE_CONNECT	= 2,
45 	PHY_STATE_FS_LS_ONLINE	= 4,
46 };
47 
48 /**
49  * enum usb_chg_state - Different states involved in USB charger detection.
50  * @USB_CHG_STATE_UNDEFINED:	USB charger is not connected or detection
51  *				process is not yet started.
52  * @USB_CHG_STATE_WAIT_FOR_DCD:	Waiting for Data pins contact.
53  * @USB_CHG_STATE_DCD_DONE:	Data pin contact is detected.
54  * @USB_CHG_STATE_PRIMARY_DONE:	Primary detection is completed (Detects
55  *				between SDP and DCP/CDP).
56  * @USB_CHG_STATE_SECONDARY_DONE: Secondary detection is completed (Detects
57  *				  between DCP and CDP).
58  * @USB_CHG_STATE_DETECTED:	USB charger type is determined.
59  */
60 enum usb_chg_state {
61 	USB_CHG_STATE_UNDEFINED = 0,
62 	USB_CHG_STATE_WAIT_FOR_DCD,
63 	USB_CHG_STATE_DCD_DONE,
64 	USB_CHG_STATE_PRIMARY_DONE,
65 	USB_CHG_STATE_SECONDARY_DONE,
66 	USB_CHG_STATE_DETECTED,
67 };
68 
69 static const unsigned int rockchip_usb2phy_extcon_cable[] = {
70 	EXTCON_USB,
71 	EXTCON_USB_HOST,
72 	EXTCON_CHG_USB_SDP,
73 	EXTCON_CHG_USB_CDP,
74 	EXTCON_CHG_USB_DCP,
75 	EXTCON_CHG_USB_SLOW,
76 	EXTCON_NONE,
77 };
78 
79 struct usb2phy_reg {
80 	unsigned int	offset;
81 	unsigned int	bitend;
82 	unsigned int	bitstart;
83 	unsigned int	disable;
84 	unsigned int	enable;
85 };
86 
87 /**
88  * struct rockchip_chg_det_reg - usb charger detect registers
89  * @cp_det: charging port detected successfully.
90  * @dcp_det: dedicated charging port detected successfully.
91  * @dp_det: assert data pin connect successfully.
92  * @idm_sink_en: open dm sink curren.
93  * @idp_sink_en: open dp sink current.
94  * @idp_src_en: open dm source current.
95  * @rdm_pdwn_en: open dm pull down resistor.
96  * @vdm_src_en: open dm voltage source.
97  * @vdp_src_en: open dp voltage source.
98  * @opmode: utmi operational mode.
99  */
100 struct rockchip_chg_det_reg {
101 	struct usb2phy_reg	cp_det;
102 	struct usb2phy_reg	dcp_det;
103 	struct usb2phy_reg	dp_det;
104 	struct usb2phy_reg	idm_sink_en;
105 	struct usb2phy_reg	idp_sink_en;
106 	struct usb2phy_reg	idp_src_en;
107 	struct usb2phy_reg	rdm_pdwn_en;
108 	struct usb2phy_reg	vdm_src_en;
109 	struct usb2phy_reg	vdp_src_en;
110 	struct usb2phy_reg	opmode;
111 };
112 
113 /**
114  * struct rockchip_usb2phy_port_cfg - usb-phy port configuration.
115  * @phy_sus: phy suspend register.
116  * @bvalid_det_en: vbus valid rise detection enable register.
117  * @bvalid_det_st: vbus valid rise detection status register.
118  * @bvalid_det_clr: vbus valid rise detection clear register.
119  * @id_det_en: id detection enable register.
120  * @id_det_st: id detection state register.
121  * @id_det_clr: id detection clear register.
122  * @ls_det_en: linestate detection enable register.
123  * @ls_det_st: linestate detection state register.
124  * @ls_det_clr: linestate detection clear register.
125  * @utmi_avalid: utmi vbus avalid status register.
126  * @utmi_bvalid: utmi vbus bvalid status register.
127  * @utmi_id: utmi id state register.
128  * @utmi_ls: utmi linestate state register.
129  * @utmi_hstdet: utmi host disconnect register.
130  */
131 struct rockchip_usb2phy_port_cfg {
132 	struct usb2phy_reg	phy_sus;
133 	struct usb2phy_reg	bvalid_det_en;
134 	struct usb2phy_reg	bvalid_det_st;
135 	struct usb2phy_reg	bvalid_det_clr;
136 	struct usb2phy_reg	id_det_en;
137 	struct usb2phy_reg	id_det_st;
138 	struct usb2phy_reg	id_det_clr;
139 	struct usb2phy_reg	ls_det_en;
140 	struct usb2phy_reg	ls_det_st;
141 	struct usb2phy_reg	ls_det_clr;
142 	struct usb2phy_reg	utmi_avalid;
143 	struct usb2phy_reg	utmi_bvalid;
144 	struct usb2phy_reg	utmi_id;
145 	struct usb2phy_reg	utmi_ls;
146 	struct usb2phy_reg	utmi_hstdet;
147 };
148 
149 /**
150  * struct rockchip_usb2phy_cfg - usb-phy configuration.
151  * @reg: the address offset of grf for usb-phy config.
152  * @num_ports: specify how many ports that the phy has.
153  * @clkout_ctl: keep on/turn off output clk of phy.
154  * @port_cfgs: usb-phy port configurations.
155  * @chg_det: charger detection registers.
156  */
157 struct rockchip_usb2phy_cfg {
158 	unsigned int	reg;
159 	unsigned int	num_ports;
160 	struct usb2phy_reg	clkout_ctl;
161 	const struct rockchip_usb2phy_port_cfg	port_cfgs[USB2PHY_NUM_PORTS];
162 	const struct rockchip_chg_det_reg	chg_det;
163 };
164 
165 /**
166  * struct rockchip_usb2phy_port - usb-phy port data.
167  * @phy: generic phy.
168  * @port_id: flag for otg port or host port.
169  * @suspended: phy suspended flag.
170  * @vbus_attached: otg device vbus status.
171  * @bvalid_irq: IRQ number assigned for vbus valid rise detection.
172  * @id_irq: IRQ number assigned for ID pin detection.
173  * @ls_irq: IRQ number assigned for linestate detection.
174  * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate
175  *		 irqs to one irq in otg-port.
176  * @mutex: for register updating in sm_work.
177  * @chg_work: charge detect work.
178  * @otg_sm_work: OTG state machine work.
179  * @sm_work: HOST state machine work.
180  * @port_cfg: port register configuration, assigned by driver data.
181  * @event_nb: hold event notification callback.
182  * @state: define OTG enumeration states before device reset.
183  * @mode: the dr_mode of the controller.
184  */
185 struct rockchip_usb2phy_port {
186 	struct phy	*phy;
187 	unsigned int	port_id;
188 	bool		suspended;
189 	bool		vbus_attached;
190 	int		bvalid_irq;
191 	int		id_irq;
192 	int		ls_irq;
193 	int		otg_mux_irq;
194 	struct mutex	mutex;
195 	struct		delayed_work chg_work;
196 	struct		delayed_work otg_sm_work;
197 	struct		delayed_work sm_work;
198 	const struct	rockchip_usb2phy_port_cfg *port_cfg;
199 	struct notifier_block	event_nb;
200 	enum usb_otg_state	state;
201 	enum usb_dr_mode	mode;
202 };
203 
204 /**
205  * struct rockchip_usb2phy - usb2.0 phy driver data.
206  * @dev: pointer to device.
207  * @grf: General Register Files regmap.
208  * @usbgrf: USB General Register Files regmap.
209  * @clk: clock struct of phy input clk.
210  * @clk480m: clock struct of phy output clk.
211  * @clk480m_hw: clock struct of phy output clk management.
212  * @chg_state: states involved in USB charger detection.
213  * @chg_type: USB charger types.
214  * @dcd_retries: The retry count used to track Data contact
215  *		 detection process.
216  * @edev: extcon device for notification registration
217  * @irq: muxed interrupt for single irq configuration
218  * @phy_cfg: phy register configuration, assigned by driver data.
219  * @ports: phy port instance.
220  */
221 struct rockchip_usb2phy {
222 	struct device	*dev;
223 	struct regmap	*grf;
224 	struct regmap	*usbgrf;
225 	struct clk	*clk;
226 	struct clk	*clk480m;
227 	struct clk_hw	clk480m_hw;
228 	enum usb_chg_state	chg_state;
229 	enum power_supply_type	chg_type;
230 	u8			dcd_retries;
231 	struct extcon_dev	*edev;
232 	int			irq;
233 	const struct rockchip_usb2phy_cfg	*phy_cfg;
234 	struct rockchip_usb2phy_port	ports[USB2PHY_NUM_PORTS];
235 };
236 
237 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy)
238 {
239 	return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf;
240 }
241 
242 static inline int property_enable(struct regmap *base,
243 				  const struct usb2phy_reg *reg, bool en)
244 {
245 	unsigned int val, mask, tmp;
246 
247 	tmp = en ? reg->enable : reg->disable;
248 	mask = GENMASK(reg->bitend, reg->bitstart);
249 	val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT);
250 
251 	return regmap_write(base, reg->offset, val);
252 }
253 
254 static inline bool property_enabled(struct regmap *base,
255 				    const struct usb2phy_reg *reg)
256 {
257 	int ret;
258 	unsigned int tmp, orig;
259 	unsigned int mask = GENMASK(reg->bitend, reg->bitstart);
260 
261 	ret = regmap_read(base, reg->offset, &orig);
262 	if (ret)
263 		return false;
264 
265 	tmp = (orig & mask) >> reg->bitstart;
266 	return tmp != reg->disable;
267 }
268 
269 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw)
270 {
271 	struct rockchip_usb2phy *rphy =
272 		container_of(hw, struct rockchip_usb2phy, clk480m_hw);
273 	struct regmap *base = get_reg_base(rphy);
274 	int ret;
275 
276 	/* turn on 480m clk output if it is off */
277 	if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) {
278 		ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true);
279 		if (ret)
280 			return ret;
281 
282 		/* waiting for the clk become stable */
283 		usleep_range(1200, 1300);
284 	}
285 
286 	return 0;
287 }
288 
289 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw)
290 {
291 	struct rockchip_usb2phy *rphy =
292 		container_of(hw, struct rockchip_usb2phy, clk480m_hw);
293 	struct regmap *base = get_reg_base(rphy);
294 
295 	/* turn off 480m clk output */
296 	property_enable(base, &rphy->phy_cfg->clkout_ctl, false);
297 }
298 
299 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw)
300 {
301 	struct rockchip_usb2phy *rphy =
302 		container_of(hw, struct rockchip_usb2phy, clk480m_hw);
303 	struct regmap *base = get_reg_base(rphy);
304 
305 	return property_enabled(base, &rphy->phy_cfg->clkout_ctl);
306 }
307 
308 static unsigned long
309 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw,
310 				     unsigned long parent_rate)
311 {
312 	return 480000000;
313 }
314 
315 static const struct clk_ops rockchip_usb2phy_clkout_ops = {
316 	.prepare = rockchip_usb2phy_clk480m_prepare,
317 	.unprepare = rockchip_usb2phy_clk480m_unprepare,
318 	.is_prepared = rockchip_usb2phy_clk480m_prepared,
319 	.recalc_rate = rockchip_usb2phy_clk480m_recalc_rate,
320 };
321 
322 static void rockchip_usb2phy_clk480m_unregister(void *data)
323 {
324 	struct rockchip_usb2phy *rphy = data;
325 
326 	of_clk_del_provider(rphy->dev->of_node);
327 	clk_unregister(rphy->clk480m);
328 }
329 
330 static int
331 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy)
332 {
333 	struct device_node *node = rphy->dev->of_node;
334 	struct clk_init_data init;
335 	const char *clk_name;
336 	int ret = 0;
337 
338 	init.flags = 0;
339 	init.name = "clk_usbphy_480m";
340 	init.ops = &rockchip_usb2phy_clkout_ops;
341 
342 	/* optional override of the clockname */
343 	of_property_read_string(node, "clock-output-names", &init.name);
344 
345 	if (rphy->clk) {
346 		clk_name = __clk_get_name(rphy->clk);
347 		init.parent_names = &clk_name;
348 		init.num_parents = 1;
349 	} else {
350 		init.parent_names = NULL;
351 		init.num_parents = 0;
352 	}
353 
354 	rphy->clk480m_hw.init = &init;
355 
356 	/* register the clock */
357 	rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw);
358 	if (IS_ERR(rphy->clk480m)) {
359 		ret = PTR_ERR(rphy->clk480m);
360 		goto err_ret;
361 	}
362 
363 	ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m);
364 	if (ret < 0)
365 		goto err_clk_provider;
366 
367 	return devm_add_action_or_reset(rphy->dev, rockchip_usb2phy_clk480m_unregister, rphy);
368 
369 err_clk_provider:
370 	clk_unregister(rphy->clk480m);
371 err_ret:
372 	return ret;
373 }
374 
375 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy)
376 {
377 	int ret;
378 	struct device_node *node = rphy->dev->of_node;
379 	struct extcon_dev *edev;
380 
381 	if (of_property_read_bool(node, "extcon")) {
382 		edev = extcon_get_edev_by_phandle(rphy->dev, 0);
383 		if (IS_ERR(edev)) {
384 			if (PTR_ERR(edev) != -EPROBE_DEFER)
385 				dev_err(rphy->dev, "Invalid or missing extcon\n");
386 			return PTR_ERR(edev);
387 		}
388 	} else {
389 		/* Initialize extcon device */
390 		edev = devm_extcon_dev_allocate(rphy->dev,
391 						rockchip_usb2phy_extcon_cable);
392 
393 		if (IS_ERR(edev))
394 			return -ENOMEM;
395 
396 		ret = devm_extcon_dev_register(rphy->dev, edev);
397 		if (ret) {
398 			dev_err(rphy->dev, "failed to register extcon device\n");
399 			return ret;
400 		}
401 	}
402 
403 	rphy->edev = edev;
404 
405 	return 0;
406 }
407 
408 static int rockchip_usb2phy_init(struct phy *phy)
409 {
410 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
411 	struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
412 	int ret = 0;
413 
414 	mutex_lock(&rport->mutex);
415 
416 	if (rport->port_id == USB2PHY_PORT_OTG) {
417 		if (rport->mode != USB_DR_MODE_HOST &&
418 		    rport->mode != USB_DR_MODE_UNKNOWN) {
419 			/* clear bvalid status and enable bvalid detect irq */
420 			ret = property_enable(rphy->grf,
421 					      &rport->port_cfg->bvalid_det_clr,
422 					      true);
423 			if (ret)
424 				goto out;
425 
426 			ret = property_enable(rphy->grf,
427 					      &rport->port_cfg->bvalid_det_en,
428 					      true);
429 			if (ret)
430 				goto out;
431 
432 			/* clear id status and enable id detect irq */
433 			ret = property_enable(rphy->grf,
434 					      &rport->port_cfg->id_det_clr,
435 					      true);
436 			if (ret)
437 				goto out;
438 
439 			ret = property_enable(rphy->grf,
440 					      &rport->port_cfg->id_det_en,
441 					      true);
442 			if (ret)
443 				goto out;
444 
445 			schedule_delayed_work(&rport->otg_sm_work,
446 					      OTG_SCHEDULE_DELAY * 3);
447 		} else {
448 			/* If OTG works in host only mode, do nothing. */
449 			dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode);
450 		}
451 	} else if (rport->port_id == USB2PHY_PORT_HOST) {
452 		/* clear linestate and enable linestate detect irq */
453 		ret = property_enable(rphy->grf,
454 				      &rport->port_cfg->ls_det_clr, true);
455 		if (ret)
456 			goto out;
457 
458 		ret = property_enable(rphy->grf,
459 				      &rport->port_cfg->ls_det_en, true);
460 		if (ret)
461 			goto out;
462 
463 		schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
464 	}
465 
466 out:
467 	mutex_unlock(&rport->mutex);
468 	return ret;
469 }
470 
471 static int rockchip_usb2phy_power_on(struct phy *phy)
472 {
473 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
474 	struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
475 	struct regmap *base = get_reg_base(rphy);
476 	int ret;
477 
478 	dev_dbg(&rport->phy->dev, "port power on\n");
479 
480 	if (!rport->suspended)
481 		return 0;
482 
483 	ret = clk_prepare_enable(rphy->clk480m);
484 	if (ret)
485 		return ret;
486 
487 	ret = property_enable(base, &rport->port_cfg->phy_sus, false);
488 	if (ret)
489 		return ret;
490 
491 	/* waiting for the utmi_clk to become stable */
492 	usleep_range(1500, 2000);
493 
494 	rport->suspended = false;
495 	return 0;
496 }
497 
498 static int rockchip_usb2phy_power_off(struct phy *phy)
499 {
500 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
501 	struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent);
502 	struct regmap *base = get_reg_base(rphy);
503 	int ret;
504 
505 	dev_dbg(&rport->phy->dev, "port power off\n");
506 
507 	if (rport->suspended)
508 		return 0;
509 
510 	ret = property_enable(base, &rport->port_cfg->phy_sus, true);
511 	if (ret)
512 		return ret;
513 
514 	rport->suspended = true;
515 	clk_disable_unprepare(rphy->clk480m);
516 
517 	return 0;
518 }
519 
520 static int rockchip_usb2phy_exit(struct phy *phy)
521 {
522 	struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy);
523 
524 	if (rport->port_id == USB2PHY_PORT_OTG &&
525 	    rport->mode != USB_DR_MODE_HOST &&
526 	    rport->mode != USB_DR_MODE_UNKNOWN) {
527 		cancel_delayed_work_sync(&rport->otg_sm_work);
528 		cancel_delayed_work_sync(&rport->chg_work);
529 	} else if (rport->port_id == USB2PHY_PORT_HOST)
530 		cancel_delayed_work_sync(&rport->sm_work);
531 
532 	return 0;
533 }
534 
535 static const struct phy_ops rockchip_usb2phy_ops = {
536 	.init		= rockchip_usb2phy_init,
537 	.exit		= rockchip_usb2phy_exit,
538 	.power_on	= rockchip_usb2phy_power_on,
539 	.power_off	= rockchip_usb2phy_power_off,
540 	.owner		= THIS_MODULE,
541 };
542 
543 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work)
544 {
545 	struct rockchip_usb2phy_port *rport =
546 		container_of(work, struct rockchip_usb2phy_port,
547 			     otg_sm_work.work);
548 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
549 	static unsigned int cable;
550 	unsigned long delay;
551 	bool vbus_attach, sch_work, notify_charger;
552 
553 	vbus_attach = property_enabled(rphy->grf,
554 				       &rport->port_cfg->utmi_bvalid);
555 
556 	sch_work = false;
557 	notify_charger = false;
558 	delay = OTG_SCHEDULE_DELAY;
559 	dev_dbg(&rport->phy->dev, "%s otg sm work\n",
560 		usb_otg_state_string(rport->state));
561 
562 	switch (rport->state) {
563 	case OTG_STATE_UNDEFINED:
564 		rport->state = OTG_STATE_B_IDLE;
565 		if (!vbus_attach)
566 			rockchip_usb2phy_power_off(rport->phy);
567 		fallthrough;
568 	case OTG_STATE_B_IDLE:
569 		if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) {
570 			dev_dbg(&rport->phy->dev, "usb otg host connect\n");
571 			rport->state = OTG_STATE_A_HOST;
572 			rockchip_usb2phy_power_on(rport->phy);
573 			return;
574 		} else if (vbus_attach) {
575 			dev_dbg(&rport->phy->dev, "vbus_attach\n");
576 			switch (rphy->chg_state) {
577 			case USB_CHG_STATE_UNDEFINED:
578 				schedule_delayed_work(&rport->chg_work, 0);
579 				return;
580 			case USB_CHG_STATE_DETECTED:
581 				switch (rphy->chg_type) {
582 				case POWER_SUPPLY_TYPE_USB:
583 					dev_dbg(&rport->phy->dev, "sdp cable is connected\n");
584 					rockchip_usb2phy_power_on(rport->phy);
585 					rport->state = OTG_STATE_B_PERIPHERAL;
586 					notify_charger = true;
587 					sch_work = true;
588 					cable = EXTCON_CHG_USB_SDP;
589 					break;
590 				case POWER_SUPPLY_TYPE_USB_DCP:
591 					dev_dbg(&rport->phy->dev, "dcp cable is connected\n");
592 					rockchip_usb2phy_power_off(rport->phy);
593 					notify_charger = true;
594 					sch_work = true;
595 					cable = EXTCON_CHG_USB_DCP;
596 					break;
597 				case POWER_SUPPLY_TYPE_USB_CDP:
598 					dev_dbg(&rport->phy->dev, "cdp cable is connected\n");
599 					rockchip_usb2phy_power_on(rport->phy);
600 					rport->state = OTG_STATE_B_PERIPHERAL;
601 					notify_charger = true;
602 					sch_work = true;
603 					cable = EXTCON_CHG_USB_CDP;
604 					break;
605 				default:
606 					break;
607 				}
608 				break;
609 			default:
610 				break;
611 			}
612 		} else {
613 			notify_charger = true;
614 			rphy->chg_state = USB_CHG_STATE_UNDEFINED;
615 			rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
616 		}
617 
618 		if (rport->vbus_attached != vbus_attach) {
619 			rport->vbus_attached = vbus_attach;
620 
621 			if (notify_charger && rphy->edev) {
622 				extcon_set_state_sync(rphy->edev,
623 							cable, vbus_attach);
624 				if (cable == EXTCON_CHG_USB_SDP)
625 					extcon_set_state_sync(rphy->edev,
626 							      EXTCON_USB,
627 							      vbus_attach);
628 			}
629 		}
630 		break;
631 	case OTG_STATE_B_PERIPHERAL:
632 		if (!vbus_attach) {
633 			dev_dbg(&rport->phy->dev, "usb disconnect\n");
634 			rphy->chg_state = USB_CHG_STATE_UNDEFINED;
635 			rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
636 			rport->state = OTG_STATE_B_IDLE;
637 			delay = 0;
638 			rockchip_usb2phy_power_off(rport->phy);
639 		}
640 		sch_work = true;
641 		break;
642 	case OTG_STATE_A_HOST:
643 		if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) {
644 			dev_dbg(&rport->phy->dev, "usb otg host disconnect\n");
645 			rport->state = OTG_STATE_B_IDLE;
646 			rockchip_usb2phy_power_off(rport->phy);
647 		}
648 		break;
649 	default:
650 		break;
651 	}
652 
653 	if (sch_work)
654 		schedule_delayed_work(&rport->otg_sm_work, delay);
655 }
656 
657 static const char *chg_to_string(enum power_supply_type chg_type)
658 {
659 	switch (chg_type) {
660 	case POWER_SUPPLY_TYPE_USB:
661 		return "USB_SDP_CHARGER";
662 	case POWER_SUPPLY_TYPE_USB_DCP:
663 		return "USB_DCP_CHARGER";
664 	case POWER_SUPPLY_TYPE_USB_CDP:
665 		return "USB_CDP_CHARGER";
666 	default:
667 		return "INVALID_CHARGER";
668 	}
669 }
670 
671 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy,
672 				    bool en)
673 {
674 	struct regmap *base = get_reg_base(rphy);
675 
676 	property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en);
677 	property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en);
678 }
679 
680 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy,
681 					    bool en)
682 {
683 	struct regmap *base = get_reg_base(rphy);
684 
685 	property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en);
686 	property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en);
687 }
688 
689 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy,
690 					      bool en)
691 {
692 	struct regmap *base = get_reg_base(rphy);
693 
694 	property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en);
695 	property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en);
696 }
697 
698 #define CHG_DCD_POLL_TIME	(100 * HZ / 1000)
699 #define CHG_DCD_MAX_RETRIES	6
700 #define CHG_PRIMARY_DET_TIME	(40 * HZ / 1000)
701 #define CHG_SECONDARY_DET_TIME	(40 * HZ / 1000)
702 static void rockchip_chg_detect_work(struct work_struct *work)
703 {
704 	struct rockchip_usb2phy_port *rport =
705 		container_of(work, struct rockchip_usb2phy_port, chg_work.work);
706 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
707 	struct regmap *base = get_reg_base(rphy);
708 	bool is_dcd, tmout, vout;
709 	unsigned long delay;
710 
711 	dev_dbg(&rport->phy->dev, "chg detection work state = %d\n",
712 		rphy->chg_state);
713 	switch (rphy->chg_state) {
714 	case USB_CHG_STATE_UNDEFINED:
715 		if (!rport->suspended)
716 			rockchip_usb2phy_power_off(rport->phy);
717 		/* put the controller in non-driving mode */
718 		property_enable(base, &rphy->phy_cfg->chg_det.opmode, false);
719 		/* Start DCD processing stage 1 */
720 		rockchip_chg_enable_dcd(rphy, true);
721 		rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD;
722 		rphy->dcd_retries = 0;
723 		delay = CHG_DCD_POLL_TIME;
724 		break;
725 	case USB_CHG_STATE_WAIT_FOR_DCD:
726 		/* get data contact detection status */
727 		is_dcd = property_enabled(rphy->grf,
728 					  &rphy->phy_cfg->chg_det.dp_det);
729 		tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES;
730 		/* stage 2 */
731 		if (is_dcd || tmout) {
732 			/* stage 4 */
733 			/* Turn off DCD circuitry */
734 			rockchip_chg_enable_dcd(rphy, false);
735 			/* Voltage Source on DP, Probe on DM */
736 			rockchip_chg_enable_primary_det(rphy, true);
737 			delay = CHG_PRIMARY_DET_TIME;
738 			rphy->chg_state = USB_CHG_STATE_DCD_DONE;
739 		} else {
740 			/* stage 3 */
741 			delay = CHG_DCD_POLL_TIME;
742 		}
743 		break;
744 	case USB_CHG_STATE_DCD_DONE:
745 		vout = property_enabled(rphy->grf,
746 					&rphy->phy_cfg->chg_det.cp_det);
747 		rockchip_chg_enable_primary_det(rphy, false);
748 		if (vout) {
749 			/* Voltage Source on DM, Probe on DP  */
750 			rockchip_chg_enable_secondary_det(rphy, true);
751 			delay = CHG_SECONDARY_DET_TIME;
752 			rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE;
753 		} else {
754 			if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) {
755 				/* floating charger found */
756 				rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
757 				rphy->chg_state = USB_CHG_STATE_DETECTED;
758 				delay = 0;
759 			} else {
760 				rphy->chg_type = POWER_SUPPLY_TYPE_USB;
761 				rphy->chg_state = USB_CHG_STATE_DETECTED;
762 				delay = 0;
763 			}
764 		}
765 		break;
766 	case USB_CHG_STATE_PRIMARY_DONE:
767 		vout = property_enabled(rphy->grf,
768 					&rphy->phy_cfg->chg_det.dcp_det);
769 		/* Turn off voltage source */
770 		rockchip_chg_enable_secondary_det(rphy, false);
771 		if (vout)
772 			rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP;
773 		else
774 			rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP;
775 		fallthrough;
776 	case USB_CHG_STATE_SECONDARY_DONE:
777 		rphy->chg_state = USB_CHG_STATE_DETECTED;
778 		fallthrough;
779 	case USB_CHG_STATE_DETECTED:
780 		/* put the controller in normal mode */
781 		property_enable(base, &rphy->phy_cfg->chg_det.opmode, true);
782 		rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
783 		dev_dbg(&rport->phy->dev, "charger = %s\n",
784 			 chg_to_string(rphy->chg_type));
785 		return;
786 	default:
787 		return;
788 	}
789 
790 	schedule_delayed_work(&rport->chg_work, delay);
791 }
792 
793 /*
794  * The function manage host-phy port state and suspend/resume phy port
795  * to save power.
796  *
797  * we rely on utmi_linestate and utmi_hostdisconnect to identify whether
798  * devices is disconnect or not. Besides, we do not need care it is FS/LS
799  * disconnected or HS disconnected, actually, we just only need get the
800  * device is disconnected at last through rearm the delayed work,
801  * to suspend the phy port in _PHY_STATE_DISCONNECT_ case.
802  *
803  * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke
804  * some clk related APIs, so do not invoke it from interrupt context directly.
805  */
806 static void rockchip_usb2phy_sm_work(struct work_struct *work)
807 {
808 	struct rockchip_usb2phy_port *rport =
809 		container_of(work, struct rockchip_usb2phy_port, sm_work.work);
810 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
811 	unsigned int sh = rport->port_cfg->utmi_hstdet.bitend -
812 			  rport->port_cfg->utmi_hstdet.bitstart + 1;
813 	unsigned int ul, uhd, state;
814 	unsigned int ul_mask, uhd_mask;
815 	int ret;
816 
817 	mutex_lock(&rport->mutex);
818 
819 	ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul);
820 	if (ret < 0)
821 		goto next_schedule;
822 
823 	ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd);
824 	if (ret < 0)
825 		goto next_schedule;
826 
827 	uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend,
828 			   rport->port_cfg->utmi_hstdet.bitstart);
829 	ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend,
830 			  rport->port_cfg->utmi_ls.bitstart);
831 
832 	/* stitch on utmi_ls and utmi_hstdet as phy state */
833 	state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) |
834 		(((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh);
835 
836 	switch (state) {
837 	case PHY_STATE_HS_ONLINE:
838 		dev_dbg(&rport->phy->dev, "HS online\n");
839 		break;
840 	case PHY_STATE_FS_LS_ONLINE:
841 		/*
842 		 * For FS/LS device, the online state share with connect state
843 		 * from utmi_ls and utmi_hstdet register, so we distinguish
844 		 * them via suspended flag.
845 		 *
846 		 * Plus, there are two cases, one is D- Line pull-up, and D+
847 		 * line pull-down, the state is 4; another is D+ line pull-up,
848 		 * and D- line pull-down, the state is 2.
849 		 */
850 		if (!rport->suspended) {
851 			/* D- line pull-up, D+ line pull-down */
852 			dev_dbg(&rport->phy->dev, "FS/LS online\n");
853 			break;
854 		}
855 		fallthrough;
856 	case PHY_STATE_CONNECT:
857 		if (rport->suspended) {
858 			dev_dbg(&rport->phy->dev, "Connected\n");
859 			rockchip_usb2phy_power_on(rport->phy);
860 			rport->suspended = false;
861 		} else {
862 			/* D+ line pull-up, D- line pull-down */
863 			dev_dbg(&rport->phy->dev, "FS/LS online\n");
864 		}
865 		break;
866 	case PHY_STATE_DISCONNECT:
867 		if (!rport->suspended) {
868 			dev_dbg(&rport->phy->dev, "Disconnected\n");
869 			rockchip_usb2phy_power_off(rport->phy);
870 			rport->suspended = true;
871 		}
872 
873 		/*
874 		 * activate the linestate detection to get the next device
875 		 * plug-in irq.
876 		 */
877 		property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
878 		property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true);
879 
880 		/*
881 		 * we don't need to rearm the delayed work when the phy port
882 		 * is suspended.
883 		 */
884 		mutex_unlock(&rport->mutex);
885 		return;
886 	default:
887 		dev_dbg(&rport->phy->dev, "unknown phy state\n");
888 		break;
889 	}
890 
891 next_schedule:
892 	mutex_unlock(&rport->mutex);
893 	schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY);
894 }
895 
896 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data)
897 {
898 	struct rockchip_usb2phy_port *rport = data;
899 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
900 
901 	if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st))
902 		return IRQ_NONE;
903 
904 	mutex_lock(&rport->mutex);
905 
906 	/* disable linestate detect irq and clear its status */
907 	property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false);
908 	property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true);
909 
910 	mutex_unlock(&rport->mutex);
911 
912 	/*
913 	 * In this case for host phy port, a new device is plugged in,
914 	 * meanwhile, if the phy port is suspended, we need rearm the work to
915 	 * resume it and mange its states; otherwise, we do nothing about that.
916 	 */
917 	if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST)
918 		rockchip_usb2phy_sm_work(&rport->sm_work.work);
919 
920 	return IRQ_HANDLED;
921 }
922 
923 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data)
924 {
925 	struct rockchip_usb2phy_port *rport = data;
926 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
927 
928 	if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st))
929 		return IRQ_NONE;
930 
931 	/* clear bvalid detect irq pending status */
932 	property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true);
933 
934 	rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work);
935 
936 	return IRQ_HANDLED;
937 }
938 
939 static irqreturn_t rockchip_usb2phy_id_irq(int irq, void *data)
940 {
941 	struct rockchip_usb2phy_port *rport = data;
942 	struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent);
943 	bool id;
944 
945 	if (!property_enabled(rphy->grf, &rport->port_cfg->id_det_st))
946 		return IRQ_NONE;
947 
948 	/* clear id detect irq pending status */
949 	property_enable(rphy->grf, &rport->port_cfg->id_det_clr, true);
950 
951 	id = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
952 	extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !id);
953 
954 	return IRQ_HANDLED;
955 }
956 
957 static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data)
958 {
959 	irqreturn_t ret = IRQ_NONE;
960 
961 	ret |= rockchip_usb2phy_bvalid_irq(irq, data);
962 	ret |= rockchip_usb2phy_id_irq(irq, data);
963 
964 	return ret;
965 }
966 
967 static irqreturn_t rockchip_usb2phy_irq(int irq, void *data)
968 {
969 	struct rockchip_usb2phy *rphy = data;
970 	struct rockchip_usb2phy_port *rport;
971 	irqreturn_t ret = IRQ_NONE;
972 	unsigned int index;
973 
974 	for (index = 0; index < rphy->phy_cfg->num_ports; index++) {
975 		rport = &rphy->ports[index];
976 		if (!rport->phy)
977 			continue;
978 
979 		switch (rport->port_id) {
980 		case USB2PHY_PORT_OTG:
981 			if (rport->mode != USB_DR_MODE_HOST &&
982 			    rport->mode != USB_DR_MODE_UNKNOWN)
983 				ret |= rockchip_usb2phy_otg_mux_irq(irq, rport);
984 			break;
985 		case USB2PHY_PORT_HOST:
986 			ret |= rockchip_usb2phy_linestate_irq(irq, rport);
987 			break;
988 		}
989 	}
990 
991 	return ret;
992 }
993 
994 static int rockchip_usb2phy_port_irq_init(struct rockchip_usb2phy *rphy,
995 					  struct rockchip_usb2phy_port *rport,
996 					  struct device_node *child_np)
997 {
998 	int ret;
999 
1000 	/*
1001 	 * If the usb2 phy used combined irq for otg and host port,
1002 	 * don't need to init otg and host port irq separately.
1003 	 */
1004 	if (rphy->irq > 0)
1005 		return 0;
1006 
1007 	switch (rport->port_id) {
1008 	case USB2PHY_PORT_HOST:
1009 		rport->ls_irq = of_irq_get_byname(child_np, "linestate");
1010 		if (rport->ls_irq < 0) {
1011 			dev_err(rphy->dev, "no linestate irq provided\n");
1012 			return rport->ls_irq;
1013 		}
1014 
1015 		ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL,
1016 						rockchip_usb2phy_linestate_irq,
1017 						IRQF_ONESHOT,
1018 						"rockchip_usb2phy", rport);
1019 		if (ret) {
1020 			dev_err(rphy->dev, "failed to request linestate irq handle\n");
1021 			return ret;
1022 		}
1023 		break;
1024 	case USB2PHY_PORT_OTG:
1025 		/*
1026 		 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate
1027 		 * interrupts muxed together, so probe the otg-mux interrupt first,
1028 		 * if not found, then look for the regular interrupts one by one.
1029 		 */
1030 		rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux");
1031 		if (rport->otg_mux_irq > 0) {
1032 			ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq,
1033 							NULL,
1034 							rockchip_usb2phy_otg_mux_irq,
1035 							IRQF_ONESHOT,
1036 							"rockchip_usb2phy_otg",
1037 							rport);
1038 			if (ret) {
1039 				dev_err(rphy->dev,
1040 					"failed to request otg-mux irq handle\n");
1041 				return ret;
1042 			}
1043 		} else {
1044 			rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid");
1045 			if (rport->bvalid_irq < 0) {
1046 				dev_err(rphy->dev, "no vbus valid irq provided\n");
1047 				ret = rport->bvalid_irq;
1048 				return ret;
1049 			}
1050 
1051 			ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq,
1052 							NULL,
1053 							rockchip_usb2phy_bvalid_irq,
1054 							IRQF_ONESHOT,
1055 							"rockchip_usb2phy_bvalid",
1056 							rport);
1057 			if (ret) {
1058 				dev_err(rphy->dev,
1059 					"failed to request otg-bvalid irq handle\n");
1060 				return ret;
1061 			}
1062 
1063 			rport->id_irq = of_irq_get_byname(child_np, "otg-id");
1064 			if (rport->id_irq < 0) {
1065 				dev_err(rphy->dev, "no otg-id irq provided\n");
1066 				ret = rport->id_irq;
1067 				return ret;
1068 			}
1069 
1070 			ret = devm_request_threaded_irq(rphy->dev, rport->id_irq,
1071 							NULL,
1072 							rockchip_usb2phy_id_irq,
1073 							IRQF_ONESHOT,
1074 							"rockchip_usb2phy_id",
1075 							rport);
1076 			if (ret) {
1077 				dev_err(rphy->dev,
1078 					"failed to request otg-id irq handle\n");
1079 				return ret;
1080 			}
1081 		}
1082 		break;
1083 	default:
1084 		return -EINVAL;
1085 	}
1086 
1087 	return 0;
1088 }
1089 
1090 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy,
1091 					   struct rockchip_usb2phy_port *rport,
1092 					   struct device_node *child_np)
1093 {
1094 	int ret;
1095 
1096 	rport->port_id = USB2PHY_PORT_HOST;
1097 	rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST];
1098 	rport->suspended = true;
1099 
1100 	mutex_init(&rport->mutex);
1101 	INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work);
1102 
1103 	ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1104 	if (ret) {
1105 		dev_err(rphy->dev, "failed to setup host irq\n");
1106 		return ret;
1107 	}
1108 
1109 	return 0;
1110 }
1111 
1112 static int rockchip_otg_event(struct notifier_block *nb,
1113 			      unsigned long event, void *ptr)
1114 {
1115 	struct rockchip_usb2phy_port *rport =
1116 		container_of(nb, struct rockchip_usb2phy_port, event_nb);
1117 
1118 	schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY);
1119 
1120 	return NOTIFY_DONE;
1121 }
1122 
1123 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy,
1124 					  struct rockchip_usb2phy_port *rport,
1125 					  struct device_node *child_np)
1126 {
1127 	int ret;
1128 
1129 	rport->port_id = USB2PHY_PORT_OTG;
1130 	rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG];
1131 	rport->state = OTG_STATE_UNDEFINED;
1132 
1133 	/*
1134 	 * set suspended flag to true, but actually don't
1135 	 * put phy in suspend mode, it aims to enable usb
1136 	 * phy and clock in power_on() called by usb controller
1137 	 * driver during probe.
1138 	 */
1139 	rport->suspended = true;
1140 	rport->vbus_attached = false;
1141 
1142 	mutex_init(&rport->mutex);
1143 
1144 	rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1);
1145 	if (rport->mode == USB_DR_MODE_HOST ||
1146 	    rport->mode == USB_DR_MODE_UNKNOWN) {
1147 		ret = 0;
1148 		goto out;
1149 	}
1150 
1151 	INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work);
1152 	INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work);
1153 
1154 	ret = rockchip_usb2phy_port_irq_init(rphy, rport, child_np);
1155 	if (ret) {
1156 		dev_err(rphy->dev, "failed to init irq for host port\n");
1157 		goto out;
1158 	}
1159 
1160 	if (!IS_ERR(rphy->edev)) {
1161 		rport->event_nb.notifier_call = rockchip_otg_event;
1162 
1163 		ret = devm_extcon_register_notifier(rphy->dev, rphy->edev,
1164 					EXTCON_USB_HOST, &rport->event_nb);
1165 		if (ret)
1166 			dev_err(rphy->dev, "register USB HOST notifier failed\n");
1167 
1168 		if (!of_property_read_bool(rphy->dev->of_node, "extcon")) {
1169 			/* do initial sync of usb state */
1170 			ret = property_enabled(rphy->grf, &rport->port_cfg->utmi_id);
1171 			extcon_set_state_sync(rphy->edev, EXTCON_USB_HOST, !ret);
1172 		}
1173 	}
1174 
1175 out:
1176 	return ret;
1177 }
1178 
1179 static int rockchip_usb2phy_probe(struct platform_device *pdev)
1180 {
1181 	struct device *dev = &pdev->dev;
1182 	struct device_node *np = dev->of_node;
1183 	struct device_node *child_np;
1184 	struct phy_provider *provider;
1185 	struct rockchip_usb2phy *rphy;
1186 	const struct rockchip_usb2phy_cfg *phy_cfgs;
1187 	const struct of_device_id *match;
1188 	unsigned int reg;
1189 	int index, ret;
1190 
1191 	rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL);
1192 	if (!rphy)
1193 		return -ENOMEM;
1194 
1195 	match = of_match_device(dev->driver->of_match_table, dev);
1196 	if (!match || !match->data) {
1197 		dev_err(dev, "phy configs are not assigned!\n");
1198 		return -EINVAL;
1199 	}
1200 
1201 	if (!dev->parent || !dev->parent->of_node) {
1202 		rphy->grf = syscon_regmap_lookup_by_phandle(np, "rockchip,usbgrf");
1203 		if (IS_ERR(rphy->grf)) {
1204 			dev_err(dev, "failed to locate usbgrf\n");
1205 			return PTR_ERR(rphy->grf);
1206 		}
1207 	}
1208 
1209 	else {
1210 		rphy->grf = syscon_node_to_regmap(dev->parent->of_node);
1211 		if (IS_ERR(rphy->grf))
1212 			return PTR_ERR(rphy->grf);
1213 	}
1214 
1215 	if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) {
1216 		rphy->usbgrf =
1217 			syscon_regmap_lookup_by_phandle(dev->of_node,
1218 							"rockchip,usbgrf");
1219 		if (IS_ERR(rphy->usbgrf))
1220 			return PTR_ERR(rphy->usbgrf);
1221 	} else {
1222 		rphy->usbgrf = NULL;
1223 	}
1224 
1225 	if (of_property_read_u32_index(np, "reg", 0, &reg)) {
1226 		dev_err(dev, "the reg property is not assigned in %pOFn node\n",
1227 			np);
1228 		return -EINVAL;
1229 	}
1230 
1231 	/* support address_cells=2 */
1232 	if (reg == 0) {
1233 		if (of_property_read_u32_index(np, "reg", 1, &reg)) {
1234 			dev_err(dev, "the reg property is not assigned in %pOFn node\n",
1235 				np);
1236 			return -EINVAL;
1237 		}
1238 	}
1239 
1240 	rphy->dev = dev;
1241 	phy_cfgs = match->data;
1242 	rphy->chg_state = USB_CHG_STATE_UNDEFINED;
1243 	rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN;
1244 	rphy->irq = platform_get_irq_optional(pdev, 0);
1245 	platform_set_drvdata(pdev, rphy);
1246 
1247 	ret = rockchip_usb2phy_extcon_register(rphy);
1248 	if (ret)
1249 		return ret;
1250 
1251 	/* find out a proper config which can be matched with dt. */
1252 	index = 0;
1253 	while (phy_cfgs[index].reg) {
1254 		if (phy_cfgs[index].reg == reg) {
1255 			rphy->phy_cfg = &phy_cfgs[index];
1256 			break;
1257 		}
1258 
1259 		++index;
1260 	}
1261 
1262 	if (!rphy->phy_cfg) {
1263 		dev_err(dev, "no phy-config can be matched with %pOFn node\n",
1264 			np);
1265 		return -EINVAL;
1266 	}
1267 
1268 	rphy->clk = of_clk_get_by_name(np, "phyclk");
1269 	if (!IS_ERR(rphy->clk)) {
1270 		clk_prepare_enable(rphy->clk);
1271 	} else {
1272 		dev_info(&pdev->dev, "no phyclk specified\n");
1273 		rphy->clk = NULL;
1274 	}
1275 
1276 	ret = rockchip_usb2phy_clk480m_register(rphy);
1277 	if (ret) {
1278 		dev_err(dev, "failed to register 480m output clock\n");
1279 		goto disable_clks;
1280 	}
1281 
1282 	index = 0;
1283 	for_each_available_child_of_node(np, child_np) {
1284 		struct rockchip_usb2phy_port *rport = &rphy->ports[index];
1285 		struct phy *phy;
1286 
1287 		/* This driver aims to support both otg-port and host-port */
1288 		if (!of_node_name_eq(child_np, "host-port") &&
1289 		    !of_node_name_eq(child_np, "otg-port"))
1290 			goto next_child;
1291 
1292 		phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops);
1293 		if (IS_ERR(phy)) {
1294 			dev_err_probe(dev, PTR_ERR(phy), "failed to create phy\n");
1295 			ret = PTR_ERR(phy);
1296 			goto put_child;
1297 		}
1298 
1299 		rport->phy = phy;
1300 		phy_set_drvdata(rport->phy, rport);
1301 
1302 		/* initialize otg/host port separately */
1303 		if (of_node_name_eq(child_np, "host-port")) {
1304 			ret = rockchip_usb2phy_host_port_init(rphy, rport,
1305 							      child_np);
1306 			if (ret)
1307 				goto put_child;
1308 		} else {
1309 			ret = rockchip_usb2phy_otg_port_init(rphy, rport,
1310 							     child_np);
1311 			if (ret)
1312 				goto put_child;
1313 		}
1314 
1315 next_child:
1316 		/* to prevent out of boundary */
1317 		if (++index >= rphy->phy_cfg->num_ports) {
1318 			of_node_put(child_np);
1319 			break;
1320 		}
1321 	}
1322 
1323 	provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
1324 
1325 	if (rphy->irq > 0) {
1326 		ret = devm_request_threaded_irq(rphy->dev, rphy->irq, NULL,
1327 						rockchip_usb2phy_irq,
1328 						IRQF_ONESHOT,
1329 						"rockchip_usb2phy",
1330 						rphy);
1331 		if (ret) {
1332 			dev_err(rphy->dev,
1333 				"failed to request usb2phy irq handle\n");
1334 			goto put_child;
1335 		}
1336 	}
1337 
1338 	return PTR_ERR_OR_ZERO(provider);
1339 
1340 put_child:
1341 	of_node_put(child_np);
1342 disable_clks:
1343 	if (rphy->clk) {
1344 		clk_disable_unprepare(rphy->clk);
1345 		clk_put(rphy->clk);
1346 	}
1347 	return ret;
1348 }
1349 
1350 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = {
1351 	{
1352 		.reg = 0x760,
1353 		.num_ports	= 2,
1354 		.clkout_ctl	= { 0x0768, 4, 4, 1, 0 },
1355 		.port_cfgs	= {
1356 			[USB2PHY_PORT_OTG] = {
1357 				.phy_sus	= { 0x0760, 15, 0, 0, 0x1d1 },
1358 				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
1359 				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
1360 				.bvalid_det_clr	= { 0x06a0, 3, 3, 0, 1 },
1361 				.id_det_en	= { 0x0680, 6, 5, 0, 3 },
1362 				.id_det_st	= { 0x0690, 6, 5, 0, 3 },
1363 				.id_det_clr	= { 0x06a0, 6, 5, 0, 3 },
1364 				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
1365 				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
1366 				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
1367 				.utmi_bvalid	= { 0x0480, 4, 4, 0, 1 },
1368 				.utmi_id	= { 0x0480, 1, 1, 0, 1 },
1369 				.utmi_ls	= { 0x0480, 3, 2, 0, 1 },
1370 			},
1371 			[USB2PHY_PORT_HOST] = {
1372 				.phy_sus	= { 0x0764, 15, 0, 0, 0x1d1 },
1373 				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
1374 				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
1375 				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 }
1376 			}
1377 		},
1378 		.chg_det = {
1379 			.opmode		= { 0x0760, 3, 0, 5, 1 },
1380 			.cp_det		= { 0x0884, 4, 4, 0, 1 },
1381 			.dcp_det	= { 0x0884, 3, 3, 0, 1 },
1382 			.dp_det		= { 0x0884, 5, 5, 0, 1 },
1383 			.idm_sink_en	= { 0x0768, 8, 8, 0, 1 },
1384 			.idp_sink_en	= { 0x0768, 7, 7, 0, 1 },
1385 			.idp_src_en	= { 0x0768, 9, 9, 0, 1 },
1386 			.rdm_pdwn_en	= { 0x0768, 10, 10, 0, 1 },
1387 			.vdm_src_en	= { 0x0768, 12, 12, 0, 1 },
1388 			.vdp_src_en	= { 0x0768, 11, 11, 0, 1 },
1389 		},
1390 	},
1391 	{
1392 		.reg = 0x800,
1393 		.num_ports	= 2,
1394 		.clkout_ctl	= { 0x0808, 4, 4, 1, 0 },
1395 		.port_cfgs	= {
1396 			[USB2PHY_PORT_OTG] = {
1397 				.phy_sus	= { 0x800, 15, 0, 0, 0x1d1 },
1398 				.ls_det_en	= { 0x0684, 0, 0, 0, 1 },
1399 				.ls_det_st	= { 0x0694, 0, 0, 0, 1 },
1400 				.ls_det_clr	= { 0x06a4, 0, 0, 0, 1 }
1401 			},
1402 			[USB2PHY_PORT_HOST] = {
1403 				.phy_sus	= { 0x804, 15, 0, 0, 0x1d1 },
1404 				.ls_det_en	= { 0x0684, 1, 1, 0, 1 },
1405 				.ls_det_st	= { 0x0694, 1, 1, 0, 1 },
1406 				.ls_det_clr	= { 0x06a4, 1, 1, 0, 1 }
1407 			}
1408 		},
1409 	},
1410 	{ /* sentinel */ }
1411 };
1412 
1413 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = {
1414 	{
1415 		.reg = 0x100,
1416 		.num_ports	= 2,
1417 		.clkout_ctl	= { 0x108, 4, 4, 1, 0 },
1418 		.port_cfgs	= {
1419 			[USB2PHY_PORT_OTG] = {
1420 				.phy_sus	= { 0x0100, 8, 0, 0, 0x1d1 },
1421 				.bvalid_det_en	= { 0x3020, 3, 2, 0, 3 },
1422 				.bvalid_det_st	= { 0x3024, 3, 2, 0, 3 },
1423 				.bvalid_det_clr = { 0x3028, 3, 2, 0, 3 },
1424 				.id_det_en	= { 0x3020, 5, 4, 0, 3 },
1425 				.id_det_st	= { 0x3024, 5, 4, 0, 3 },
1426 				.id_det_clr	= { 0x3028, 5, 4, 0, 3 },
1427 				.ls_det_en	= { 0x3020, 0, 0, 0, 1 },
1428 				.ls_det_st	= { 0x3024, 0, 0, 0, 1 },
1429 				.ls_det_clr	= { 0x3028, 0, 0, 0, 1 },
1430 				.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
1431 				.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
1432 				.utmi_id	= { 0x0120, 6, 6, 0, 1 },
1433 				.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
1434 			},
1435 			[USB2PHY_PORT_HOST] = {
1436 				.phy_sus	= { 0x0104, 8, 0, 0, 0x1d1 },
1437 				.ls_det_en	= { 0x3020, 1, 1, 0, 1 },
1438 				.ls_det_st	= { 0x3024, 1, 1, 0, 1 },
1439 				.ls_det_clr	= { 0x3028, 1, 1, 0, 1 },
1440 				.utmi_ls	= { 0x0120, 17, 16, 0, 1 },
1441 				.utmi_hstdet	= { 0x0120, 19, 19, 0, 1 }
1442 			}
1443 		},
1444 		.chg_det = {
1445 			.opmode		= { 0x0100, 3, 0, 5, 1 },
1446 			.cp_det		= { 0x0120, 24, 24, 0, 1 },
1447 			.dcp_det	= { 0x0120, 23, 23, 0, 1 },
1448 			.dp_det		= { 0x0120, 25, 25, 0, 1 },
1449 			.idm_sink_en	= { 0x0108, 8, 8, 0, 1 },
1450 			.idp_sink_en	= { 0x0108, 7, 7, 0, 1 },
1451 			.idp_src_en	= { 0x0108, 9, 9, 0, 1 },
1452 			.rdm_pdwn_en	= { 0x0108, 10, 10, 0, 1 },
1453 			.vdm_src_en	= { 0x0108, 12, 12, 0, 1 },
1454 			.vdp_src_en	= { 0x0108, 11, 11, 0, 1 },
1455 		},
1456 	},
1457 	{ /* sentinel */ }
1458 };
1459 
1460 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = {
1461 	{
1462 		.reg = 0x100,
1463 		.num_ports	= 2,
1464 		.clkout_ctl	= { 0x108, 4, 4, 1, 0 },
1465 		.port_cfgs	= {
1466 			[USB2PHY_PORT_OTG] = {
1467 				.phy_sus	= { 0x0100, 15, 0, 0, 0x1d1 },
1468 				.bvalid_det_en	= { 0x0110, 3, 2, 0, 3 },
1469 				.bvalid_det_st	= { 0x0114, 3, 2, 0, 3 },
1470 				.bvalid_det_clr = { 0x0118, 3, 2, 0, 3 },
1471 				.id_det_en	= { 0x0110, 5, 4, 0, 3 },
1472 				.id_det_st	= { 0x0114, 5, 4, 0, 3 },
1473 				.id_det_clr	= { 0x0118, 5, 4, 0, 3 },
1474 				.ls_det_en	= { 0x0110, 0, 0, 0, 1 },
1475 				.ls_det_st	= { 0x0114, 0, 0, 0, 1 },
1476 				.ls_det_clr	= { 0x0118, 0, 0, 0, 1 },
1477 				.utmi_avalid	= { 0x0120, 10, 10, 0, 1 },
1478 				.utmi_bvalid	= { 0x0120, 9, 9, 0, 1 },
1479 				.utmi_id	= { 0x0120, 6, 6, 0, 1 },
1480 				.utmi_ls	= { 0x0120, 5, 4, 0, 1 },
1481 			},
1482 			[USB2PHY_PORT_HOST] = {
1483 				.phy_sus	= { 0x104, 15, 0, 0, 0x1d1 },
1484 				.ls_det_en	= { 0x110, 1, 1, 0, 1 },
1485 				.ls_det_st	= { 0x114, 1, 1, 0, 1 },
1486 				.ls_det_clr	= { 0x118, 1, 1, 0, 1 },
1487 				.utmi_ls	= { 0x120, 17, 16, 0, 1 },
1488 				.utmi_hstdet	= { 0x120, 19, 19, 0, 1 }
1489 			}
1490 		},
1491 		.chg_det = {
1492 			.opmode		= { 0x0100, 3, 0, 5, 1 },
1493 			.cp_det		= { 0x0120, 24, 24, 0, 1 },
1494 			.dcp_det	= { 0x0120, 23, 23, 0, 1 },
1495 			.dp_det		= { 0x0120, 25, 25, 0, 1 },
1496 			.idm_sink_en	= { 0x0108, 8, 8, 0, 1 },
1497 			.idp_sink_en	= { 0x0108, 7, 7, 0, 1 },
1498 			.idp_src_en	= { 0x0108, 9, 9, 0, 1 },
1499 			.rdm_pdwn_en	= { 0x0108, 10, 10, 0, 1 },
1500 			.vdm_src_en	= { 0x0108, 12, 12, 0, 1 },
1501 			.vdp_src_en	= { 0x0108, 11, 11, 0, 1 },
1502 		},
1503 	},
1504 	{ /* sentinel */ }
1505 };
1506 
1507 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = {
1508 	{
1509 		.reg = 0x700,
1510 		.num_ports	= 2,
1511 		.clkout_ctl	= { 0x0724, 15, 15, 1, 0 },
1512 		.port_cfgs	= {
1513 			[USB2PHY_PORT_HOST] = {
1514 				.phy_sus	= { 0x0728, 15, 0, 0, 0x1d1 },
1515 				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
1516 				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
1517 				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 },
1518 				.utmi_ls	= { 0x049c, 14, 13, 0, 1 },
1519 				.utmi_hstdet	= { 0x049c, 12, 12, 0, 1 }
1520 			}
1521 		},
1522 	},
1523 	{ /* sentinel */ }
1524 };
1525 
1526 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = {
1527 	{
1528 		.reg		= 0xe450,
1529 		.num_ports	= 2,
1530 		.clkout_ctl	= { 0xe450, 4, 4, 1, 0 },
1531 		.port_cfgs	= {
1532 			[USB2PHY_PORT_OTG] = {
1533 				.phy_sus	= { 0xe454, 1, 0, 2, 1 },
1534 				.bvalid_det_en	= { 0xe3c0, 3, 3, 0, 1 },
1535 				.bvalid_det_st	= { 0xe3e0, 3, 3, 0, 1 },
1536 				.bvalid_det_clr	= { 0xe3d0, 3, 3, 0, 1 },
1537 				.id_det_en	= { 0xe3c0, 5, 4, 0, 3 },
1538 				.id_det_st	= { 0xe3e0, 5, 4, 0, 3 },
1539 				.id_det_clr	= { 0xe3d0, 5, 4, 0, 3 },
1540 				.utmi_avalid	= { 0xe2ac, 7, 7, 0, 1 },
1541 				.utmi_bvalid	= { 0xe2ac, 12, 12, 0, 1 },
1542 				.utmi_id	= { 0xe2ac, 8, 8, 0, 1 },
1543 			},
1544 			[USB2PHY_PORT_HOST] = {
1545 				.phy_sus	= { 0xe458, 1, 0, 0x2, 0x1 },
1546 				.ls_det_en	= { 0xe3c0, 6, 6, 0, 1 },
1547 				.ls_det_st	= { 0xe3e0, 6, 6, 0, 1 },
1548 				.ls_det_clr	= { 0xe3d0, 6, 6, 0, 1 },
1549 				.utmi_ls	= { 0xe2ac, 22, 21, 0, 1 },
1550 				.utmi_hstdet	= { 0xe2ac, 23, 23, 0, 1 }
1551 			}
1552 		},
1553 		.chg_det = {
1554 			.opmode		= { 0xe454, 3, 0, 5, 1 },
1555 			.cp_det		= { 0xe2ac, 2, 2, 0, 1 },
1556 			.dcp_det	= { 0xe2ac, 1, 1, 0, 1 },
1557 			.dp_det		= { 0xe2ac, 0, 0, 0, 1 },
1558 			.idm_sink_en	= { 0xe450, 8, 8, 0, 1 },
1559 			.idp_sink_en	= { 0xe450, 7, 7, 0, 1 },
1560 			.idp_src_en	= { 0xe450, 9, 9, 0, 1 },
1561 			.rdm_pdwn_en	= { 0xe450, 10, 10, 0, 1 },
1562 			.vdm_src_en	= { 0xe450, 12, 12, 0, 1 },
1563 			.vdp_src_en	= { 0xe450, 11, 11, 0, 1 },
1564 		},
1565 	},
1566 	{
1567 		.reg		= 0xe460,
1568 		.num_ports	= 2,
1569 		.clkout_ctl	= { 0xe460, 4, 4, 1, 0 },
1570 		.port_cfgs	= {
1571 			[USB2PHY_PORT_OTG] = {
1572 				.phy_sus        = { 0xe464, 1, 0, 2, 1 },
1573 				.bvalid_det_en  = { 0xe3c0, 8, 8, 0, 1 },
1574 				.bvalid_det_st  = { 0xe3e0, 8, 8, 0, 1 },
1575 				.bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 },
1576 				.id_det_en	= { 0xe3c0, 10, 9, 0, 3 },
1577 				.id_det_st	= { 0xe3e0, 10, 9, 0, 3 },
1578 				.id_det_clr	= { 0xe3d0, 10, 9, 0, 3 },
1579 				.utmi_avalid	= { 0xe2ac, 10, 10, 0, 1 },
1580 				.utmi_bvalid    = { 0xe2ac, 16, 16, 0, 1 },
1581 				.utmi_id	= { 0xe2ac, 11, 11, 0, 1 },
1582 			},
1583 			[USB2PHY_PORT_HOST] = {
1584 				.phy_sus	= { 0xe468, 1, 0, 0x2, 0x1 },
1585 				.ls_det_en	= { 0xe3c0, 11, 11, 0, 1 },
1586 				.ls_det_st	= { 0xe3e0, 11, 11, 0, 1 },
1587 				.ls_det_clr	= { 0xe3d0, 11, 11, 0, 1 },
1588 				.utmi_ls	= { 0xe2ac, 26, 25, 0, 1 },
1589 				.utmi_hstdet	= { 0xe2ac, 27, 27, 0, 1 }
1590 			}
1591 		},
1592 	},
1593 	{ /* sentinel */ }
1594 };
1595 
1596 static const struct rockchip_usb2phy_cfg rk3568_phy_cfgs[] = {
1597 	{
1598 		.reg = 0xfe8a0000,
1599 		.num_ports	= 2,
1600 		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },
1601 		.port_cfgs	= {
1602 			[USB2PHY_PORT_OTG] = {
1603 				.phy_sus	= { 0x0000, 8, 0, 0, 0x1d1 },
1604 				.bvalid_det_en	= { 0x0080, 3, 2, 0, 3 },
1605 				.bvalid_det_st	= { 0x0084, 3, 2, 0, 3 },
1606 				.bvalid_det_clr = { 0x0088, 3, 2, 0, 3 },
1607 				.id_det_en	= { 0x0080, 5, 4, 0, 3 },
1608 				.id_det_st	= { 0x0084, 5, 4, 0, 3 },
1609 				.id_det_clr	= { 0x0088, 5, 4, 0, 3 },
1610 				.utmi_avalid	= { 0x00c0, 10, 10, 0, 1 },
1611 				.utmi_bvalid	= { 0x00c0, 9, 9, 0, 1 },
1612 				.utmi_id	= { 0x00c0, 6, 6, 0, 1 },
1613 			},
1614 			[USB2PHY_PORT_HOST] = {
1615 				/* Select suspend control from controller */
1616 				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d2 },
1617 				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },
1618 				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },
1619 				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },
1620 				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },
1621 				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }
1622 			}
1623 		},
1624 		.chg_det = {
1625 			.opmode		= { 0x0000, 3, 0, 5, 1 },
1626 			.cp_det		= { 0x00c0, 24, 24, 0, 1 },
1627 			.dcp_det	= { 0x00c0, 23, 23, 0, 1 },
1628 			.dp_det		= { 0x00c0, 25, 25, 0, 1 },
1629 			.idm_sink_en	= { 0x0008, 8, 8, 0, 1 },
1630 			.idp_sink_en	= { 0x0008, 7, 7, 0, 1 },
1631 			.idp_src_en	= { 0x0008, 9, 9, 0, 1 },
1632 			.rdm_pdwn_en	= { 0x0008, 10, 10, 0, 1 },
1633 			.vdm_src_en	= { 0x0008, 12, 12, 0, 1 },
1634 			.vdp_src_en	= { 0x0008, 11, 11, 0, 1 },
1635 		},
1636 	},
1637 	{
1638 		.reg = 0xfe8b0000,
1639 		.num_ports	= 2,
1640 		.clkout_ctl	= { 0x0008, 4, 4, 1, 0 },
1641 		.port_cfgs	= {
1642 			[USB2PHY_PORT_OTG] = {
1643 				.phy_sus	= { 0x0000, 8, 0, 0x1d2, 0x1d1 },
1644 				.ls_det_en	= { 0x0080, 0, 0, 0, 1 },
1645 				.ls_det_st	= { 0x0084, 0, 0, 0, 1 },
1646 				.ls_det_clr	= { 0x0088, 0, 0, 0, 1 },
1647 				.utmi_ls	= { 0x00c0, 5, 4, 0, 1 },
1648 				.utmi_hstdet	= { 0x00c0, 7, 7, 0, 1 }
1649 			},
1650 			[USB2PHY_PORT_HOST] = {
1651 				.phy_sus	= { 0x0004, 8, 0, 0x1d2, 0x1d1 },
1652 				.ls_det_en	= { 0x0080, 1, 1, 0, 1 },
1653 				.ls_det_st	= { 0x0084, 1, 1, 0, 1 },
1654 				.ls_det_clr	= { 0x0088, 1, 1, 0, 1 },
1655 				.utmi_ls	= { 0x00c0, 17, 16, 0, 1 },
1656 				.utmi_hstdet	= { 0x00c0, 19, 19, 0, 1 }
1657 			}
1658 		},
1659 	},
1660 	{ /* sentinel */ }
1661 };
1662 
1663 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = {
1664 	{
1665 		.reg = 0x100,
1666 		.num_ports	= 2,
1667 		.clkout_ctl	= { 0x108, 4, 4, 1, 0 },
1668 		.port_cfgs	= {
1669 			[USB2PHY_PORT_OTG] = {
1670 				.phy_sus	= { 0x0100, 15, 0, 0, 0x1d1 },
1671 				.bvalid_det_en	= { 0x0680, 3, 3, 0, 1 },
1672 				.bvalid_det_st	= { 0x0690, 3, 3, 0, 1 },
1673 				.bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 },
1674 				.ls_det_en	= { 0x0680, 2, 2, 0, 1 },
1675 				.ls_det_st	= { 0x0690, 2, 2, 0, 1 },
1676 				.ls_det_clr	= { 0x06a0, 2, 2, 0, 1 },
1677 				.utmi_bvalid	= { 0x0804, 10, 10, 0, 1 },
1678 				.utmi_ls	= { 0x0804, 13, 12, 0, 1 },
1679 			},
1680 			[USB2PHY_PORT_HOST] = {
1681 				.phy_sus	= { 0x0104, 15, 0, 0, 0x1d1 },
1682 				.ls_det_en	= { 0x0680, 4, 4, 0, 1 },
1683 				.ls_det_st	= { 0x0690, 4, 4, 0, 1 },
1684 				.ls_det_clr	= { 0x06a0, 4, 4, 0, 1 },
1685 				.utmi_ls	= { 0x0804, 9, 8, 0, 1 },
1686 				.utmi_hstdet	= { 0x0804, 7, 7, 0, 1 }
1687 			}
1688 		},
1689 		.chg_det = {
1690 			.opmode		= { 0x0100, 3, 0, 5, 1 },
1691 			.cp_det		= { 0x0804, 1, 1, 0, 1 },
1692 			.dcp_det	= { 0x0804, 0, 0, 0, 1 },
1693 			.dp_det		= { 0x0804, 2, 2, 0, 1 },
1694 			.idm_sink_en	= { 0x0108, 8, 8, 0, 1 },
1695 			.idp_sink_en	= { 0x0108, 7, 7, 0, 1 },
1696 			.idp_src_en	= { 0x0108, 9, 9, 0, 1 },
1697 			.rdm_pdwn_en	= { 0x0108, 10, 10, 0, 1 },
1698 			.vdm_src_en	= { 0x0108, 12, 12, 0, 1 },
1699 			.vdp_src_en	= { 0x0108, 11, 11, 0, 1 },
1700 		},
1701 	},
1702 	{ /* sentinel */ }
1703 };
1704 
1705 static const struct of_device_id rockchip_usb2phy_dt_match[] = {
1706 	{ .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs },
1707 	{ .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs },
1708 	{ .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs },
1709 	{ .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs },
1710 	{ .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs },
1711 	{ .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs },
1712 	{ .compatible = "rockchip,rk3568-usb2phy", .data = &rk3568_phy_cfgs },
1713 	{ .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs },
1714 	{}
1715 };
1716 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match);
1717 
1718 static struct platform_driver rockchip_usb2phy_driver = {
1719 	.probe		= rockchip_usb2phy_probe,
1720 	.driver		= {
1721 		.name	= "rockchip-usb2phy",
1722 		.of_match_table = rockchip_usb2phy_dt_match,
1723 	},
1724 };
1725 module_platform_driver(rockchip_usb2phy_driver);
1726 
1727 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>");
1728 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver");
1729 MODULE_LICENSE("GPL v2");
1730