1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Rockchip USB2.0 PHY with Innosilicon IP block driver 4 * 5 * Copyright (C) 2016 Fuzhou Rockchip Electronics Co., Ltd 6 */ 7 8 #include <linux/clk.h> 9 #include <linux/clk-provider.h> 10 #include <linux/delay.h> 11 #include <linux/extcon-provider.h> 12 #include <linux/interrupt.h> 13 #include <linux/io.h> 14 #include <linux/gpio/consumer.h> 15 #include <linux/jiffies.h> 16 #include <linux/kernel.h> 17 #include <linux/module.h> 18 #include <linux/mutex.h> 19 #include <linux/of.h> 20 #include <linux/of_address.h> 21 #include <linux/of_irq.h> 22 #include <linux/of_platform.h> 23 #include <linux/phy/phy.h> 24 #include <linux/platform_device.h> 25 #include <linux/power_supply.h> 26 #include <linux/regmap.h> 27 #include <linux/mfd/syscon.h> 28 #include <linux/usb/of.h> 29 #include <linux/usb/otg.h> 30 31 #define BIT_WRITEABLE_SHIFT 16 32 #define SCHEDULE_DELAY (60 * HZ) 33 #define OTG_SCHEDULE_DELAY (2 * HZ) 34 35 enum rockchip_usb2phy_port_id { 36 USB2PHY_PORT_OTG, 37 USB2PHY_PORT_HOST, 38 USB2PHY_NUM_PORTS, 39 }; 40 41 enum rockchip_usb2phy_host_state { 42 PHY_STATE_HS_ONLINE = 0, 43 PHY_STATE_DISCONNECT = 1, 44 PHY_STATE_CONNECT = 2, 45 PHY_STATE_FS_LS_ONLINE = 4, 46 }; 47 48 /** 49 * enum usb_chg_state - Different states involved in USB charger detection. 50 * @USB_CHG_STATE_UNDEFINED: USB charger is not connected or detection 51 * process is not yet started. 52 * @USB_CHG_STATE_WAIT_FOR_DCD: Waiting for Data pins contact. 53 * @USB_CHG_STATE_DCD_DONE: Data pin contact is detected. 54 * @USB_CHG_STATE_PRIMARY_DONE: Primary detection is completed (Detects 55 * between SDP and DCP/CDP). 56 * @USB_CHG_STATE_SECONDARY_DONE: Secondary detection is completed (Detects 57 * between DCP and CDP). 58 * @USB_CHG_STATE_DETECTED: USB charger type is determined. 59 */ 60 enum usb_chg_state { 61 USB_CHG_STATE_UNDEFINED = 0, 62 USB_CHG_STATE_WAIT_FOR_DCD, 63 USB_CHG_STATE_DCD_DONE, 64 USB_CHG_STATE_PRIMARY_DONE, 65 USB_CHG_STATE_SECONDARY_DONE, 66 USB_CHG_STATE_DETECTED, 67 }; 68 69 static const unsigned int rockchip_usb2phy_extcon_cable[] = { 70 EXTCON_USB, 71 EXTCON_USB_HOST, 72 EXTCON_CHG_USB_SDP, 73 EXTCON_CHG_USB_CDP, 74 EXTCON_CHG_USB_DCP, 75 EXTCON_CHG_USB_SLOW, 76 EXTCON_NONE, 77 }; 78 79 struct usb2phy_reg { 80 unsigned int offset; 81 unsigned int bitend; 82 unsigned int bitstart; 83 unsigned int disable; 84 unsigned int enable; 85 }; 86 87 /** 88 * struct rockchip_chg_det_reg - usb charger detect registers 89 * @cp_det: charging port detected successfully. 90 * @dcp_det: dedicated charging port detected successfully. 91 * @dp_det: assert data pin connect successfully. 92 * @idm_sink_en: open dm sink curren. 93 * @idp_sink_en: open dp sink current. 94 * @idp_src_en: open dm source current. 95 * @rdm_pdwn_en: open dm pull down resistor. 96 * @vdm_src_en: open dm voltage source. 97 * @vdp_src_en: open dp voltage source. 98 * @opmode: utmi operational mode. 99 */ 100 struct rockchip_chg_det_reg { 101 struct usb2phy_reg cp_det; 102 struct usb2phy_reg dcp_det; 103 struct usb2phy_reg dp_det; 104 struct usb2phy_reg idm_sink_en; 105 struct usb2phy_reg idp_sink_en; 106 struct usb2phy_reg idp_src_en; 107 struct usb2phy_reg rdm_pdwn_en; 108 struct usb2phy_reg vdm_src_en; 109 struct usb2phy_reg vdp_src_en; 110 struct usb2phy_reg opmode; 111 }; 112 113 /** 114 * struct rockchip_usb2phy_port_cfg - usb-phy port configuration. 115 * @phy_sus: phy suspend register. 116 * @bvalid_det_en: vbus valid rise detection enable register. 117 * @bvalid_det_st: vbus valid rise detection status register. 118 * @bvalid_det_clr: vbus valid rise detection clear register. 119 * @ls_det_en: linestate detection enable register. 120 * @ls_det_st: linestate detection state register. 121 * @ls_det_clr: linestate detection clear register. 122 * @utmi_avalid: utmi vbus avalid status register. 123 * @utmi_bvalid: utmi vbus bvalid status register. 124 * @utmi_ls: utmi linestate state register. 125 * @utmi_hstdet: utmi host disconnect register. 126 */ 127 struct rockchip_usb2phy_port_cfg { 128 struct usb2phy_reg phy_sus; 129 struct usb2phy_reg bvalid_det_en; 130 struct usb2phy_reg bvalid_det_st; 131 struct usb2phy_reg bvalid_det_clr; 132 struct usb2phy_reg ls_det_en; 133 struct usb2phy_reg ls_det_st; 134 struct usb2phy_reg ls_det_clr; 135 struct usb2phy_reg utmi_avalid; 136 struct usb2phy_reg utmi_bvalid; 137 struct usb2phy_reg utmi_ls; 138 struct usb2phy_reg utmi_hstdet; 139 }; 140 141 /** 142 * struct rockchip_usb2phy_cfg - usb-phy configuration. 143 * @reg: the address offset of grf for usb-phy config. 144 * @num_ports: specify how many ports that the phy has. 145 * @clkout_ctl: keep on/turn off output clk of phy. 146 * @port_cfgs: usb-phy port configurations. 147 * @chg_det: charger detection registers. 148 */ 149 struct rockchip_usb2phy_cfg { 150 unsigned int reg; 151 unsigned int num_ports; 152 struct usb2phy_reg clkout_ctl; 153 const struct rockchip_usb2phy_port_cfg port_cfgs[USB2PHY_NUM_PORTS]; 154 const struct rockchip_chg_det_reg chg_det; 155 }; 156 157 /** 158 * struct rockchip_usb2phy_port - usb-phy port data. 159 * @phy: generic phy. 160 * @port_id: flag for otg port or host port. 161 * @suspended: phy suspended flag. 162 * @vbus_attached: otg device vbus status. 163 * @bvalid_irq: IRQ number assigned for vbus valid rise detection. 164 * @ls_irq: IRQ number assigned for linestate detection. 165 * @otg_mux_irq: IRQ number which multiplex otg-id/otg-bvalid/linestate 166 * irqs to one irq in otg-port. 167 * @mutex: for register updating in sm_work. 168 * @chg_work: charge detect work. 169 * @otg_sm_work: OTG state machine work. 170 * @sm_work: HOST state machine work. 171 * @port_cfg: port register configuration, assigned by driver data. 172 * @event_nb: hold event notification callback. 173 * @state: define OTG enumeration states before device reset. 174 * @mode: the dr_mode of the controller. 175 */ 176 struct rockchip_usb2phy_port { 177 struct phy *phy; 178 unsigned int port_id; 179 bool suspended; 180 bool vbus_attached; 181 int bvalid_irq; 182 int ls_irq; 183 int otg_mux_irq; 184 struct mutex mutex; 185 struct delayed_work chg_work; 186 struct delayed_work otg_sm_work; 187 struct delayed_work sm_work; 188 const struct rockchip_usb2phy_port_cfg *port_cfg; 189 struct notifier_block event_nb; 190 enum usb_otg_state state; 191 enum usb_dr_mode mode; 192 }; 193 194 /** 195 * struct rockchip_usb2phy - usb2.0 phy driver data. 196 * @dev: pointer to device. 197 * @grf: General Register Files regmap. 198 * @usbgrf: USB General Register Files regmap. 199 * @clk: clock struct of phy input clk. 200 * @clk480m: clock struct of phy output clk. 201 * @clk480m_hw: clock struct of phy output clk management. 202 * @chg_state: states involved in USB charger detection. 203 * @chg_type: USB charger types. 204 * @dcd_retries: The retry count used to track Data contact 205 * detection process. 206 * @edev: extcon device for notification registration 207 * @phy_cfg: phy register configuration, assigned by driver data. 208 * @ports: phy port instance. 209 */ 210 struct rockchip_usb2phy { 211 struct device *dev; 212 struct regmap *grf; 213 struct regmap *usbgrf; 214 struct clk *clk; 215 struct clk *clk480m; 216 struct clk_hw clk480m_hw; 217 enum usb_chg_state chg_state; 218 enum power_supply_type chg_type; 219 u8 dcd_retries; 220 struct extcon_dev *edev; 221 const struct rockchip_usb2phy_cfg *phy_cfg; 222 struct rockchip_usb2phy_port ports[USB2PHY_NUM_PORTS]; 223 }; 224 225 static inline struct regmap *get_reg_base(struct rockchip_usb2phy *rphy) 226 { 227 return rphy->usbgrf == NULL ? rphy->grf : rphy->usbgrf; 228 } 229 230 static inline int property_enable(struct regmap *base, 231 const struct usb2phy_reg *reg, bool en) 232 { 233 unsigned int val, mask, tmp; 234 235 tmp = en ? reg->enable : reg->disable; 236 mask = GENMASK(reg->bitend, reg->bitstart); 237 val = (tmp << reg->bitstart) | (mask << BIT_WRITEABLE_SHIFT); 238 239 return regmap_write(base, reg->offset, val); 240 } 241 242 static inline bool property_enabled(struct regmap *base, 243 const struct usb2phy_reg *reg) 244 { 245 int ret; 246 unsigned int tmp, orig; 247 unsigned int mask = GENMASK(reg->bitend, reg->bitstart); 248 249 ret = regmap_read(base, reg->offset, &orig); 250 if (ret) 251 return false; 252 253 tmp = (orig & mask) >> reg->bitstart; 254 return tmp == reg->enable; 255 } 256 257 static int rockchip_usb2phy_clk480m_prepare(struct clk_hw *hw) 258 { 259 struct rockchip_usb2phy *rphy = 260 container_of(hw, struct rockchip_usb2phy, clk480m_hw); 261 struct regmap *base = get_reg_base(rphy); 262 int ret; 263 264 /* turn on 480m clk output if it is off */ 265 if (!property_enabled(base, &rphy->phy_cfg->clkout_ctl)) { 266 ret = property_enable(base, &rphy->phy_cfg->clkout_ctl, true); 267 if (ret) 268 return ret; 269 270 /* waiting for the clk become stable */ 271 usleep_range(1200, 1300); 272 } 273 274 return 0; 275 } 276 277 static void rockchip_usb2phy_clk480m_unprepare(struct clk_hw *hw) 278 { 279 struct rockchip_usb2phy *rphy = 280 container_of(hw, struct rockchip_usb2phy, clk480m_hw); 281 struct regmap *base = get_reg_base(rphy); 282 283 /* turn off 480m clk output */ 284 property_enable(base, &rphy->phy_cfg->clkout_ctl, false); 285 } 286 287 static int rockchip_usb2phy_clk480m_prepared(struct clk_hw *hw) 288 { 289 struct rockchip_usb2phy *rphy = 290 container_of(hw, struct rockchip_usb2phy, clk480m_hw); 291 struct regmap *base = get_reg_base(rphy); 292 293 return property_enabled(base, &rphy->phy_cfg->clkout_ctl); 294 } 295 296 static unsigned long 297 rockchip_usb2phy_clk480m_recalc_rate(struct clk_hw *hw, 298 unsigned long parent_rate) 299 { 300 return 480000000; 301 } 302 303 static const struct clk_ops rockchip_usb2phy_clkout_ops = { 304 .prepare = rockchip_usb2phy_clk480m_prepare, 305 .unprepare = rockchip_usb2phy_clk480m_unprepare, 306 .is_prepared = rockchip_usb2phy_clk480m_prepared, 307 .recalc_rate = rockchip_usb2phy_clk480m_recalc_rate, 308 }; 309 310 static void rockchip_usb2phy_clk480m_unregister(void *data) 311 { 312 struct rockchip_usb2phy *rphy = data; 313 314 of_clk_del_provider(rphy->dev->of_node); 315 clk_unregister(rphy->clk480m); 316 } 317 318 static int 319 rockchip_usb2phy_clk480m_register(struct rockchip_usb2phy *rphy) 320 { 321 struct device_node *node = rphy->dev->of_node; 322 struct clk_init_data init; 323 const char *clk_name; 324 int ret = 0; 325 326 init.flags = 0; 327 init.name = "clk_usbphy_480m"; 328 init.ops = &rockchip_usb2phy_clkout_ops; 329 330 /* optional override of the clockname */ 331 of_property_read_string(node, "clock-output-names", &init.name); 332 333 if (rphy->clk) { 334 clk_name = __clk_get_name(rphy->clk); 335 init.parent_names = &clk_name; 336 init.num_parents = 1; 337 } else { 338 init.parent_names = NULL; 339 init.num_parents = 0; 340 } 341 342 rphy->clk480m_hw.init = &init; 343 344 /* register the clock */ 345 rphy->clk480m = clk_register(rphy->dev, &rphy->clk480m_hw); 346 if (IS_ERR(rphy->clk480m)) { 347 ret = PTR_ERR(rphy->clk480m); 348 goto err_ret; 349 } 350 351 ret = of_clk_add_provider(node, of_clk_src_simple_get, rphy->clk480m); 352 if (ret < 0) 353 goto err_clk_provider; 354 355 return devm_add_action_or_reset(rphy->dev, rockchip_usb2phy_clk480m_unregister, rphy); 356 357 err_clk_provider: 358 clk_unregister(rphy->clk480m); 359 err_ret: 360 return ret; 361 } 362 363 static int rockchip_usb2phy_extcon_register(struct rockchip_usb2phy *rphy) 364 { 365 int ret; 366 struct device_node *node = rphy->dev->of_node; 367 struct extcon_dev *edev; 368 369 if (of_property_read_bool(node, "extcon")) { 370 edev = extcon_get_edev_by_phandle(rphy->dev, 0); 371 if (IS_ERR(edev)) { 372 if (PTR_ERR(edev) != -EPROBE_DEFER) 373 dev_err(rphy->dev, "Invalid or missing extcon\n"); 374 return PTR_ERR(edev); 375 } 376 } else { 377 /* Initialize extcon device */ 378 edev = devm_extcon_dev_allocate(rphy->dev, 379 rockchip_usb2phy_extcon_cable); 380 381 if (IS_ERR(edev)) 382 return -ENOMEM; 383 384 ret = devm_extcon_dev_register(rphy->dev, edev); 385 if (ret) { 386 dev_err(rphy->dev, "failed to register extcon device\n"); 387 return ret; 388 } 389 } 390 391 rphy->edev = edev; 392 393 return 0; 394 } 395 396 static int rockchip_usb2phy_init(struct phy *phy) 397 { 398 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 399 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); 400 int ret = 0; 401 402 mutex_lock(&rport->mutex); 403 404 if (rport->port_id == USB2PHY_PORT_OTG) { 405 if (rport->mode != USB_DR_MODE_HOST && 406 rport->mode != USB_DR_MODE_UNKNOWN) { 407 /* clear bvalid status and enable bvalid detect irq */ 408 ret = property_enable(rphy->grf, 409 &rport->port_cfg->bvalid_det_clr, 410 true); 411 if (ret) 412 goto out; 413 414 ret = property_enable(rphy->grf, 415 &rport->port_cfg->bvalid_det_en, 416 true); 417 if (ret) 418 goto out; 419 420 schedule_delayed_work(&rport->otg_sm_work, 421 OTG_SCHEDULE_DELAY * 3); 422 } else { 423 /* If OTG works in host only mode, do nothing. */ 424 dev_dbg(&rport->phy->dev, "mode %d\n", rport->mode); 425 } 426 } else if (rport->port_id == USB2PHY_PORT_HOST) { 427 /* clear linestate and enable linestate detect irq */ 428 ret = property_enable(rphy->grf, 429 &rport->port_cfg->ls_det_clr, true); 430 if (ret) 431 goto out; 432 433 ret = property_enable(rphy->grf, 434 &rport->port_cfg->ls_det_en, true); 435 if (ret) 436 goto out; 437 438 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY); 439 } 440 441 out: 442 mutex_unlock(&rport->mutex); 443 return ret; 444 } 445 446 static int rockchip_usb2phy_power_on(struct phy *phy) 447 { 448 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 449 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); 450 struct regmap *base = get_reg_base(rphy); 451 int ret; 452 453 dev_dbg(&rport->phy->dev, "port power on\n"); 454 455 if (!rport->suspended) 456 return 0; 457 458 ret = clk_prepare_enable(rphy->clk480m); 459 if (ret) 460 return ret; 461 462 ret = property_enable(base, &rport->port_cfg->phy_sus, false); 463 if (ret) 464 return ret; 465 466 /* waiting for the utmi_clk to become stable */ 467 usleep_range(1500, 2000); 468 469 rport->suspended = false; 470 return 0; 471 } 472 473 static int rockchip_usb2phy_power_off(struct phy *phy) 474 { 475 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 476 struct rockchip_usb2phy *rphy = dev_get_drvdata(phy->dev.parent); 477 struct regmap *base = get_reg_base(rphy); 478 int ret; 479 480 dev_dbg(&rport->phy->dev, "port power off\n"); 481 482 if (rport->suspended) 483 return 0; 484 485 ret = property_enable(base, &rport->port_cfg->phy_sus, true); 486 if (ret) 487 return ret; 488 489 rport->suspended = true; 490 clk_disable_unprepare(rphy->clk480m); 491 492 return 0; 493 } 494 495 static int rockchip_usb2phy_exit(struct phy *phy) 496 { 497 struct rockchip_usb2phy_port *rport = phy_get_drvdata(phy); 498 499 if (rport->port_id == USB2PHY_PORT_OTG && 500 rport->mode != USB_DR_MODE_HOST && 501 rport->mode != USB_DR_MODE_UNKNOWN) { 502 cancel_delayed_work_sync(&rport->otg_sm_work); 503 cancel_delayed_work_sync(&rport->chg_work); 504 } else if (rport->port_id == USB2PHY_PORT_HOST) 505 cancel_delayed_work_sync(&rport->sm_work); 506 507 return 0; 508 } 509 510 static const struct phy_ops rockchip_usb2phy_ops = { 511 .init = rockchip_usb2phy_init, 512 .exit = rockchip_usb2phy_exit, 513 .power_on = rockchip_usb2phy_power_on, 514 .power_off = rockchip_usb2phy_power_off, 515 .owner = THIS_MODULE, 516 }; 517 518 static void rockchip_usb2phy_otg_sm_work(struct work_struct *work) 519 { 520 struct rockchip_usb2phy_port *rport = 521 container_of(work, struct rockchip_usb2phy_port, 522 otg_sm_work.work); 523 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 524 static unsigned int cable; 525 unsigned long delay; 526 bool vbus_attach, sch_work, notify_charger; 527 528 vbus_attach = property_enabled(rphy->grf, 529 &rport->port_cfg->utmi_bvalid); 530 531 sch_work = false; 532 notify_charger = false; 533 delay = OTG_SCHEDULE_DELAY; 534 dev_dbg(&rport->phy->dev, "%s otg sm work\n", 535 usb_otg_state_string(rport->state)); 536 537 switch (rport->state) { 538 case OTG_STATE_UNDEFINED: 539 rport->state = OTG_STATE_B_IDLE; 540 if (!vbus_attach) 541 rockchip_usb2phy_power_off(rport->phy); 542 fallthrough; 543 case OTG_STATE_B_IDLE: 544 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) > 0) { 545 dev_dbg(&rport->phy->dev, "usb otg host connect\n"); 546 rport->state = OTG_STATE_A_HOST; 547 rockchip_usb2phy_power_on(rport->phy); 548 return; 549 } else if (vbus_attach) { 550 dev_dbg(&rport->phy->dev, "vbus_attach\n"); 551 switch (rphy->chg_state) { 552 case USB_CHG_STATE_UNDEFINED: 553 schedule_delayed_work(&rport->chg_work, 0); 554 return; 555 case USB_CHG_STATE_DETECTED: 556 switch (rphy->chg_type) { 557 case POWER_SUPPLY_TYPE_USB: 558 dev_dbg(&rport->phy->dev, "sdp cable is connected\n"); 559 rockchip_usb2phy_power_on(rport->phy); 560 rport->state = OTG_STATE_B_PERIPHERAL; 561 notify_charger = true; 562 sch_work = true; 563 cable = EXTCON_CHG_USB_SDP; 564 break; 565 case POWER_SUPPLY_TYPE_USB_DCP: 566 dev_dbg(&rport->phy->dev, "dcp cable is connected\n"); 567 rockchip_usb2phy_power_off(rport->phy); 568 notify_charger = true; 569 sch_work = true; 570 cable = EXTCON_CHG_USB_DCP; 571 break; 572 case POWER_SUPPLY_TYPE_USB_CDP: 573 dev_dbg(&rport->phy->dev, "cdp cable is connected\n"); 574 rockchip_usb2phy_power_on(rport->phy); 575 rport->state = OTG_STATE_B_PERIPHERAL; 576 notify_charger = true; 577 sch_work = true; 578 cable = EXTCON_CHG_USB_CDP; 579 break; 580 default: 581 break; 582 } 583 break; 584 default: 585 break; 586 } 587 } else { 588 notify_charger = true; 589 rphy->chg_state = USB_CHG_STATE_UNDEFINED; 590 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; 591 } 592 593 if (rport->vbus_attached != vbus_attach) { 594 rport->vbus_attached = vbus_attach; 595 596 if (notify_charger && rphy->edev) { 597 extcon_set_state_sync(rphy->edev, 598 cable, vbus_attach); 599 if (cable == EXTCON_CHG_USB_SDP) 600 extcon_set_state_sync(rphy->edev, 601 EXTCON_USB, 602 vbus_attach); 603 } 604 } 605 break; 606 case OTG_STATE_B_PERIPHERAL: 607 if (!vbus_attach) { 608 dev_dbg(&rport->phy->dev, "usb disconnect\n"); 609 rphy->chg_state = USB_CHG_STATE_UNDEFINED; 610 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; 611 rport->state = OTG_STATE_B_IDLE; 612 delay = 0; 613 rockchip_usb2phy_power_off(rport->phy); 614 } 615 sch_work = true; 616 break; 617 case OTG_STATE_A_HOST: 618 if (extcon_get_state(rphy->edev, EXTCON_USB_HOST) == 0) { 619 dev_dbg(&rport->phy->dev, "usb otg host disconnect\n"); 620 rport->state = OTG_STATE_B_IDLE; 621 rockchip_usb2phy_power_off(rport->phy); 622 } 623 break; 624 default: 625 break; 626 } 627 628 if (sch_work) 629 schedule_delayed_work(&rport->otg_sm_work, delay); 630 } 631 632 static const char *chg_to_string(enum power_supply_type chg_type) 633 { 634 switch (chg_type) { 635 case POWER_SUPPLY_TYPE_USB: 636 return "USB_SDP_CHARGER"; 637 case POWER_SUPPLY_TYPE_USB_DCP: 638 return "USB_DCP_CHARGER"; 639 case POWER_SUPPLY_TYPE_USB_CDP: 640 return "USB_CDP_CHARGER"; 641 default: 642 return "INVALID_CHARGER"; 643 } 644 } 645 646 static void rockchip_chg_enable_dcd(struct rockchip_usb2phy *rphy, 647 bool en) 648 { 649 struct regmap *base = get_reg_base(rphy); 650 651 property_enable(base, &rphy->phy_cfg->chg_det.rdm_pdwn_en, en); 652 property_enable(base, &rphy->phy_cfg->chg_det.idp_src_en, en); 653 } 654 655 static void rockchip_chg_enable_primary_det(struct rockchip_usb2phy *rphy, 656 bool en) 657 { 658 struct regmap *base = get_reg_base(rphy); 659 660 property_enable(base, &rphy->phy_cfg->chg_det.vdp_src_en, en); 661 property_enable(base, &rphy->phy_cfg->chg_det.idm_sink_en, en); 662 } 663 664 static void rockchip_chg_enable_secondary_det(struct rockchip_usb2phy *rphy, 665 bool en) 666 { 667 struct regmap *base = get_reg_base(rphy); 668 669 property_enable(base, &rphy->phy_cfg->chg_det.vdm_src_en, en); 670 property_enable(base, &rphy->phy_cfg->chg_det.idp_sink_en, en); 671 } 672 673 #define CHG_DCD_POLL_TIME (100 * HZ / 1000) 674 #define CHG_DCD_MAX_RETRIES 6 675 #define CHG_PRIMARY_DET_TIME (40 * HZ / 1000) 676 #define CHG_SECONDARY_DET_TIME (40 * HZ / 1000) 677 static void rockchip_chg_detect_work(struct work_struct *work) 678 { 679 struct rockchip_usb2phy_port *rport = 680 container_of(work, struct rockchip_usb2phy_port, chg_work.work); 681 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 682 struct regmap *base = get_reg_base(rphy); 683 bool is_dcd, tmout, vout; 684 unsigned long delay; 685 686 dev_dbg(&rport->phy->dev, "chg detection work state = %d\n", 687 rphy->chg_state); 688 switch (rphy->chg_state) { 689 case USB_CHG_STATE_UNDEFINED: 690 if (!rport->suspended) 691 rockchip_usb2phy_power_off(rport->phy); 692 /* put the controller in non-driving mode */ 693 property_enable(base, &rphy->phy_cfg->chg_det.opmode, false); 694 /* Start DCD processing stage 1 */ 695 rockchip_chg_enable_dcd(rphy, true); 696 rphy->chg_state = USB_CHG_STATE_WAIT_FOR_DCD; 697 rphy->dcd_retries = 0; 698 delay = CHG_DCD_POLL_TIME; 699 break; 700 case USB_CHG_STATE_WAIT_FOR_DCD: 701 /* get data contact detection status */ 702 is_dcd = property_enabled(rphy->grf, 703 &rphy->phy_cfg->chg_det.dp_det); 704 tmout = ++rphy->dcd_retries == CHG_DCD_MAX_RETRIES; 705 /* stage 2 */ 706 if (is_dcd || tmout) { 707 /* stage 4 */ 708 /* Turn off DCD circuitry */ 709 rockchip_chg_enable_dcd(rphy, false); 710 /* Voltage Source on DP, Probe on DM */ 711 rockchip_chg_enable_primary_det(rphy, true); 712 delay = CHG_PRIMARY_DET_TIME; 713 rphy->chg_state = USB_CHG_STATE_DCD_DONE; 714 } else { 715 /* stage 3 */ 716 delay = CHG_DCD_POLL_TIME; 717 } 718 break; 719 case USB_CHG_STATE_DCD_DONE: 720 vout = property_enabled(rphy->grf, 721 &rphy->phy_cfg->chg_det.cp_det); 722 rockchip_chg_enable_primary_det(rphy, false); 723 if (vout) { 724 /* Voltage Source on DM, Probe on DP */ 725 rockchip_chg_enable_secondary_det(rphy, true); 726 delay = CHG_SECONDARY_DET_TIME; 727 rphy->chg_state = USB_CHG_STATE_PRIMARY_DONE; 728 } else { 729 if (rphy->dcd_retries == CHG_DCD_MAX_RETRIES) { 730 /* floating charger found */ 731 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP; 732 rphy->chg_state = USB_CHG_STATE_DETECTED; 733 delay = 0; 734 } else { 735 rphy->chg_type = POWER_SUPPLY_TYPE_USB; 736 rphy->chg_state = USB_CHG_STATE_DETECTED; 737 delay = 0; 738 } 739 } 740 break; 741 case USB_CHG_STATE_PRIMARY_DONE: 742 vout = property_enabled(rphy->grf, 743 &rphy->phy_cfg->chg_det.dcp_det); 744 /* Turn off voltage source */ 745 rockchip_chg_enable_secondary_det(rphy, false); 746 if (vout) 747 rphy->chg_type = POWER_SUPPLY_TYPE_USB_DCP; 748 else 749 rphy->chg_type = POWER_SUPPLY_TYPE_USB_CDP; 750 fallthrough; 751 case USB_CHG_STATE_SECONDARY_DONE: 752 rphy->chg_state = USB_CHG_STATE_DETECTED; 753 delay = 0; 754 fallthrough; 755 case USB_CHG_STATE_DETECTED: 756 /* put the controller in normal mode */ 757 property_enable(base, &rphy->phy_cfg->chg_det.opmode, true); 758 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); 759 dev_dbg(&rport->phy->dev, "charger = %s\n", 760 chg_to_string(rphy->chg_type)); 761 return; 762 default: 763 return; 764 } 765 766 schedule_delayed_work(&rport->chg_work, delay); 767 } 768 769 /* 770 * The function manage host-phy port state and suspend/resume phy port 771 * to save power. 772 * 773 * we rely on utmi_linestate and utmi_hostdisconnect to identify whether 774 * devices is disconnect or not. Besides, we do not need care it is FS/LS 775 * disconnected or HS disconnected, actually, we just only need get the 776 * device is disconnected at last through rearm the delayed work, 777 * to suspend the phy port in _PHY_STATE_DISCONNECT_ case. 778 * 779 * NOTE: It may invoke *phy_powr_off or *phy_power_on which will invoke 780 * some clk related APIs, so do not invoke it from interrupt context directly. 781 */ 782 static void rockchip_usb2phy_sm_work(struct work_struct *work) 783 { 784 struct rockchip_usb2phy_port *rport = 785 container_of(work, struct rockchip_usb2phy_port, sm_work.work); 786 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 787 unsigned int sh = rport->port_cfg->utmi_hstdet.bitend - 788 rport->port_cfg->utmi_hstdet.bitstart + 1; 789 unsigned int ul, uhd, state; 790 unsigned int ul_mask, uhd_mask; 791 int ret; 792 793 mutex_lock(&rport->mutex); 794 795 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_ls.offset, &ul); 796 if (ret < 0) 797 goto next_schedule; 798 799 ret = regmap_read(rphy->grf, rport->port_cfg->utmi_hstdet.offset, &uhd); 800 if (ret < 0) 801 goto next_schedule; 802 803 uhd_mask = GENMASK(rport->port_cfg->utmi_hstdet.bitend, 804 rport->port_cfg->utmi_hstdet.bitstart); 805 ul_mask = GENMASK(rport->port_cfg->utmi_ls.bitend, 806 rport->port_cfg->utmi_ls.bitstart); 807 808 /* stitch on utmi_ls and utmi_hstdet as phy state */ 809 state = ((uhd & uhd_mask) >> rport->port_cfg->utmi_hstdet.bitstart) | 810 (((ul & ul_mask) >> rport->port_cfg->utmi_ls.bitstart) << sh); 811 812 switch (state) { 813 case PHY_STATE_HS_ONLINE: 814 dev_dbg(&rport->phy->dev, "HS online\n"); 815 break; 816 case PHY_STATE_FS_LS_ONLINE: 817 /* 818 * For FS/LS device, the online state share with connect state 819 * from utmi_ls and utmi_hstdet register, so we distinguish 820 * them via suspended flag. 821 * 822 * Plus, there are two cases, one is D- Line pull-up, and D+ 823 * line pull-down, the state is 4; another is D+ line pull-up, 824 * and D- line pull-down, the state is 2. 825 */ 826 if (!rport->suspended) { 827 /* D- line pull-up, D+ line pull-down */ 828 dev_dbg(&rport->phy->dev, "FS/LS online\n"); 829 break; 830 } 831 fallthrough; 832 case PHY_STATE_CONNECT: 833 if (rport->suspended) { 834 dev_dbg(&rport->phy->dev, "Connected\n"); 835 rockchip_usb2phy_power_on(rport->phy); 836 rport->suspended = false; 837 } else { 838 /* D+ line pull-up, D- line pull-down */ 839 dev_dbg(&rport->phy->dev, "FS/LS online\n"); 840 } 841 break; 842 case PHY_STATE_DISCONNECT: 843 if (!rport->suspended) { 844 dev_dbg(&rport->phy->dev, "Disconnected\n"); 845 rockchip_usb2phy_power_off(rport->phy); 846 rport->suspended = true; 847 } 848 849 /* 850 * activate the linestate detection to get the next device 851 * plug-in irq. 852 */ 853 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true); 854 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, true); 855 856 /* 857 * we don't need to rearm the delayed work when the phy port 858 * is suspended. 859 */ 860 mutex_unlock(&rport->mutex); 861 return; 862 default: 863 dev_dbg(&rport->phy->dev, "unknown phy state\n"); 864 break; 865 } 866 867 next_schedule: 868 mutex_unlock(&rport->mutex); 869 schedule_delayed_work(&rport->sm_work, SCHEDULE_DELAY); 870 } 871 872 static irqreturn_t rockchip_usb2phy_linestate_irq(int irq, void *data) 873 { 874 struct rockchip_usb2phy_port *rport = data; 875 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 876 877 if (!property_enabled(rphy->grf, &rport->port_cfg->ls_det_st)) 878 return IRQ_NONE; 879 880 mutex_lock(&rport->mutex); 881 882 /* disable linestate detect irq and clear its status */ 883 property_enable(rphy->grf, &rport->port_cfg->ls_det_en, false); 884 property_enable(rphy->grf, &rport->port_cfg->ls_det_clr, true); 885 886 mutex_unlock(&rport->mutex); 887 888 /* 889 * In this case for host phy port, a new device is plugged in, 890 * meanwhile, if the phy port is suspended, we need rearm the work to 891 * resume it and mange its states; otherwise, we do nothing about that. 892 */ 893 if (rport->suspended && rport->port_id == USB2PHY_PORT_HOST) 894 rockchip_usb2phy_sm_work(&rport->sm_work.work); 895 896 return IRQ_HANDLED; 897 } 898 899 static irqreturn_t rockchip_usb2phy_bvalid_irq(int irq, void *data) 900 { 901 struct rockchip_usb2phy_port *rport = data; 902 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 903 904 if (!property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st)) 905 return IRQ_NONE; 906 907 mutex_lock(&rport->mutex); 908 909 /* clear bvalid detect irq pending status */ 910 property_enable(rphy->grf, &rport->port_cfg->bvalid_det_clr, true); 911 912 mutex_unlock(&rport->mutex); 913 914 rockchip_usb2phy_otg_sm_work(&rport->otg_sm_work.work); 915 916 return IRQ_HANDLED; 917 } 918 919 static irqreturn_t rockchip_usb2phy_otg_mux_irq(int irq, void *data) 920 { 921 struct rockchip_usb2phy_port *rport = data; 922 struct rockchip_usb2phy *rphy = dev_get_drvdata(rport->phy->dev.parent); 923 924 if (property_enabled(rphy->grf, &rport->port_cfg->bvalid_det_st)) 925 return rockchip_usb2phy_bvalid_irq(irq, data); 926 else 927 return IRQ_NONE; 928 } 929 930 static int rockchip_usb2phy_host_port_init(struct rockchip_usb2phy *rphy, 931 struct rockchip_usb2phy_port *rport, 932 struct device_node *child_np) 933 { 934 int ret; 935 936 rport->port_id = USB2PHY_PORT_HOST; 937 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_HOST]; 938 rport->suspended = true; 939 940 mutex_init(&rport->mutex); 941 INIT_DELAYED_WORK(&rport->sm_work, rockchip_usb2phy_sm_work); 942 943 rport->ls_irq = of_irq_get_byname(child_np, "linestate"); 944 if (rport->ls_irq < 0) { 945 dev_err(rphy->dev, "no linestate irq provided\n"); 946 return rport->ls_irq; 947 } 948 949 ret = devm_request_threaded_irq(rphy->dev, rport->ls_irq, NULL, 950 rockchip_usb2phy_linestate_irq, 951 IRQF_ONESHOT, 952 "rockchip_usb2phy", rport); 953 if (ret) { 954 dev_err(rphy->dev, "failed to request linestate irq handle\n"); 955 return ret; 956 } 957 958 return 0; 959 } 960 961 static int rockchip_otg_event(struct notifier_block *nb, 962 unsigned long event, void *ptr) 963 { 964 struct rockchip_usb2phy_port *rport = 965 container_of(nb, struct rockchip_usb2phy_port, event_nb); 966 967 schedule_delayed_work(&rport->otg_sm_work, OTG_SCHEDULE_DELAY); 968 969 return NOTIFY_DONE; 970 } 971 972 static int rockchip_usb2phy_otg_port_init(struct rockchip_usb2phy *rphy, 973 struct rockchip_usb2phy_port *rport, 974 struct device_node *child_np) 975 { 976 int ret; 977 978 rport->port_id = USB2PHY_PORT_OTG; 979 rport->port_cfg = &rphy->phy_cfg->port_cfgs[USB2PHY_PORT_OTG]; 980 rport->state = OTG_STATE_UNDEFINED; 981 982 /* 983 * set suspended flag to true, but actually don't 984 * put phy in suspend mode, it aims to enable usb 985 * phy and clock in power_on() called by usb controller 986 * driver during probe. 987 */ 988 rport->suspended = true; 989 rport->vbus_attached = false; 990 991 mutex_init(&rport->mutex); 992 993 rport->mode = of_usb_get_dr_mode_by_phy(child_np, -1); 994 if (rport->mode == USB_DR_MODE_HOST || 995 rport->mode == USB_DR_MODE_UNKNOWN) { 996 ret = 0; 997 goto out; 998 } 999 1000 INIT_DELAYED_WORK(&rport->chg_work, rockchip_chg_detect_work); 1001 INIT_DELAYED_WORK(&rport->otg_sm_work, rockchip_usb2phy_otg_sm_work); 1002 1003 /* 1004 * Some SoCs use one interrupt with otg-id/otg-bvalid/linestate 1005 * interrupts muxed together, so probe the otg-mux interrupt first, 1006 * if not found, then look for the regular interrupts one by one. 1007 */ 1008 rport->otg_mux_irq = of_irq_get_byname(child_np, "otg-mux"); 1009 if (rport->otg_mux_irq > 0) { 1010 ret = devm_request_threaded_irq(rphy->dev, rport->otg_mux_irq, 1011 NULL, 1012 rockchip_usb2phy_otg_mux_irq, 1013 IRQF_ONESHOT, 1014 "rockchip_usb2phy_otg", 1015 rport); 1016 if (ret) { 1017 dev_err(rphy->dev, 1018 "failed to request otg-mux irq handle\n"); 1019 goto out; 1020 } 1021 } else { 1022 rport->bvalid_irq = of_irq_get_byname(child_np, "otg-bvalid"); 1023 if (rport->bvalid_irq < 0) { 1024 dev_err(rphy->dev, "no vbus valid irq provided\n"); 1025 ret = rport->bvalid_irq; 1026 goto out; 1027 } 1028 1029 ret = devm_request_threaded_irq(rphy->dev, rport->bvalid_irq, 1030 NULL, 1031 rockchip_usb2phy_bvalid_irq, 1032 IRQF_ONESHOT, 1033 "rockchip_usb2phy_bvalid", 1034 rport); 1035 if (ret) { 1036 dev_err(rphy->dev, 1037 "failed to request otg-bvalid irq handle\n"); 1038 goto out; 1039 } 1040 } 1041 1042 if (!IS_ERR(rphy->edev)) { 1043 rport->event_nb.notifier_call = rockchip_otg_event; 1044 1045 ret = devm_extcon_register_notifier(rphy->dev, rphy->edev, 1046 EXTCON_USB_HOST, &rport->event_nb); 1047 if (ret) 1048 dev_err(rphy->dev, "register USB HOST notifier failed\n"); 1049 } 1050 1051 out: 1052 return ret; 1053 } 1054 1055 static int rockchip_usb2phy_probe(struct platform_device *pdev) 1056 { 1057 struct device *dev = &pdev->dev; 1058 struct device_node *np = dev->of_node; 1059 struct device_node *child_np; 1060 struct phy_provider *provider; 1061 struct rockchip_usb2phy *rphy; 1062 const struct rockchip_usb2phy_cfg *phy_cfgs; 1063 const struct of_device_id *match; 1064 unsigned int reg; 1065 int index, ret; 1066 1067 rphy = devm_kzalloc(dev, sizeof(*rphy), GFP_KERNEL); 1068 if (!rphy) 1069 return -ENOMEM; 1070 1071 match = of_match_device(dev->driver->of_match_table, dev); 1072 if (!match || !match->data) { 1073 dev_err(dev, "phy configs are not assigned!\n"); 1074 return -EINVAL; 1075 } 1076 1077 if (!dev->parent || !dev->parent->of_node) 1078 return -EINVAL; 1079 1080 rphy->grf = syscon_node_to_regmap(dev->parent->of_node); 1081 if (IS_ERR(rphy->grf)) 1082 return PTR_ERR(rphy->grf); 1083 1084 if (of_device_is_compatible(np, "rockchip,rv1108-usb2phy")) { 1085 rphy->usbgrf = 1086 syscon_regmap_lookup_by_phandle(dev->of_node, 1087 "rockchip,usbgrf"); 1088 if (IS_ERR(rphy->usbgrf)) 1089 return PTR_ERR(rphy->usbgrf); 1090 } else { 1091 rphy->usbgrf = NULL; 1092 } 1093 1094 if (of_property_read_u32(np, "reg", ®)) { 1095 dev_err(dev, "the reg property is not assigned in %pOFn node\n", 1096 np); 1097 return -EINVAL; 1098 } 1099 1100 rphy->dev = dev; 1101 phy_cfgs = match->data; 1102 rphy->chg_state = USB_CHG_STATE_UNDEFINED; 1103 rphy->chg_type = POWER_SUPPLY_TYPE_UNKNOWN; 1104 platform_set_drvdata(pdev, rphy); 1105 1106 ret = rockchip_usb2phy_extcon_register(rphy); 1107 if (ret) 1108 return ret; 1109 1110 /* find out a proper config which can be matched with dt. */ 1111 index = 0; 1112 while (phy_cfgs[index].reg) { 1113 if (phy_cfgs[index].reg == reg) { 1114 rphy->phy_cfg = &phy_cfgs[index]; 1115 break; 1116 } 1117 1118 ++index; 1119 } 1120 1121 if (!rphy->phy_cfg) { 1122 dev_err(dev, "no phy-config can be matched with %pOFn node\n", 1123 np); 1124 return -EINVAL; 1125 } 1126 1127 rphy->clk = of_clk_get_by_name(np, "phyclk"); 1128 if (!IS_ERR(rphy->clk)) { 1129 clk_prepare_enable(rphy->clk); 1130 } else { 1131 dev_info(&pdev->dev, "no phyclk specified\n"); 1132 rphy->clk = NULL; 1133 } 1134 1135 ret = rockchip_usb2phy_clk480m_register(rphy); 1136 if (ret) { 1137 dev_err(dev, "failed to register 480m output clock\n"); 1138 goto disable_clks; 1139 } 1140 1141 index = 0; 1142 for_each_available_child_of_node(np, child_np) { 1143 struct rockchip_usb2phy_port *rport = &rphy->ports[index]; 1144 struct phy *phy; 1145 1146 /* This driver aims to support both otg-port and host-port */ 1147 if (!of_node_name_eq(child_np, "host-port") && 1148 !of_node_name_eq(child_np, "otg-port")) 1149 goto next_child; 1150 1151 phy = devm_phy_create(dev, child_np, &rockchip_usb2phy_ops); 1152 if (IS_ERR(phy)) { 1153 dev_err(dev, "failed to create phy\n"); 1154 ret = PTR_ERR(phy); 1155 goto put_child; 1156 } 1157 1158 rport->phy = phy; 1159 phy_set_drvdata(rport->phy, rport); 1160 1161 /* initialize otg/host port separately */ 1162 if (of_node_name_eq(child_np, "host-port")) { 1163 ret = rockchip_usb2phy_host_port_init(rphy, rport, 1164 child_np); 1165 if (ret) 1166 goto put_child; 1167 } else { 1168 ret = rockchip_usb2phy_otg_port_init(rphy, rport, 1169 child_np); 1170 if (ret) 1171 goto put_child; 1172 } 1173 1174 next_child: 1175 /* to prevent out of boundary */ 1176 if (++index >= rphy->phy_cfg->num_ports) { 1177 of_node_put(child_np); 1178 break; 1179 } 1180 } 1181 1182 provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1183 return PTR_ERR_OR_ZERO(provider); 1184 1185 put_child: 1186 of_node_put(child_np); 1187 disable_clks: 1188 if (rphy->clk) { 1189 clk_disable_unprepare(rphy->clk); 1190 clk_put(rphy->clk); 1191 } 1192 return ret; 1193 } 1194 1195 static const struct rockchip_usb2phy_cfg rk3228_phy_cfgs[] = { 1196 { 1197 .reg = 0x760, 1198 .num_ports = 2, 1199 .clkout_ctl = { 0x0768, 4, 4, 1, 0 }, 1200 .port_cfgs = { 1201 [USB2PHY_PORT_OTG] = { 1202 .phy_sus = { 0x0760, 15, 0, 0, 0x1d1 }, 1203 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1204 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1205 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1206 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1207 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1208 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1209 .utmi_bvalid = { 0x0480, 4, 4, 0, 1 }, 1210 .utmi_ls = { 0x0480, 3, 2, 0, 1 }, 1211 }, 1212 [USB2PHY_PORT_HOST] = { 1213 .phy_sus = { 0x0764, 15, 0, 0, 0x1d1 }, 1214 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1215 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1216 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 } 1217 } 1218 }, 1219 .chg_det = { 1220 .opmode = { 0x0760, 3, 0, 5, 1 }, 1221 .cp_det = { 0x0884, 4, 4, 0, 1 }, 1222 .dcp_det = { 0x0884, 3, 3, 0, 1 }, 1223 .dp_det = { 0x0884, 5, 5, 0, 1 }, 1224 .idm_sink_en = { 0x0768, 8, 8, 0, 1 }, 1225 .idp_sink_en = { 0x0768, 7, 7, 0, 1 }, 1226 .idp_src_en = { 0x0768, 9, 9, 0, 1 }, 1227 .rdm_pdwn_en = { 0x0768, 10, 10, 0, 1 }, 1228 .vdm_src_en = { 0x0768, 12, 12, 0, 1 }, 1229 .vdp_src_en = { 0x0768, 11, 11, 0, 1 }, 1230 }, 1231 }, 1232 { 1233 .reg = 0x800, 1234 .num_ports = 2, 1235 .clkout_ctl = { 0x0808, 4, 4, 1, 0 }, 1236 .port_cfgs = { 1237 [USB2PHY_PORT_OTG] = { 1238 .phy_sus = { 0x800, 15, 0, 0, 0x1d1 }, 1239 .ls_det_en = { 0x0684, 0, 0, 0, 1 }, 1240 .ls_det_st = { 0x0694, 0, 0, 0, 1 }, 1241 .ls_det_clr = { 0x06a4, 0, 0, 0, 1 } 1242 }, 1243 [USB2PHY_PORT_HOST] = { 1244 .phy_sus = { 0x804, 15, 0, 0, 0x1d1 }, 1245 .ls_det_en = { 0x0684, 1, 1, 0, 1 }, 1246 .ls_det_st = { 0x0694, 1, 1, 0, 1 }, 1247 .ls_det_clr = { 0x06a4, 1, 1, 0, 1 } 1248 } 1249 }, 1250 }, 1251 { /* sentinel */ } 1252 }; 1253 1254 static const struct rockchip_usb2phy_cfg rk3308_phy_cfgs[] = { 1255 { 1256 .reg = 0x100, 1257 .num_ports = 2, 1258 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1259 .port_cfgs = { 1260 [USB2PHY_PORT_OTG] = { 1261 .phy_sus = { 0x0100, 8, 0, 0, 0x1d1 }, 1262 .bvalid_det_en = { 0x3020, 2, 2, 0, 1 }, 1263 .bvalid_det_st = { 0x3024, 2, 2, 0, 1 }, 1264 .bvalid_det_clr = { 0x3028, 2, 2, 0, 1 }, 1265 .ls_det_en = { 0x3020, 0, 0, 0, 1 }, 1266 .ls_det_st = { 0x3024, 0, 0, 0, 1 }, 1267 .ls_det_clr = { 0x3028, 0, 0, 0, 1 }, 1268 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1269 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1270 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1271 }, 1272 [USB2PHY_PORT_HOST] = { 1273 .phy_sus = { 0x0104, 8, 0, 0, 0x1d1 }, 1274 .ls_det_en = { 0x3020, 1, 1, 0, 1 }, 1275 .ls_det_st = { 0x3024, 1, 1, 0, 1 }, 1276 .ls_det_clr = { 0x3028, 1, 1, 0, 1 }, 1277 .utmi_ls = { 0x0120, 17, 16, 0, 1 }, 1278 .utmi_hstdet = { 0x0120, 19, 19, 0, 1 } 1279 } 1280 }, 1281 .chg_det = { 1282 .opmode = { 0x0100, 3, 0, 5, 1 }, 1283 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1284 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1285 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1286 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1287 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1288 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1289 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1290 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1291 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1292 }, 1293 }, 1294 { /* sentinel */ } 1295 }; 1296 1297 static const struct rockchip_usb2phy_cfg rk3328_phy_cfgs[] = { 1298 { 1299 .reg = 0x100, 1300 .num_ports = 2, 1301 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1302 .port_cfgs = { 1303 [USB2PHY_PORT_OTG] = { 1304 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 }, 1305 .bvalid_det_en = { 0x0110, 2, 2, 0, 1 }, 1306 .bvalid_det_st = { 0x0114, 2, 2, 0, 1 }, 1307 .bvalid_det_clr = { 0x0118, 2, 2, 0, 1 }, 1308 .ls_det_en = { 0x0110, 0, 0, 0, 1 }, 1309 .ls_det_st = { 0x0114, 0, 0, 0, 1 }, 1310 .ls_det_clr = { 0x0118, 0, 0, 0, 1 }, 1311 .utmi_avalid = { 0x0120, 10, 10, 0, 1 }, 1312 .utmi_bvalid = { 0x0120, 9, 9, 0, 1 }, 1313 .utmi_ls = { 0x0120, 5, 4, 0, 1 }, 1314 }, 1315 [USB2PHY_PORT_HOST] = { 1316 .phy_sus = { 0x104, 15, 0, 0, 0x1d1 }, 1317 .ls_det_en = { 0x110, 1, 1, 0, 1 }, 1318 .ls_det_st = { 0x114, 1, 1, 0, 1 }, 1319 .ls_det_clr = { 0x118, 1, 1, 0, 1 }, 1320 .utmi_ls = { 0x120, 17, 16, 0, 1 }, 1321 .utmi_hstdet = { 0x120, 19, 19, 0, 1 } 1322 } 1323 }, 1324 .chg_det = { 1325 .opmode = { 0x0100, 3, 0, 5, 1 }, 1326 .cp_det = { 0x0120, 24, 24, 0, 1 }, 1327 .dcp_det = { 0x0120, 23, 23, 0, 1 }, 1328 .dp_det = { 0x0120, 25, 25, 0, 1 }, 1329 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1330 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1331 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1332 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1333 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1334 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1335 }, 1336 }, 1337 { /* sentinel */ } 1338 }; 1339 1340 static const struct rockchip_usb2phy_cfg rk3366_phy_cfgs[] = { 1341 { 1342 .reg = 0x700, 1343 .num_ports = 2, 1344 .clkout_ctl = { 0x0724, 15, 15, 1, 0 }, 1345 .port_cfgs = { 1346 [USB2PHY_PORT_HOST] = { 1347 .phy_sus = { 0x0728, 15, 0, 0, 0x1d1 }, 1348 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1349 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1350 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1351 .utmi_ls = { 0x049c, 14, 13, 0, 1 }, 1352 .utmi_hstdet = { 0x049c, 12, 12, 0, 1 } 1353 } 1354 }, 1355 }, 1356 { /* sentinel */ } 1357 }; 1358 1359 static const struct rockchip_usb2phy_cfg rk3399_phy_cfgs[] = { 1360 { 1361 .reg = 0xe450, 1362 .num_ports = 2, 1363 .clkout_ctl = { 0xe450, 4, 4, 1, 0 }, 1364 .port_cfgs = { 1365 [USB2PHY_PORT_OTG] = { 1366 .phy_sus = { 0xe454, 1, 0, 2, 1 }, 1367 .bvalid_det_en = { 0xe3c0, 3, 3, 0, 1 }, 1368 .bvalid_det_st = { 0xe3e0, 3, 3, 0, 1 }, 1369 .bvalid_det_clr = { 0xe3d0, 3, 3, 0, 1 }, 1370 .utmi_avalid = { 0xe2ac, 7, 7, 0, 1 }, 1371 .utmi_bvalid = { 0xe2ac, 12, 12, 0, 1 }, 1372 }, 1373 [USB2PHY_PORT_HOST] = { 1374 .phy_sus = { 0xe458, 1, 0, 0x2, 0x1 }, 1375 .ls_det_en = { 0xe3c0, 6, 6, 0, 1 }, 1376 .ls_det_st = { 0xe3e0, 6, 6, 0, 1 }, 1377 .ls_det_clr = { 0xe3d0, 6, 6, 0, 1 }, 1378 .utmi_ls = { 0xe2ac, 22, 21, 0, 1 }, 1379 .utmi_hstdet = { 0xe2ac, 23, 23, 0, 1 } 1380 } 1381 }, 1382 .chg_det = { 1383 .opmode = { 0xe454, 3, 0, 5, 1 }, 1384 .cp_det = { 0xe2ac, 2, 2, 0, 1 }, 1385 .dcp_det = { 0xe2ac, 1, 1, 0, 1 }, 1386 .dp_det = { 0xe2ac, 0, 0, 0, 1 }, 1387 .idm_sink_en = { 0xe450, 8, 8, 0, 1 }, 1388 .idp_sink_en = { 0xe450, 7, 7, 0, 1 }, 1389 .idp_src_en = { 0xe450, 9, 9, 0, 1 }, 1390 .rdm_pdwn_en = { 0xe450, 10, 10, 0, 1 }, 1391 .vdm_src_en = { 0xe450, 12, 12, 0, 1 }, 1392 .vdp_src_en = { 0xe450, 11, 11, 0, 1 }, 1393 }, 1394 }, 1395 { 1396 .reg = 0xe460, 1397 .num_ports = 2, 1398 .clkout_ctl = { 0xe460, 4, 4, 1, 0 }, 1399 .port_cfgs = { 1400 [USB2PHY_PORT_OTG] = { 1401 .phy_sus = { 0xe464, 1, 0, 2, 1 }, 1402 .bvalid_det_en = { 0xe3c0, 8, 8, 0, 1 }, 1403 .bvalid_det_st = { 0xe3e0, 8, 8, 0, 1 }, 1404 .bvalid_det_clr = { 0xe3d0, 8, 8, 0, 1 }, 1405 .utmi_avalid = { 0xe2ac, 10, 10, 0, 1 }, 1406 .utmi_bvalid = { 0xe2ac, 16, 16, 0, 1 }, 1407 }, 1408 [USB2PHY_PORT_HOST] = { 1409 .phy_sus = { 0xe468, 1, 0, 0x2, 0x1 }, 1410 .ls_det_en = { 0xe3c0, 11, 11, 0, 1 }, 1411 .ls_det_st = { 0xe3e0, 11, 11, 0, 1 }, 1412 .ls_det_clr = { 0xe3d0, 11, 11, 0, 1 }, 1413 .utmi_ls = { 0xe2ac, 26, 25, 0, 1 }, 1414 .utmi_hstdet = { 0xe2ac, 27, 27, 0, 1 } 1415 } 1416 }, 1417 }, 1418 { /* sentinel */ } 1419 }; 1420 1421 static const struct rockchip_usb2phy_cfg rv1108_phy_cfgs[] = { 1422 { 1423 .reg = 0x100, 1424 .num_ports = 2, 1425 .clkout_ctl = { 0x108, 4, 4, 1, 0 }, 1426 .port_cfgs = { 1427 [USB2PHY_PORT_OTG] = { 1428 .phy_sus = { 0x0100, 15, 0, 0, 0x1d1 }, 1429 .bvalid_det_en = { 0x0680, 3, 3, 0, 1 }, 1430 .bvalid_det_st = { 0x0690, 3, 3, 0, 1 }, 1431 .bvalid_det_clr = { 0x06a0, 3, 3, 0, 1 }, 1432 .ls_det_en = { 0x0680, 2, 2, 0, 1 }, 1433 .ls_det_st = { 0x0690, 2, 2, 0, 1 }, 1434 .ls_det_clr = { 0x06a0, 2, 2, 0, 1 }, 1435 .utmi_bvalid = { 0x0804, 10, 10, 0, 1 }, 1436 .utmi_ls = { 0x0804, 13, 12, 0, 1 }, 1437 }, 1438 [USB2PHY_PORT_HOST] = { 1439 .phy_sus = { 0x0104, 15, 0, 0, 0x1d1 }, 1440 .ls_det_en = { 0x0680, 4, 4, 0, 1 }, 1441 .ls_det_st = { 0x0690, 4, 4, 0, 1 }, 1442 .ls_det_clr = { 0x06a0, 4, 4, 0, 1 }, 1443 .utmi_ls = { 0x0804, 9, 8, 0, 1 }, 1444 .utmi_hstdet = { 0x0804, 7, 7, 0, 1 } 1445 } 1446 }, 1447 .chg_det = { 1448 .opmode = { 0x0100, 3, 0, 5, 1 }, 1449 .cp_det = { 0x0804, 1, 1, 0, 1 }, 1450 .dcp_det = { 0x0804, 0, 0, 0, 1 }, 1451 .dp_det = { 0x0804, 2, 2, 0, 1 }, 1452 .idm_sink_en = { 0x0108, 8, 8, 0, 1 }, 1453 .idp_sink_en = { 0x0108, 7, 7, 0, 1 }, 1454 .idp_src_en = { 0x0108, 9, 9, 0, 1 }, 1455 .rdm_pdwn_en = { 0x0108, 10, 10, 0, 1 }, 1456 .vdm_src_en = { 0x0108, 12, 12, 0, 1 }, 1457 .vdp_src_en = { 0x0108, 11, 11, 0, 1 }, 1458 }, 1459 }, 1460 { /* sentinel */ } 1461 }; 1462 1463 static const struct of_device_id rockchip_usb2phy_dt_match[] = { 1464 { .compatible = "rockchip,px30-usb2phy", .data = &rk3328_phy_cfgs }, 1465 { .compatible = "rockchip,rk3228-usb2phy", .data = &rk3228_phy_cfgs }, 1466 { .compatible = "rockchip,rk3308-usb2phy", .data = &rk3308_phy_cfgs }, 1467 { .compatible = "rockchip,rk3328-usb2phy", .data = &rk3328_phy_cfgs }, 1468 { .compatible = "rockchip,rk3366-usb2phy", .data = &rk3366_phy_cfgs }, 1469 { .compatible = "rockchip,rk3399-usb2phy", .data = &rk3399_phy_cfgs }, 1470 { .compatible = "rockchip,rv1108-usb2phy", .data = &rv1108_phy_cfgs }, 1471 {} 1472 }; 1473 MODULE_DEVICE_TABLE(of, rockchip_usb2phy_dt_match); 1474 1475 static struct platform_driver rockchip_usb2phy_driver = { 1476 .probe = rockchip_usb2phy_probe, 1477 .driver = { 1478 .name = "rockchip-usb2phy", 1479 .of_match_table = rockchip_usb2phy_dt_match, 1480 }, 1481 }; 1482 module_platform_driver(rockchip_usb2phy_driver); 1483 1484 MODULE_AUTHOR("Frank Wang <frank.wang@rock-chips.com>"); 1485 MODULE_DESCRIPTION("Rockchip USB2.0 PHY driver"); 1486 MODULE_LICENSE("GPL v2"); 1487