1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2018 Rockchip Electronics Co. Ltd.
4  *
5  * Author: Wyon Bi <bivvy.bi@rock-chips.com>
6  */
7 
8 #include <linux/kernel.h>
9 #include <linux/clk.h>
10 #include <linux/iopoll.h>
11 #include <linux/clk-provider.h>
12 #include <linux/delay.h>
13 #include <linux/init.h>
14 #include <linux/module.h>
15 #include <linux/of_device.h>
16 #include <linux/platform_device.h>
17 #include <linux/reset.h>
18 #include <linux/phy/phy.h>
19 #include <linux/phy/phy-mipi-dphy.h>
20 #include <linux/pm_runtime.h>
21 #include <linux/mfd/syscon.h>
22 
23 #define PSEC_PER_SEC	1000000000000LL
24 
25 #define UPDATE(x, h, l)	(((x) << (l)) & GENMASK((h), (l)))
26 
27 /*
28  * The offset address[7:0] is distributed two parts, one from the bit7 to bit5
29  * is the first address, the other from the bit4 to bit0 is the second address.
30  * when you configure the registers, you must set both of them. The Clock Lane
31  * and Data Lane use the same registers with the same second address, but the
32  * first address is different.
33  */
34 #define FIRST_ADDRESS(x)		(((x) & 0x7) << 5)
35 #define SECOND_ADDRESS(x)		(((x) & 0x1f) << 0)
36 #define PHY_REG(first, second)		(FIRST_ADDRESS(first) | \
37 					 SECOND_ADDRESS(second))
38 
39 /* Analog Register Part: reg00 */
40 #define BANDGAP_POWER_MASK			BIT(7)
41 #define BANDGAP_POWER_DOWN			BIT(7)
42 #define BANDGAP_POWER_ON			0
43 #define LANE_EN_MASK				GENMASK(6, 2)
44 #define LANE_EN_CK				BIT(6)
45 #define LANE_EN_3				BIT(5)
46 #define LANE_EN_2				BIT(4)
47 #define LANE_EN_1				BIT(3)
48 #define LANE_EN_0				BIT(2)
49 #define POWER_WORK_MASK				GENMASK(1, 0)
50 #define POWER_WORK_ENABLE			UPDATE(1, 1, 0)
51 #define POWER_WORK_DISABLE			UPDATE(2, 1, 0)
52 /* Analog Register Part: reg01 */
53 #define REG_SYNCRST_MASK			BIT(2)
54 #define REG_SYNCRST_RESET			BIT(2)
55 #define REG_SYNCRST_NORMAL			0
56 #define REG_LDOPD_MASK				BIT(1)
57 #define REG_LDOPD_POWER_DOWN			BIT(1)
58 #define REG_LDOPD_POWER_ON			0
59 #define REG_PLLPD_MASK				BIT(0)
60 #define REG_PLLPD_POWER_DOWN			BIT(0)
61 #define REG_PLLPD_POWER_ON			0
62 /* Analog Register Part: reg03 */
63 #define REG_FBDIV_HI_MASK			BIT(5)
64 #define REG_FBDIV_HI(x)				UPDATE((x >> 8), 5, 5)
65 #define REG_PREDIV_MASK				GENMASK(4, 0)
66 #define REG_PREDIV(x)				UPDATE(x, 4, 0)
67 /* Analog Register Part: reg04 */
68 #define REG_FBDIV_LO_MASK			GENMASK(7, 0)
69 #define REG_FBDIV_LO(x)				UPDATE(x, 7, 0)
70 /* Analog Register Part: reg05 */
71 #define SAMPLE_CLOCK_PHASE_MASK			GENMASK(6, 4)
72 #define SAMPLE_CLOCK_PHASE(x)			UPDATE(x, 6, 4)
73 #define CLOCK_LANE_SKEW_PHASE_MASK		GENMASK(2, 0)
74 #define CLOCK_LANE_SKEW_PHASE(x)		UPDATE(x, 2, 0)
75 /* Analog Register Part: reg06 */
76 #define DATA_LANE_3_SKEW_PHASE_MASK		GENMASK(6, 4)
77 #define DATA_LANE_3_SKEW_PHASE(x)		UPDATE(x, 6, 4)
78 #define DATA_LANE_2_SKEW_PHASE_MASK		GENMASK(2, 0)
79 #define DATA_LANE_2_SKEW_PHASE(x)		UPDATE(x, 2, 0)
80 /* Analog Register Part: reg07 */
81 #define DATA_LANE_1_SKEW_PHASE_MASK		GENMASK(6, 4)
82 #define DATA_LANE_1_SKEW_PHASE(x)		UPDATE(x, 6, 4)
83 #define DATA_LANE_0_SKEW_PHASE_MASK		GENMASK(2, 0)
84 #define DATA_LANE_0_SKEW_PHASE(x)		UPDATE(x, 2, 0)
85 /* Analog Register Part: reg08 */
86 #define SAMPLE_CLOCK_DIRECTION_MASK		BIT(4)
87 #define SAMPLE_CLOCK_DIRECTION_REVERSE		BIT(4)
88 #define SAMPLE_CLOCK_DIRECTION_FORWARD		0
89 /* Digital Register Part: reg00 */
90 #define REG_DIG_RSTN_MASK			BIT(0)
91 #define REG_DIG_RSTN_NORMAL			BIT(0)
92 #define REG_DIG_RSTN_RESET			0
93 /* Digital Register Part: reg01 */
94 #define INVERT_TXCLKESC_MASK			BIT(1)
95 #define INVERT_TXCLKESC_ENABLE			BIT(1)
96 #define INVERT_TXCLKESC_DISABLE			0
97 #define INVERT_TXBYTECLKHS_MASK			BIT(0)
98 #define INVERT_TXBYTECLKHS_ENABLE		BIT(0)
99 #define INVERT_TXBYTECLKHS_DISABLE		0
100 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */
101 #define T_LPX_CNT_MASK				GENMASK(5, 0)
102 #define T_LPX_CNT(x)				UPDATE(x, 5, 0)
103 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */
104 #define T_HS_PREPARE_CNT_MASK			GENMASK(6, 0)
105 #define T_HS_PREPARE_CNT(x)			UPDATE(x, 6, 0)
106 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */
107 #define T_HS_ZERO_CNT_MASK			GENMASK(5, 0)
108 #define T_HS_ZERO_CNT(x)			UPDATE(x, 5, 0)
109 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */
110 #define T_HS_TRAIL_CNT_MASK			GENMASK(6, 0)
111 #define T_HS_TRAIL_CNT(x)			UPDATE(x, 6, 0)
112 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */
113 #define T_HS_EXIT_CNT_MASK			GENMASK(4, 0)
114 #define T_HS_EXIT_CNT(x)			UPDATE(x, 4, 0)
115 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */
116 #define T_CLK_POST_CNT_MASK			GENMASK(3, 0)
117 #define T_CLK_POST_CNT(x)			UPDATE(x, 3, 0)
118 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */
119 #define LPDT_TX_PPI_SYNC_MASK			BIT(2)
120 #define LPDT_TX_PPI_SYNC_ENABLE			BIT(2)
121 #define LPDT_TX_PPI_SYNC_DISABLE		0
122 #define T_WAKEUP_CNT_HI_MASK			GENMASK(1, 0)
123 #define T_WAKEUP_CNT_HI(x)			UPDATE(x, 1, 0)
124 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */
125 #define T_WAKEUP_CNT_LO_MASK			GENMASK(7, 0)
126 #define T_WAKEUP_CNT_LO(x)			UPDATE(x, 7, 0)
127 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */
128 #define T_CLK_PRE_CNT_MASK			GENMASK(3, 0)
129 #define T_CLK_PRE_CNT(x)			UPDATE(x, 3, 0)
130 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */
131 #define T_TA_GO_CNT_MASK			GENMASK(5, 0)
132 #define T_TA_GO_CNT(x)				UPDATE(x, 5, 0)
133 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */
134 #define T_TA_SURE_CNT_MASK			GENMASK(5, 0)
135 #define T_TA_SURE_CNT(x)			UPDATE(x, 5, 0)
136 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */
137 #define T_TA_WAIT_CNT_MASK			GENMASK(5, 0)
138 #define T_TA_WAIT_CNT(x)			UPDATE(x, 5, 0)
139 /* LVDS Register Part: reg00 */
140 #define LVDS_DIGITAL_INTERNAL_RESET_MASK	BIT(2)
141 #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE	BIT(2)
142 #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE	0
143 /* LVDS Register Part: reg01 */
144 #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK	BIT(7)
145 #define LVDS_DIGITAL_INTERNAL_ENABLE		BIT(7)
146 #define LVDS_DIGITAL_INTERNAL_DISABLE		0
147 /* LVDS Register Part: reg03 */
148 #define MODE_ENABLE_MASK			GENMASK(2, 0)
149 #define TTL_MODE_ENABLE				BIT(2)
150 #define LVDS_MODE_ENABLE			BIT(1)
151 #define MIPI_MODE_ENABLE			BIT(0)
152 /* LVDS Register Part: reg0b */
153 #define LVDS_LANE_EN_MASK			GENMASK(7, 3)
154 #define LVDS_DATA_LANE0_EN			BIT(7)
155 #define LVDS_DATA_LANE1_EN			BIT(6)
156 #define LVDS_DATA_LANE2_EN			BIT(5)
157 #define LVDS_DATA_LANE3_EN			BIT(4)
158 #define LVDS_CLK_LANE_EN			BIT(3)
159 #define LVDS_PLL_POWER_MASK			BIT(2)
160 #define LVDS_PLL_POWER_OFF			BIT(2)
161 #define LVDS_PLL_POWER_ON			0
162 #define LVDS_BANDGAP_POWER_MASK			BIT(0)
163 #define LVDS_BANDGAP_POWER_DOWN			BIT(0)
164 #define LVDS_BANDGAP_POWER_ON			0
165 
166 #define DSI_PHY_RSTZ		0xa0
167 #define PHY_ENABLECLK		BIT(2)
168 #define DSI_PHY_STATUS		0xb0
169 #define PHY_LOCK		BIT(0)
170 
171 struct inno_dsidphy {
172 	struct device *dev;
173 	struct clk *ref_clk;
174 	struct clk *pclk_phy;
175 	struct clk *pclk_host;
176 	void __iomem *phy_base;
177 	void __iomem *host_base;
178 	struct reset_control *rst;
179 	enum phy_mode mode;
180 	struct phy_configure_opts_mipi_dphy dphy_cfg;
181 
182 	struct clk *pll_clk;
183 	struct {
184 		struct clk_hw hw;
185 		u8 prediv;
186 		u16 fbdiv;
187 		unsigned long rate;
188 	} pll;
189 };
190 
191 enum {
192 	REGISTER_PART_ANALOG,
193 	REGISTER_PART_DIGITAL,
194 	REGISTER_PART_CLOCK_LANE,
195 	REGISTER_PART_DATA0_LANE,
196 	REGISTER_PART_DATA1_LANE,
197 	REGISTER_PART_DATA2_LANE,
198 	REGISTER_PART_DATA3_LANE,
199 	REGISTER_PART_LVDS,
200 };
201 
202 static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw)
203 {
204 	return container_of(hw, struct inno_dsidphy, pll.hw);
205 }
206 
207 static void phy_update_bits(struct inno_dsidphy *inno,
208 			    u8 first, u8 second, u8 mask, u8 val)
209 {
210 	u32 reg = PHY_REG(first, second) << 2;
211 	unsigned int tmp, orig;
212 
213 	orig = readl(inno->phy_base + reg);
214 	tmp = orig & ~mask;
215 	tmp |= val & mask;
216 	writel(tmp, inno->phy_base + reg);
217 }
218 
219 static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno,
220 						unsigned long rate)
221 {
222 	unsigned long prate = clk_get_rate(inno->ref_clk);
223 	unsigned long best_freq = 0;
224 	unsigned long fref, fout;
225 	u8 min_prediv, max_prediv;
226 	u8 _prediv, best_prediv = 1;
227 	u16 _fbdiv, best_fbdiv = 1;
228 	u32 min_delta = UINT_MAX;
229 
230 	/*
231 	 * The PLL output frequency can be calculated using a simple formula:
232 	 * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2
233 	 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2
234 	 */
235 	fref = prate / 2;
236 	if (rate > 1000000000UL)
237 		fout = 1000000000UL;
238 	else
239 		fout = rate;
240 
241 	/* 5Mhz < Fref / prediv < 40MHz */
242 	min_prediv = DIV_ROUND_UP(fref, 40000000);
243 	max_prediv = fref / 5000000;
244 
245 	for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) {
246 		u64 tmp;
247 		u32 delta;
248 
249 		tmp = (u64)fout * _prediv;
250 		do_div(tmp, fref);
251 		_fbdiv = tmp;
252 
253 		/*
254 		 * The possible settings of feedback divider are
255 		 * 12, 13, 14, 16, ~ 511
256 		 */
257 		if (_fbdiv == 15)
258 			continue;
259 
260 		if (_fbdiv < 12 || _fbdiv > 511)
261 			continue;
262 
263 		tmp = (u64)_fbdiv * fref;
264 		do_div(tmp, _prediv);
265 
266 		delta = abs(fout - tmp);
267 		if (!delta) {
268 			best_prediv = _prediv;
269 			best_fbdiv = _fbdiv;
270 			best_freq = tmp;
271 			break;
272 		} else if (delta < min_delta) {
273 			best_prediv = _prediv;
274 			best_fbdiv = _fbdiv;
275 			best_freq = tmp;
276 			min_delta = delta;
277 		}
278 	}
279 
280 	if (best_freq) {
281 		inno->pll.prediv = best_prediv;
282 		inno->pll.fbdiv = best_fbdiv;
283 		inno->pll.rate = best_freq;
284 	}
285 
286 	return best_freq;
287 }
288 
289 static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno)
290 {
291 	struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg;
292 	const struct {
293 		unsigned long rate;
294 		u8 hs_prepare;
295 		u8 clk_lane_hs_zero;
296 		u8 data_lane_hs_zero;
297 		u8 hs_trail;
298 	} timings[] = {
299 		{ 110000000, 0x20, 0x16, 0x02, 0x22},
300 		{ 150000000, 0x06, 0x16, 0x03, 0x45},
301 		{ 200000000, 0x18, 0x17, 0x04, 0x0b},
302 		{ 250000000, 0x05, 0x17, 0x05, 0x16},
303 		{ 300000000, 0x51, 0x18, 0x06, 0x2c},
304 		{ 400000000, 0x64, 0x19, 0x07, 0x33},
305 		{ 500000000, 0x20, 0x1b, 0x07, 0x4e},
306 		{ 600000000, 0x6a, 0x1d, 0x08, 0x3a},
307 		{ 700000000, 0x3e, 0x1e, 0x08, 0x6a},
308 		{ 800000000, 0x21, 0x1f, 0x09, 0x29},
309 		{1000000000, 0x09, 0x20, 0x09, 0x27},
310 	};
311 	u32 t_txbyteclkhs, t_txclkesc;
312 	u32 txbyteclkhs, txclkesc, esc_clk_div;
313 	u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait;
314 	u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero;
315 	unsigned int i;
316 
317 	inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate);
318 
319 	/* Select MIPI mode */
320 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
321 			MODE_ENABLE_MASK, MIPI_MODE_ENABLE);
322 	/* Configure PLL */
323 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
324 			REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv));
325 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
326 			REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv));
327 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
328 			REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv));
329 	/* Enable PLL and LDO */
330 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
331 			REG_LDOPD_MASK | REG_PLLPD_MASK,
332 			REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON);
333 	/* Reset analog */
334 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
335 			REG_SYNCRST_MASK, REG_SYNCRST_RESET);
336 	udelay(1);
337 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
338 			REG_SYNCRST_MASK, REG_SYNCRST_NORMAL);
339 	/* Reset digital */
340 	phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
341 			REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET);
342 	udelay(1);
343 	phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00,
344 			REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL);
345 
346 	txbyteclkhs = inno->pll.rate / 8;
347 	t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs);
348 
349 	esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000);
350 	txclkesc = txbyteclkhs / esc_clk_div;
351 	t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc);
352 
353 	/*
354 	 * The value of counter for HS Ths-exit
355 	 * Ths-exit = Tpin_txbyteclkhs * value
356 	 */
357 	hs_exit = DIV_ROUND_UP(cfg->hs_exit, t_txbyteclkhs);
358 	/*
359 	 * The value of counter for HS Tclk-post
360 	 * Tclk-post = Tpin_txbyteclkhs * value
361 	 */
362 	clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs);
363 	/*
364 	 * The value of counter for HS Tclk-pre
365 	 * Tclk-pre = Tpin_txbyteclkhs * value
366 	 */
367 	clk_pre = DIV_ROUND_UP(cfg->clk_pre, t_txbyteclkhs);
368 
369 	/*
370 	 * The value of counter for HS Tlpx Time
371 	 * Tlpx = Tpin_txbyteclkhs * (2 + value)
372 	 */
373 	lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs);
374 	if (lpx >= 2)
375 		lpx -= 2;
376 
377 	/*
378 	 * The value of counter for HS Tta-go
379 	 * Tta-go for turnaround
380 	 * Tta-go = Ttxclkesc * value
381 	 */
382 	ta_go = DIV_ROUND_UP(cfg->ta_go, t_txclkesc);
383 	/*
384 	 * The value of counter for HS Tta-sure
385 	 * Tta-sure for turnaround
386 	 * Tta-sure = Ttxclkesc * value
387 	 */
388 	ta_sure = DIV_ROUND_UP(cfg->ta_sure, t_txclkesc);
389 	/*
390 	 * The value of counter for HS Tta-wait
391 	 * Tta-wait for turnaround
392 	 * Tta-wait = Ttxclkesc * value
393 	 */
394 	ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc);
395 
396 	for (i = 0; i < ARRAY_SIZE(timings); i++)
397 		if (inno->pll.rate <= timings[i].rate)
398 			break;
399 
400 	if (i == ARRAY_SIZE(timings))
401 		--i;
402 
403 	hs_prepare = timings[i].hs_prepare;
404 	hs_trail = timings[i].hs_trail;
405 	clk_lane_hs_zero = timings[i].clk_lane_hs_zero;
406 	data_lane_hs_zero = timings[i].data_lane_hs_zero;
407 	wakeup = 0x3ff;
408 
409 	for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) {
410 		if (i == REGISTER_PART_CLOCK_LANE)
411 			hs_zero = clk_lane_hs_zero;
412 		else
413 			hs_zero = data_lane_hs_zero;
414 
415 		phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK,
416 				T_LPX_CNT(lpx));
417 		phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK,
418 				T_HS_PREPARE_CNT(hs_prepare));
419 		phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK,
420 				T_HS_ZERO_CNT(hs_zero));
421 		phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK,
422 				T_HS_TRAIL_CNT(hs_trail));
423 		phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK,
424 				T_HS_EXIT_CNT(hs_exit));
425 		phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK,
426 				T_CLK_POST_CNT(clk_post));
427 		phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK,
428 				T_CLK_PRE_CNT(clk_pre));
429 		phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK,
430 				T_WAKEUP_CNT_HI(wakeup >> 8));
431 		phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK,
432 				T_WAKEUP_CNT_LO(wakeup));
433 		phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK,
434 				T_TA_GO_CNT(ta_go));
435 		phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK,
436 				T_TA_SURE_CNT(ta_sure));
437 		phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK,
438 				T_TA_WAIT_CNT(ta_wait));
439 	}
440 
441 	/* Enable all lanes on analog part */
442 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
443 			LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 |
444 			LANE_EN_1 | LANE_EN_0);
445 }
446 
447 static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno)
448 {
449 	u8 prediv = 2;
450 	u16 fbdiv = 28;
451 
452 	/* Sample clock reverse direction */
453 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08,
454 			SAMPLE_CLOCK_DIRECTION_MASK,
455 			SAMPLE_CLOCK_DIRECTION_REVERSE);
456 
457 	/* Select LVDS mode */
458 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x03,
459 			MODE_ENABLE_MASK, LVDS_MODE_ENABLE);
460 	/* Configure PLL */
461 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
462 			REG_PREDIV_MASK, REG_PREDIV(prediv));
463 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03,
464 			REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv));
465 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04,
466 			REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv));
467 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc);
468 	/* Enable PLL and Bandgap */
469 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
470 			LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
471 			LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON);
472 
473 	msleep(20);
474 
475 	/* Reset LVDS digital logic */
476 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
477 			LVDS_DIGITAL_INTERNAL_RESET_MASK,
478 			LVDS_DIGITAL_INTERNAL_RESET_ENABLE);
479 	udelay(1);
480 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x00,
481 			LVDS_DIGITAL_INTERNAL_RESET_MASK,
482 			LVDS_DIGITAL_INTERNAL_RESET_DISABLE);
483 	/* Enable LVDS digital logic */
484 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
485 			LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
486 			LVDS_DIGITAL_INTERNAL_ENABLE);
487 	/* Enable LVDS analog driver */
488 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
489 			LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN |
490 			LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN |
491 			LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN);
492 }
493 
494 static int inno_dsidphy_power_on(struct phy *phy)
495 {
496 	struct inno_dsidphy *inno = phy_get_drvdata(phy);
497 
498 	clk_prepare_enable(inno->pclk_phy);
499 	clk_prepare_enable(inno->ref_clk);
500 	pm_runtime_get_sync(inno->dev);
501 
502 	/* Bandgap power on */
503 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
504 			BANDGAP_POWER_MASK, BANDGAP_POWER_ON);
505 	/* Enable power work */
506 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
507 			POWER_WORK_MASK, POWER_WORK_ENABLE);
508 
509 	switch (inno->mode) {
510 	case PHY_MODE_MIPI_DPHY:
511 		inno_dsidphy_mipi_mode_enable(inno);
512 		break;
513 	case PHY_MODE_LVDS:
514 		inno_dsidphy_lvds_mode_enable(inno);
515 		break;
516 	default:
517 		return -EINVAL;
518 	}
519 
520 	return 0;
521 }
522 
523 static int inno_dsidphy_power_off(struct phy *phy)
524 {
525 	struct inno_dsidphy *inno = phy_get_drvdata(phy);
526 
527 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0);
528 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01,
529 			REG_LDOPD_MASK | REG_PLLPD_MASK,
530 			REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN);
531 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
532 			POWER_WORK_MASK, POWER_WORK_DISABLE);
533 	phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00,
534 			BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN);
535 
536 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0);
537 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x01,
538 			LVDS_DIGITAL_INTERNAL_ENABLE_MASK,
539 			LVDS_DIGITAL_INTERNAL_DISABLE);
540 	phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b,
541 			LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK,
542 			LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN);
543 
544 	pm_runtime_put(inno->dev);
545 	clk_disable_unprepare(inno->ref_clk);
546 	clk_disable_unprepare(inno->pclk_phy);
547 
548 	return 0;
549 }
550 
551 static int inno_dsidphy_set_mode(struct phy *phy, enum phy_mode mode,
552 				   int submode)
553 {
554 	struct inno_dsidphy *inno = phy_get_drvdata(phy);
555 
556 	switch (mode) {
557 	case PHY_MODE_MIPI_DPHY:
558 	case PHY_MODE_LVDS:
559 		inno->mode = mode;
560 		break;
561 	default:
562 		return -EINVAL;
563 	}
564 
565 	return 0;
566 }
567 
568 static int inno_dsidphy_configure(struct phy *phy,
569 				  union phy_configure_opts *opts)
570 {
571 	struct inno_dsidphy *inno = phy_get_drvdata(phy);
572 	int ret;
573 
574 	if (inno->mode != PHY_MODE_MIPI_DPHY)
575 		return -EINVAL;
576 
577 	ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy);
578 	if (ret)
579 		return ret;
580 
581 	memcpy(&inno->dphy_cfg, &opts->mipi_dphy, sizeof(inno->dphy_cfg));
582 
583 	return 0;
584 }
585 
586 static const struct phy_ops inno_dsidphy_ops = {
587 	.configure = inno_dsidphy_configure,
588 	.set_mode = inno_dsidphy_set_mode,
589 	.power_on = inno_dsidphy_power_on,
590 	.power_off = inno_dsidphy_power_off,
591 	.owner = THIS_MODULE,
592 };
593 
594 static int inno_dsidphy_probe(struct platform_device *pdev)
595 {
596 	struct device *dev = &pdev->dev;
597 	struct inno_dsidphy *inno;
598 	struct phy_provider *phy_provider;
599 	struct phy *phy;
600 	int ret;
601 
602 	inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL);
603 	if (!inno)
604 		return -ENOMEM;
605 
606 	inno->dev = dev;
607 	platform_set_drvdata(pdev, inno);
608 
609 	inno->phy_base = devm_platform_ioremap_resource(pdev, 0);
610 	if (!inno->phy_base)
611 		return -ENOMEM;
612 
613 	inno->ref_clk = devm_clk_get(dev, "ref");
614 	if (IS_ERR(inno->ref_clk)) {
615 		ret = PTR_ERR(inno->ref_clk);
616 		dev_err(dev, "failed to get ref clock: %d\n", ret);
617 		return ret;
618 	}
619 
620 	inno->pclk_phy = devm_clk_get(dev, "pclk");
621 	if (IS_ERR(inno->pclk_phy)) {
622 		ret = PTR_ERR(inno->pclk_phy);
623 		dev_err(dev, "failed to get phy pclk: %d\n", ret);
624 		return ret;
625 	}
626 
627 	inno->rst = devm_reset_control_get(dev, "apb");
628 	if (IS_ERR(inno->rst)) {
629 		ret = PTR_ERR(inno->rst);
630 		dev_err(dev, "failed to get system reset control: %d\n", ret);
631 		return ret;
632 	}
633 
634 	phy = devm_phy_create(dev, NULL, &inno_dsidphy_ops);
635 	if (IS_ERR(phy)) {
636 		ret = PTR_ERR(phy);
637 		dev_err(dev, "failed to create phy: %d\n", ret);
638 		return ret;
639 	}
640 
641 	phy_set_drvdata(phy, inno);
642 
643 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
644 	if (IS_ERR(phy_provider)) {
645 		ret = PTR_ERR(phy_provider);
646 		dev_err(dev, "failed to register phy provider: %d\n", ret);
647 		return ret;
648 	}
649 
650 	pm_runtime_enable(dev);
651 
652 	return 0;
653 }
654 
655 static int inno_dsidphy_remove(struct platform_device *pdev)
656 {
657 	struct inno_dsidphy *inno = platform_get_drvdata(pdev);
658 
659 	pm_runtime_disable(inno->dev);
660 
661 	return 0;
662 }
663 
664 static const struct of_device_id inno_dsidphy_of_match[] = {
665 	{ .compatible = "rockchip,px30-dsi-dphy", },
666 	{ .compatible = "rockchip,rk3128-dsi-dphy", },
667 	{ .compatible = "rockchip,rk3368-dsi-dphy", },
668 	{}
669 };
670 MODULE_DEVICE_TABLE(of, inno_dsidphy_of_match);
671 
672 static struct platform_driver inno_dsidphy_driver = {
673 	.driver = {
674 		.name = "inno-dsidphy",
675 		.of_match_table	= of_match_ptr(inno_dsidphy_of_match),
676 	},
677 	.probe = inno_dsidphy_probe,
678 	.remove = inno_dsidphy_remove,
679 };
680 module_platform_driver(inno_dsidphy_driver);
681 
682 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>");
683 MODULE_DESCRIPTION("Innosilicon MIPI/LVDS/TTL Video Combo PHY driver");
684 MODULE_LICENSE("GPL v2");
685