1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Wyon Bi <bivvy.bi@rock-chips.com> 6 */ 7 8 #include <linux/bits.h> 9 #include <linux/kernel.h> 10 #include <linux/clk.h> 11 #include <linux/iopoll.h> 12 #include <linux/clk-provider.h> 13 #include <linux/delay.h> 14 #include <linux/init.h> 15 #include <linux/mfd/syscon.h> 16 #include <linux/module.h> 17 #include <linux/of_device.h> 18 #include <linux/platform_device.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/reset.h> 21 #include <linux/time64.h> 22 23 #include <linux/phy/phy.h> 24 #include <linux/phy/phy-mipi-dphy.h> 25 26 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 27 28 /* 29 * The offset address[7:0] is distributed two parts, one from the bit7 to bit5 30 * is the first address, the other from the bit4 to bit0 is the second address. 31 * when you configure the registers, you must set both of them. The Clock Lane 32 * and Data Lane use the same registers with the same second address, but the 33 * first address is different. 34 */ 35 #define FIRST_ADDRESS(x) (((x) & 0x7) << 5) 36 #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0) 37 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ 38 SECOND_ADDRESS(second)) 39 40 /* Analog Register Part: reg00 */ 41 #define BANDGAP_POWER_MASK BIT(7) 42 #define BANDGAP_POWER_DOWN BIT(7) 43 #define BANDGAP_POWER_ON 0 44 #define LANE_EN_MASK GENMASK(6, 2) 45 #define LANE_EN_CK BIT(6) 46 #define LANE_EN_3 BIT(5) 47 #define LANE_EN_2 BIT(4) 48 #define LANE_EN_1 BIT(3) 49 #define LANE_EN_0 BIT(2) 50 #define POWER_WORK_MASK GENMASK(1, 0) 51 #define POWER_WORK_ENABLE UPDATE(1, 1, 0) 52 #define POWER_WORK_DISABLE UPDATE(2, 1, 0) 53 /* Analog Register Part: reg01 */ 54 #define REG_SYNCRST_MASK BIT(2) 55 #define REG_SYNCRST_RESET BIT(2) 56 #define REG_SYNCRST_NORMAL 0 57 #define REG_LDOPD_MASK BIT(1) 58 #define REG_LDOPD_POWER_DOWN BIT(1) 59 #define REG_LDOPD_POWER_ON 0 60 #define REG_PLLPD_MASK BIT(0) 61 #define REG_PLLPD_POWER_DOWN BIT(0) 62 #define REG_PLLPD_POWER_ON 0 63 /* Analog Register Part: reg03 */ 64 #define REG_FBDIV_HI_MASK BIT(5) 65 #define REG_FBDIV_HI(x) UPDATE((x >> 8), 5, 5) 66 #define REG_PREDIV_MASK GENMASK(4, 0) 67 #define REG_PREDIV(x) UPDATE(x, 4, 0) 68 /* Analog Register Part: reg04 */ 69 #define REG_FBDIV_LO_MASK GENMASK(7, 0) 70 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0) 71 /* Analog Register Part: reg05 */ 72 #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4) 73 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4) 74 #define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0) 75 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0) 76 /* Analog Register Part: reg06 */ 77 #define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4) 78 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4) 79 #define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0) 80 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0) 81 /* Analog Register Part: reg07 */ 82 #define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4) 83 #define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4) 84 #define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0) 85 #define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0) 86 /* Analog Register Part: reg08 */ 87 #define SAMPLE_CLOCK_DIRECTION_MASK BIT(4) 88 #define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4) 89 #define SAMPLE_CLOCK_DIRECTION_FORWARD 0 90 /* Digital Register Part: reg00 */ 91 #define REG_DIG_RSTN_MASK BIT(0) 92 #define REG_DIG_RSTN_NORMAL BIT(0) 93 #define REG_DIG_RSTN_RESET 0 94 /* Digital Register Part: reg01 */ 95 #define INVERT_TXCLKESC_MASK BIT(1) 96 #define INVERT_TXCLKESC_ENABLE BIT(1) 97 #define INVERT_TXCLKESC_DISABLE 0 98 #define INVERT_TXBYTECLKHS_MASK BIT(0) 99 #define INVERT_TXBYTECLKHS_ENABLE BIT(0) 100 #define INVERT_TXBYTECLKHS_DISABLE 0 101 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */ 102 #define T_LPX_CNT_MASK GENMASK(5, 0) 103 #define T_LPX_CNT(x) UPDATE(x, 5, 0) 104 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */ 105 #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0) 106 #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0) 107 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */ 108 #define T_HS_ZERO_CNT_MASK GENMASK(5, 0) 109 #define T_HS_ZERO_CNT(x) UPDATE(x, 5, 0) 110 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */ 111 #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0) 112 #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0) 113 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */ 114 #define T_HS_EXIT_CNT_MASK GENMASK(4, 0) 115 #define T_HS_EXIT_CNT(x) UPDATE(x, 4, 0) 116 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */ 117 #define T_CLK_POST_CNT_MASK GENMASK(3, 0) 118 #define T_CLK_POST_CNT(x) UPDATE(x, 3, 0) 119 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */ 120 #define LPDT_TX_PPI_SYNC_MASK BIT(2) 121 #define LPDT_TX_PPI_SYNC_ENABLE BIT(2) 122 #define LPDT_TX_PPI_SYNC_DISABLE 0 123 #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0) 124 #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0) 125 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */ 126 #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0) 127 #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0) 128 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */ 129 #define T_CLK_PRE_CNT_MASK GENMASK(3, 0) 130 #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0) 131 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */ 132 #define T_TA_GO_CNT_MASK GENMASK(5, 0) 133 #define T_TA_GO_CNT(x) UPDATE(x, 5, 0) 134 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */ 135 #define T_TA_SURE_CNT_MASK GENMASK(5, 0) 136 #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0) 137 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */ 138 #define T_TA_WAIT_CNT_MASK GENMASK(5, 0) 139 #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0) 140 /* LVDS Register Part: reg00 */ 141 #define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2) 142 #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2) 143 #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0 144 /* LVDS Register Part: reg01 */ 145 #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7) 146 #define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7) 147 #define LVDS_DIGITAL_INTERNAL_DISABLE 0 148 /* LVDS Register Part: reg03 */ 149 #define MODE_ENABLE_MASK GENMASK(2, 0) 150 #define TTL_MODE_ENABLE BIT(2) 151 #define LVDS_MODE_ENABLE BIT(1) 152 #define MIPI_MODE_ENABLE BIT(0) 153 /* LVDS Register Part: reg0b */ 154 #define LVDS_LANE_EN_MASK GENMASK(7, 3) 155 #define LVDS_DATA_LANE0_EN BIT(7) 156 #define LVDS_DATA_LANE1_EN BIT(6) 157 #define LVDS_DATA_LANE2_EN BIT(5) 158 #define LVDS_DATA_LANE3_EN BIT(4) 159 #define LVDS_CLK_LANE_EN BIT(3) 160 #define LVDS_PLL_POWER_MASK BIT(2) 161 #define LVDS_PLL_POWER_OFF BIT(2) 162 #define LVDS_PLL_POWER_ON 0 163 #define LVDS_BANDGAP_POWER_MASK BIT(0) 164 #define LVDS_BANDGAP_POWER_DOWN BIT(0) 165 #define LVDS_BANDGAP_POWER_ON 0 166 167 #define DSI_PHY_RSTZ 0xa0 168 #define PHY_ENABLECLK BIT(2) 169 #define DSI_PHY_STATUS 0xb0 170 #define PHY_LOCK BIT(0) 171 172 struct inno_dsidphy { 173 struct device *dev; 174 struct clk *ref_clk; 175 struct clk *pclk_phy; 176 struct clk *pclk_host; 177 void __iomem *phy_base; 178 void __iomem *host_base; 179 struct reset_control *rst; 180 enum phy_mode mode; 181 struct phy_configure_opts_mipi_dphy dphy_cfg; 182 183 struct clk *pll_clk; 184 struct { 185 struct clk_hw hw; 186 u8 prediv; 187 u16 fbdiv; 188 unsigned long rate; 189 } pll; 190 }; 191 192 enum { 193 REGISTER_PART_ANALOG, 194 REGISTER_PART_DIGITAL, 195 REGISTER_PART_CLOCK_LANE, 196 REGISTER_PART_DATA0_LANE, 197 REGISTER_PART_DATA1_LANE, 198 REGISTER_PART_DATA2_LANE, 199 REGISTER_PART_DATA3_LANE, 200 REGISTER_PART_LVDS, 201 }; 202 203 static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw) 204 { 205 return container_of(hw, struct inno_dsidphy, pll.hw); 206 } 207 208 static void phy_update_bits(struct inno_dsidphy *inno, 209 u8 first, u8 second, u8 mask, u8 val) 210 { 211 u32 reg = PHY_REG(first, second) << 2; 212 unsigned int tmp, orig; 213 214 orig = readl(inno->phy_base + reg); 215 tmp = orig & ~mask; 216 tmp |= val & mask; 217 writel(tmp, inno->phy_base + reg); 218 } 219 220 static unsigned long inno_dsidphy_pll_calc_rate(struct inno_dsidphy *inno, 221 unsigned long rate) 222 { 223 unsigned long prate = clk_get_rate(inno->ref_clk); 224 unsigned long best_freq = 0; 225 unsigned long fref, fout; 226 u8 min_prediv, max_prediv; 227 u8 _prediv, best_prediv = 1; 228 u16 _fbdiv, best_fbdiv = 1; 229 u32 min_delta = UINT_MAX; 230 231 /* 232 * The PLL output frequency can be calculated using a simple formula: 233 * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2 234 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 235 */ 236 fref = prate / 2; 237 if (rate > 1000000000UL) 238 fout = 1000000000UL; 239 else 240 fout = rate; 241 242 /* 5Mhz < Fref / prediv < 40MHz */ 243 min_prediv = DIV_ROUND_UP(fref, 40000000); 244 max_prediv = fref / 5000000; 245 246 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 247 u64 tmp; 248 u32 delta; 249 250 tmp = (u64)fout * _prediv; 251 do_div(tmp, fref); 252 _fbdiv = tmp; 253 254 /* 255 * The possible settings of feedback divider are 256 * 12, 13, 14, 16, ~ 511 257 */ 258 if (_fbdiv == 15) 259 continue; 260 261 if (_fbdiv < 12 || _fbdiv > 511) 262 continue; 263 264 tmp = (u64)_fbdiv * fref; 265 do_div(tmp, _prediv); 266 267 delta = abs(fout - tmp); 268 if (!delta) { 269 best_prediv = _prediv; 270 best_fbdiv = _fbdiv; 271 best_freq = tmp; 272 break; 273 } else if (delta < min_delta) { 274 best_prediv = _prediv; 275 best_fbdiv = _fbdiv; 276 best_freq = tmp; 277 min_delta = delta; 278 } 279 } 280 281 if (best_freq) { 282 inno->pll.prediv = best_prediv; 283 inno->pll.fbdiv = best_fbdiv; 284 inno->pll.rate = best_freq; 285 } 286 287 return best_freq; 288 } 289 290 static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) 291 { 292 struct phy_configure_opts_mipi_dphy *cfg = &inno->dphy_cfg; 293 const struct { 294 unsigned long rate; 295 u8 hs_prepare; 296 u8 clk_lane_hs_zero; 297 u8 data_lane_hs_zero; 298 u8 hs_trail; 299 } timings[] = { 300 { 110000000, 0x20, 0x16, 0x02, 0x22}, 301 { 150000000, 0x06, 0x16, 0x03, 0x45}, 302 { 200000000, 0x18, 0x17, 0x04, 0x0b}, 303 { 250000000, 0x05, 0x17, 0x05, 0x16}, 304 { 300000000, 0x51, 0x18, 0x06, 0x2c}, 305 { 400000000, 0x64, 0x19, 0x07, 0x33}, 306 { 500000000, 0x20, 0x1b, 0x07, 0x4e}, 307 { 600000000, 0x6a, 0x1d, 0x08, 0x3a}, 308 { 700000000, 0x3e, 0x1e, 0x08, 0x6a}, 309 { 800000000, 0x21, 0x1f, 0x09, 0x29}, 310 {1000000000, 0x09, 0x20, 0x09, 0x27}, 311 }; 312 u32 t_txbyteclkhs, t_txclkesc; 313 u32 txbyteclkhs, txclkesc, esc_clk_div; 314 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; 315 u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; 316 unsigned int i; 317 318 inno_dsidphy_pll_calc_rate(inno, cfg->hs_clk_rate); 319 320 /* Select MIPI mode */ 321 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 322 MODE_ENABLE_MASK, MIPI_MODE_ENABLE); 323 /* Configure PLL */ 324 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 325 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); 326 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 327 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); 328 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, 329 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); 330 /* Enable PLL and LDO */ 331 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 332 REG_LDOPD_MASK | REG_PLLPD_MASK, 333 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON); 334 /* Reset analog */ 335 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 336 REG_SYNCRST_MASK, REG_SYNCRST_RESET); 337 udelay(1); 338 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 339 REG_SYNCRST_MASK, REG_SYNCRST_NORMAL); 340 /* Reset digital */ 341 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, 342 REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET); 343 udelay(1); 344 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, 345 REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL); 346 347 txbyteclkhs = inno->pll.rate / 8; 348 t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs); 349 350 esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000); 351 txclkesc = txbyteclkhs / esc_clk_div; 352 t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc); 353 354 /* 355 * The value of counter for HS Ths-exit 356 * Ths-exit = Tpin_txbyteclkhs * value 357 */ 358 hs_exit = DIV_ROUND_UP(cfg->hs_exit, t_txbyteclkhs); 359 /* 360 * The value of counter for HS Tclk-post 361 * Tclk-post = Tpin_txbyteclkhs * value 362 */ 363 clk_post = DIV_ROUND_UP(cfg->clk_post, t_txbyteclkhs); 364 /* 365 * The value of counter for HS Tclk-pre 366 * Tclk-pre = Tpin_txbyteclkhs * value 367 */ 368 clk_pre = DIV_ROUND_UP(cfg->clk_pre, BITS_PER_BYTE); 369 370 /* 371 * The value of counter for HS Tlpx Time 372 * Tlpx = Tpin_txbyteclkhs * (2 + value) 373 */ 374 lpx = DIV_ROUND_UP(cfg->lpx, t_txbyteclkhs); 375 if (lpx >= 2) 376 lpx -= 2; 377 378 /* 379 * The value of counter for HS Tta-go 380 * Tta-go for turnaround 381 * Tta-go = Ttxclkesc * value 382 */ 383 ta_go = DIV_ROUND_UP(cfg->ta_go, t_txclkesc); 384 /* 385 * The value of counter for HS Tta-sure 386 * Tta-sure for turnaround 387 * Tta-sure = Ttxclkesc * value 388 */ 389 ta_sure = DIV_ROUND_UP(cfg->ta_sure, t_txclkesc); 390 /* 391 * The value of counter for HS Tta-wait 392 * Tta-wait for turnaround 393 * Tta-wait = Ttxclkesc * value 394 */ 395 ta_wait = DIV_ROUND_UP(cfg->ta_get, t_txclkesc); 396 397 for (i = 0; i < ARRAY_SIZE(timings); i++) 398 if (inno->pll.rate <= timings[i].rate) 399 break; 400 401 if (i == ARRAY_SIZE(timings)) 402 --i; 403 404 hs_prepare = timings[i].hs_prepare; 405 hs_trail = timings[i].hs_trail; 406 clk_lane_hs_zero = timings[i].clk_lane_hs_zero; 407 data_lane_hs_zero = timings[i].data_lane_hs_zero; 408 wakeup = 0x3ff; 409 410 for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) { 411 if (i == REGISTER_PART_CLOCK_LANE) 412 hs_zero = clk_lane_hs_zero; 413 else 414 hs_zero = data_lane_hs_zero; 415 416 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK, 417 T_LPX_CNT(lpx)); 418 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK, 419 T_HS_PREPARE_CNT(hs_prepare)); 420 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK, 421 T_HS_ZERO_CNT(hs_zero)); 422 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK, 423 T_HS_TRAIL_CNT(hs_trail)); 424 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK, 425 T_HS_EXIT_CNT(hs_exit)); 426 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK, 427 T_CLK_POST_CNT(clk_post)); 428 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK, 429 T_CLK_PRE_CNT(clk_pre)); 430 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK, 431 T_WAKEUP_CNT_HI(wakeup >> 8)); 432 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK, 433 T_WAKEUP_CNT_LO(wakeup)); 434 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK, 435 T_TA_GO_CNT(ta_go)); 436 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK, 437 T_TA_SURE_CNT(ta_sure)); 438 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK, 439 T_TA_WAIT_CNT(ta_wait)); 440 } 441 442 /* Enable all lanes on analog part */ 443 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 444 LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 | 445 LANE_EN_1 | LANE_EN_0); 446 } 447 448 static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) 449 { 450 u8 prediv = 2; 451 u16 fbdiv = 28; 452 453 /* Sample clock reverse direction */ 454 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, 455 SAMPLE_CLOCK_DIRECTION_MASK, 456 SAMPLE_CLOCK_DIRECTION_REVERSE); 457 458 /* Select LVDS mode */ 459 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 460 MODE_ENABLE_MASK, LVDS_MODE_ENABLE); 461 /* Configure PLL */ 462 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 463 REG_PREDIV_MASK, REG_PREDIV(prediv)); 464 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 465 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv)); 466 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, 467 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv)); 468 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc); 469 /* Enable PLL and Bandgap */ 470 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 471 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, 472 LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON); 473 474 msleep(20); 475 476 /* Reset LVDS digital logic */ 477 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 478 LVDS_DIGITAL_INTERNAL_RESET_MASK, 479 LVDS_DIGITAL_INTERNAL_RESET_ENABLE); 480 udelay(1); 481 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 482 LVDS_DIGITAL_INTERNAL_RESET_MASK, 483 LVDS_DIGITAL_INTERNAL_RESET_DISABLE); 484 /* Enable LVDS digital logic */ 485 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 486 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 487 LVDS_DIGITAL_INTERNAL_ENABLE); 488 /* Enable LVDS analog driver */ 489 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 490 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN | 491 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN | 492 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN); 493 } 494 495 static int inno_dsidphy_power_on(struct phy *phy) 496 { 497 struct inno_dsidphy *inno = phy_get_drvdata(phy); 498 499 clk_prepare_enable(inno->pclk_phy); 500 clk_prepare_enable(inno->ref_clk); 501 pm_runtime_get_sync(inno->dev); 502 503 /* Bandgap power on */ 504 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 505 BANDGAP_POWER_MASK, BANDGAP_POWER_ON); 506 /* Enable power work */ 507 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 508 POWER_WORK_MASK, POWER_WORK_ENABLE); 509 510 switch (inno->mode) { 511 case PHY_MODE_MIPI_DPHY: 512 inno_dsidphy_mipi_mode_enable(inno); 513 break; 514 case PHY_MODE_LVDS: 515 inno_dsidphy_lvds_mode_enable(inno); 516 break; 517 default: 518 return -EINVAL; 519 } 520 521 return 0; 522 } 523 524 static int inno_dsidphy_power_off(struct phy *phy) 525 { 526 struct inno_dsidphy *inno = phy_get_drvdata(phy); 527 528 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0); 529 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 530 REG_LDOPD_MASK | REG_PLLPD_MASK, 531 REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN); 532 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 533 POWER_WORK_MASK, POWER_WORK_DISABLE); 534 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 535 BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN); 536 537 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0); 538 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 539 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 540 LVDS_DIGITAL_INTERNAL_DISABLE); 541 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 542 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, 543 LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN); 544 545 pm_runtime_put(inno->dev); 546 clk_disable_unprepare(inno->ref_clk); 547 clk_disable_unprepare(inno->pclk_phy); 548 549 return 0; 550 } 551 552 static int inno_dsidphy_set_mode(struct phy *phy, enum phy_mode mode, 553 int submode) 554 { 555 struct inno_dsidphy *inno = phy_get_drvdata(phy); 556 557 switch (mode) { 558 case PHY_MODE_MIPI_DPHY: 559 case PHY_MODE_LVDS: 560 inno->mode = mode; 561 break; 562 default: 563 return -EINVAL; 564 } 565 566 return 0; 567 } 568 569 static int inno_dsidphy_configure(struct phy *phy, 570 union phy_configure_opts *opts) 571 { 572 struct inno_dsidphy *inno = phy_get_drvdata(phy); 573 int ret; 574 575 if (inno->mode != PHY_MODE_MIPI_DPHY) 576 return -EINVAL; 577 578 ret = phy_mipi_dphy_config_validate(&opts->mipi_dphy); 579 if (ret) 580 return ret; 581 582 memcpy(&inno->dphy_cfg, &opts->mipi_dphy, sizeof(inno->dphy_cfg)); 583 584 return 0; 585 } 586 587 static const struct phy_ops inno_dsidphy_ops = { 588 .configure = inno_dsidphy_configure, 589 .set_mode = inno_dsidphy_set_mode, 590 .power_on = inno_dsidphy_power_on, 591 .power_off = inno_dsidphy_power_off, 592 .owner = THIS_MODULE, 593 }; 594 595 static int inno_dsidphy_probe(struct platform_device *pdev) 596 { 597 struct device *dev = &pdev->dev; 598 struct inno_dsidphy *inno; 599 struct phy_provider *phy_provider; 600 struct phy *phy; 601 int ret; 602 603 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL); 604 if (!inno) 605 return -ENOMEM; 606 607 inno->dev = dev; 608 platform_set_drvdata(pdev, inno); 609 610 inno->phy_base = devm_platform_ioremap_resource(pdev, 0); 611 if (IS_ERR(inno->phy_base)) 612 return PTR_ERR(inno->phy_base); 613 614 inno->ref_clk = devm_clk_get(dev, "ref"); 615 if (IS_ERR(inno->ref_clk)) { 616 ret = PTR_ERR(inno->ref_clk); 617 dev_err(dev, "failed to get ref clock: %d\n", ret); 618 return ret; 619 } 620 621 inno->pclk_phy = devm_clk_get(dev, "pclk"); 622 if (IS_ERR(inno->pclk_phy)) { 623 ret = PTR_ERR(inno->pclk_phy); 624 dev_err(dev, "failed to get phy pclk: %d\n", ret); 625 return ret; 626 } 627 628 inno->rst = devm_reset_control_get(dev, "apb"); 629 if (IS_ERR(inno->rst)) { 630 ret = PTR_ERR(inno->rst); 631 dev_err(dev, "failed to get system reset control: %d\n", ret); 632 return ret; 633 } 634 635 phy = devm_phy_create(dev, NULL, &inno_dsidphy_ops); 636 if (IS_ERR(phy)) { 637 ret = PTR_ERR(phy); 638 dev_err(dev, "failed to create phy: %d\n", ret); 639 return ret; 640 } 641 642 phy_set_drvdata(phy, inno); 643 644 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 645 if (IS_ERR(phy_provider)) { 646 ret = PTR_ERR(phy_provider); 647 dev_err(dev, "failed to register phy provider: %d\n", ret); 648 return ret; 649 } 650 651 pm_runtime_enable(dev); 652 653 return 0; 654 } 655 656 static int inno_dsidphy_remove(struct platform_device *pdev) 657 { 658 struct inno_dsidphy *inno = platform_get_drvdata(pdev); 659 660 pm_runtime_disable(inno->dev); 661 662 return 0; 663 } 664 665 static const struct of_device_id inno_dsidphy_of_match[] = { 666 { .compatible = "rockchip,px30-dsi-dphy", }, 667 { .compatible = "rockchip,rk3128-dsi-dphy", }, 668 { .compatible = "rockchip,rk3368-dsi-dphy", }, 669 {} 670 }; 671 MODULE_DEVICE_TABLE(of, inno_dsidphy_of_match); 672 673 static struct platform_driver inno_dsidphy_driver = { 674 .driver = { 675 .name = "inno-dsidphy", 676 .of_match_table = of_match_ptr(inno_dsidphy_of_match), 677 }, 678 .probe = inno_dsidphy_probe, 679 .remove = inno_dsidphy_remove, 680 }; 681 module_platform_driver(inno_dsidphy_driver); 682 683 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>"); 684 MODULE_DESCRIPTION("Innosilicon MIPI/LVDS/TTL Video Combo PHY driver"); 685 MODULE_LICENSE("GPL v2"); 686