1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2018 Rockchip Electronics Co. Ltd. 4 * 5 * Author: Wyon Bi <bivvy.bi@rock-chips.com> 6 */ 7 8 #include <linux/kernel.h> 9 #include <linux/clk.h> 10 #include <linux/iopoll.h> 11 #include <linux/clk-provider.h> 12 #include <linux/delay.h> 13 #include <linux/init.h> 14 #include <linux/module.h> 15 #include <linux/of_device.h> 16 #include <linux/platform_device.h> 17 #include <linux/reset.h> 18 #include <linux/phy/phy.h> 19 #include <linux/pm_runtime.h> 20 #include <linux/mfd/syscon.h> 21 22 #define PSEC_PER_SEC 1000000000000LL 23 24 #define UPDATE(x, h, l) (((x) << (l)) & GENMASK((h), (l))) 25 26 /* 27 * The offset address[7:0] is distributed two parts, one from the bit7 to bit5 28 * is the first address, the other from the bit4 to bit0 is the second address. 29 * when you configure the registers, you must set both of them. The Clock Lane 30 * and Data Lane use the same registers with the same second address, but the 31 * first address is different. 32 */ 33 #define FIRST_ADDRESS(x) (((x) & 0x7) << 5) 34 #define SECOND_ADDRESS(x) (((x) & 0x1f) << 0) 35 #define PHY_REG(first, second) (FIRST_ADDRESS(first) | \ 36 SECOND_ADDRESS(second)) 37 38 /* Analog Register Part: reg00 */ 39 #define BANDGAP_POWER_MASK BIT(7) 40 #define BANDGAP_POWER_DOWN BIT(7) 41 #define BANDGAP_POWER_ON 0 42 #define LANE_EN_MASK GENMASK(6, 2) 43 #define LANE_EN_CK BIT(6) 44 #define LANE_EN_3 BIT(5) 45 #define LANE_EN_2 BIT(4) 46 #define LANE_EN_1 BIT(3) 47 #define LANE_EN_0 BIT(2) 48 #define POWER_WORK_MASK GENMASK(1, 0) 49 #define POWER_WORK_ENABLE UPDATE(1, 1, 0) 50 #define POWER_WORK_DISABLE UPDATE(2, 1, 0) 51 /* Analog Register Part: reg01 */ 52 #define REG_SYNCRST_MASK BIT(2) 53 #define REG_SYNCRST_RESET BIT(2) 54 #define REG_SYNCRST_NORMAL 0 55 #define REG_LDOPD_MASK BIT(1) 56 #define REG_LDOPD_POWER_DOWN BIT(1) 57 #define REG_LDOPD_POWER_ON 0 58 #define REG_PLLPD_MASK BIT(0) 59 #define REG_PLLPD_POWER_DOWN BIT(0) 60 #define REG_PLLPD_POWER_ON 0 61 /* Analog Register Part: reg03 */ 62 #define REG_FBDIV_HI_MASK BIT(5) 63 #define REG_FBDIV_HI(x) UPDATE((x >> 8), 5, 5) 64 #define REG_PREDIV_MASK GENMASK(4, 0) 65 #define REG_PREDIV(x) UPDATE(x, 4, 0) 66 /* Analog Register Part: reg04 */ 67 #define REG_FBDIV_LO_MASK GENMASK(7, 0) 68 #define REG_FBDIV_LO(x) UPDATE(x, 7, 0) 69 /* Analog Register Part: reg05 */ 70 #define SAMPLE_CLOCK_PHASE_MASK GENMASK(6, 4) 71 #define SAMPLE_CLOCK_PHASE(x) UPDATE(x, 6, 4) 72 #define CLOCK_LANE_SKEW_PHASE_MASK GENMASK(2, 0) 73 #define CLOCK_LANE_SKEW_PHASE(x) UPDATE(x, 2, 0) 74 /* Analog Register Part: reg06 */ 75 #define DATA_LANE_3_SKEW_PHASE_MASK GENMASK(6, 4) 76 #define DATA_LANE_3_SKEW_PHASE(x) UPDATE(x, 6, 4) 77 #define DATA_LANE_2_SKEW_PHASE_MASK GENMASK(2, 0) 78 #define DATA_LANE_2_SKEW_PHASE(x) UPDATE(x, 2, 0) 79 /* Analog Register Part: reg07 */ 80 #define DATA_LANE_1_SKEW_PHASE_MASK GENMASK(6, 4) 81 #define DATA_LANE_1_SKEW_PHASE(x) UPDATE(x, 6, 4) 82 #define DATA_LANE_0_SKEW_PHASE_MASK GENMASK(2, 0) 83 #define DATA_LANE_0_SKEW_PHASE(x) UPDATE(x, 2, 0) 84 /* Analog Register Part: reg08 */ 85 #define SAMPLE_CLOCK_DIRECTION_MASK BIT(4) 86 #define SAMPLE_CLOCK_DIRECTION_REVERSE BIT(4) 87 #define SAMPLE_CLOCK_DIRECTION_FORWARD 0 88 /* Digital Register Part: reg00 */ 89 #define REG_DIG_RSTN_MASK BIT(0) 90 #define REG_DIG_RSTN_NORMAL BIT(0) 91 #define REG_DIG_RSTN_RESET 0 92 /* Digital Register Part: reg01 */ 93 #define INVERT_TXCLKESC_MASK BIT(1) 94 #define INVERT_TXCLKESC_ENABLE BIT(1) 95 #define INVERT_TXCLKESC_DISABLE 0 96 #define INVERT_TXBYTECLKHS_MASK BIT(0) 97 #define INVERT_TXBYTECLKHS_ENABLE BIT(0) 98 #define INVERT_TXBYTECLKHS_DISABLE 0 99 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg05 */ 100 #define T_LPX_CNT_MASK GENMASK(5, 0) 101 #define T_LPX_CNT(x) UPDATE(x, 5, 0) 102 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg06 */ 103 #define T_HS_PREPARE_CNT_MASK GENMASK(6, 0) 104 #define T_HS_PREPARE_CNT(x) UPDATE(x, 6, 0) 105 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg07 */ 106 #define T_HS_ZERO_CNT_MASK GENMASK(5, 0) 107 #define T_HS_ZERO_CNT(x) UPDATE(x, 5, 0) 108 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg08 */ 109 #define T_HS_TRAIL_CNT_MASK GENMASK(6, 0) 110 #define T_HS_TRAIL_CNT(x) UPDATE(x, 6, 0) 111 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg09 */ 112 #define T_HS_EXIT_CNT_MASK GENMASK(4, 0) 113 #define T_HS_EXIT_CNT(x) UPDATE(x, 4, 0) 114 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0a */ 115 #define T_CLK_POST_CNT_MASK GENMASK(3, 0) 116 #define T_CLK_POST_CNT(x) UPDATE(x, 3, 0) 117 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0c */ 118 #define LPDT_TX_PPI_SYNC_MASK BIT(2) 119 #define LPDT_TX_PPI_SYNC_ENABLE BIT(2) 120 #define LPDT_TX_PPI_SYNC_DISABLE 0 121 #define T_WAKEUP_CNT_HI_MASK GENMASK(1, 0) 122 #define T_WAKEUP_CNT_HI(x) UPDATE(x, 1, 0) 123 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0d */ 124 #define T_WAKEUP_CNT_LO_MASK GENMASK(7, 0) 125 #define T_WAKEUP_CNT_LO(x) UPDATE(x, 7, 0) 126 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg0e */ 127 #define T_CLK_PRE_CNT_MASK GENMASK(3, 0) 128 #define T_CLK_PRE_CNT(x) UPDATE(x, 3, 0) 129 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg10 */ 130 #define T_TA_GO_CNT_MASK GENMASK(5, 0) 131 #define T_TA_GO_CNT(x) UPDATE(x, 5, 0) 132 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg11 */ 133 #define T_TA_SURE_CNT_MASK GENMASK(5, 0) 134 #define T_TA_SURE_CNT(x) UPDATE(x, 5, 0) 135 /* Clock/Data0/Data1/Data2/Data3 Lane Register Part: reg12 */ 136 #define T_TA_WAIT_CNT_MASK GENMASK(5, 0) 137 #define T_TA_WAIT_CNT(x) UPDATE(x, 5, 0) 138 /* LVDS Register Part: reg00 */ 139 #define LVDS_DIGITAL_INTERNAL_RESET_MASK BIT(2) 140 #define LVDS_DIGITAL_INTERNAL_RESET_DISABLE BIT(2) 141 #define LVDS_DIGITAL_INTERNAL_RESET_ENABLE 0 142 /* LVDS Register Part: reg01 */ 143 #define LVDS_DIGITAL_INTERNAL_ENABLE_MASK BIT(7) 144 #define LVDS_DIGITAL_INTERNAL_ENABLE BIT(7) 145 #define LVDS_DIGITAL_INTERNAL_DISABLE 0 146 /* LVDS Register Part: reg03 */ 147 #define MODE_ENABLE_MASK GENMASK(2, 0) 148 #define TTL_MODE_ENABLE BIT(2) 149 #define LVDS_MODE_ENABLE BIT(1) 150 #define MIPI_MODE_ENABLE BIT(0) 151 /* LVDS Register Part: reg0b */ 152 #define LVDS_LANE_EN_MASK GENMASK(7, 3) 153 #define LVDS_DATA_LANE0_EN BIT(7) 154 #define LVDS_DATA_LANE1_EN BIT(6) 155 #define LVDS_DATA_LANE2_EN BIT(5) 156 #define LVDS_DATA_LANE3_EN BIT(4) 157 #define LVDS_CLK_LANE_EN BIT(3) 158 #define LVDS_PLL_POWER_MASK BIT(2) 159 #define LVDS_PLL_POWER_OFF BIT(2) 160 #define LVDS_PLL_POWER_ON 0 161 #define LVDS_BANDGAP_POWER_MASK BIT(0) 162 #define LVDS_BANDGAP_POWER_DOWN BIT(0) 163 #define LVDS_BANDGAP_POWER_ON 0 164 165 #define DSI_PHY_RSTZ 0xa0 166 #define PHY_ENABLECLK BIT(2) 167 #define DSI_PHY_STATUS 0xb0 168 #define PHY_LOCK BIT(0) 169 170 struct mipi_dphy_timing { 171 unsigned int clkmiss; 172 unsigned int clkpost; 173 unsigned int clkpre; 174 unsigned int clkprepare; 175 unsigned int clksettle; 176 unsigned int clktermen; 177 unsigned int clktrail; 178 unsigned int clkzero; 179 unsigned int dtermen; 180 unsigned int eot; 181 unsigned int hsexit; 182 unsigned int hsprepare; 183 unsigned int hszero; 184 unsigned int hssettle; 185 unsigned int hsskip; 186 unsigned int hstrail; 187 unsigned int init; 188 unsigned int lpx; 189 unsigned int taget; 190 unsigned int tago; 191 unsigned int tasure; 192 unsigned int wakeup; 193 }; 194 195 struct inno_dsidphy { 196 struct device *dev; 197 struct clk *ref_clk; 198 struct clk *pclk_phy; 199 struct clk *pclk_host; 200 void __iomem *phy_base; 201 void __iomem *host_base; 202 struct reset_control *rst; 203 enum phy_mode mode; 204 205 struct { 206 struct clk_hw hw; 207 u8 prediv; 208 u16 fbdiv; 209 unsigned long rate; 210 } pll; 211 }; 212 213 enum { 214 REGISTER_PART_ANALOG, 215 REGISTER_PART_DIGITAL, 216 REGISTER_PART_CLOCK_LANE, 217 REGISTER_PART_DATA0_LANE, 218 REGISTER_PART_DATA1_LANE, 219 REGISTER_PART_DATA2_LANE, 220 REGISTER_PART_DATA3_LANE, 221 REGISTER_PART_LVDS, 222 }; 223 224 static inline struct inno_dsidphy *hw_to_inno(struct clk_hw *hw) 225 { 226 return container_of(hw, struct inno_dsidphy, pll.hw); 227 } 228 229 static void phy_update_bits(struct inno_dsidphy *inno, 230 u8 first, u8 second, u8 mask, u8 val) 231 { 232 u32 reg = PHY_REG(first, second) << 2; 233 unsigned int tmp, orig; 234 235 orig = readl(inno->phy_base + reg); 236 tmp = orig & ~mask; 237 tmp |= val & mask; 238 writel(tmp, inno->phy_base + reg); 239 } 240 241 static void mipi_dphy_timing_get_default(struct mipi_dphy_timing *timing, 242 unsigned long period) 243 { 244 /* Global Operation Timing Parameters */ 245 timing->clkmiss = 0; 246 timing->clkpost = 70000 + 52 * period; 247 timing->clkpre = 8 * period; 248 timing->clkprepare = 65000; 249 timing->clksettle = 95000; 250 timing->clktermen = 0; 251 timing->clktrail = 80000; 252 timing->clkzero = 260000; 253 timing->dtermen = 0; 254 timing->eot = 0; 255 timing->hsexit = 120000; 256 timing->hsprepare = 65000 + 4 * period; 257 timing->hszero = 145000 + 6 * period; 258 timing->hssettle = 85000 + 6 * period; 259 timing->hsskip = 40000; 260 timing->hstrail = max(8 * period, 60000 + 4 * period); 261 timing->init = 100000000; 262 timing->lpx = 60000; 263 timing->taget = 5 * timing->lpx; 264 timing->tago = 4 * timing->lpx; 265 timing->tasure = 2 * timing->lpx; 266 timing->wakeup = 1000000000; 267 } 268 269 static void inno_dsidphy_mipi_mode_enable(struct inno_dsidphy *inno) 270 { 271 struct mipi_dphy_timing gotp; 272 const struct { 273 unsigned long rate; 274 u8 hs_prepare; 275 u8 clk_lane_hs_zero; 276 u8 data_lane_hs_zero; 277 u8 hs_trail; 278 } timings[] = { 279 { 110000000, 0x20, 0x16, 0x02, 0x22}, 280 { 150000000, 0x06, 0x16, 0x03, 0x45}, 281 { 200000000, 0x18, 0x17, 0x04, 0x0b}, 282 { 250000000, 0x05, 0x17, 0x05, 0x16}, 283 { 300000000, 0x51, 0x18, 0x06, 0x2c}, 284 { 400000000, 0x64, 0x19, 0x07, 0x33}, 285 { 500000000, 0x20, 0x1b, 0x07, 0x4e}, 286 { 600000000, 0x6a, 0x1d, 0x08, 0x3a}, 287 { 700000000, 0x3e, 0x1e, 0x08, 0x6a}, 288 { 800000000, 0x21, 0x1f, 0x09, 0x29}, 289 {1000000000, 0x09, 0x20, 0x09, 0x27}, 290 }; 291 u32 t_txbyteclkhs, t_txclkesc, ui; 292 u32 txbyteclkhs, txclkesc, esc_clk_div; 293 u32 hs_exit, clk_post, clk_pre, wakeup, lpx, ta_go, ta_sure, ta_wait; 294 u32 hs_prepare, hs_trail, hs_zero, clk_lane_hs_zero, data_lane_hs_zero; 295 unsigned int i; 296 297 /* Select MIPI mode */ 298 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 299 MODE_ENABLE_MASK, MIPI_MODE_ENABLE); 300 /* Configure PLL */ 301 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 302 REG_PREDIV_MASK, REG_PREDIV(inno->pll.prediv)); 303 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 304 REG_FBDIV_HI_MASK, REG_FBDIV_HI(inno->pll.fbdiv)); 305 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, 306 REG_FBDIV_LO_MASK, REG_FBDIV_LO(inno->pll.fbdiv)); 307 /* Enable PLL and LDO */ 308 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 309 REG_LDOPD_MASK | REG_PLLPD_MASK, 310 REG_LDOPD_POWER_ON | REG_PLLPD_POWER_ON); 311 /* Reset analog */ 312 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 313 REG_SYNCRST_MASK, REG_SYNCRST_RESET); 314 udelay(1); 315 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 316 REG_SYNCRST_MASK, REG_SYNCRST_NORMAL); 317 /* Reset digital */ 318 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, 319 REG_DIG_RSTN_MASK, REG_DIG_RSTN_RESET); 320 udelay(1); 321 phy_update_bits(inno, REGISTER_PART_DIGITAL, 0x00, 322 REG_DIG_RSTN_MASK, REG_DIG_RSTN_NORMAL); 323 324 txbyteclkhs = inno->pll.rate / 8; 325 t_txbyteclkhs = div_u64(PSEC_PER_SEC, txbyteclkhs); 326 327 esc_clk_div = DIV_ROUND_UP(txbyteclkhs, 20000000); 328 txclkesc = txbyteclkhs / esc_clk_div; 329 t_txclkesc = div_u64(PSEC_PER_SEC, txclkesc); 330 331 ui = div_u64(PSEC_PER_SEC, inno->pll.rate); 332 333 memset(&gotp, 0, sizeof(gotp)); 334 mipi_dphy_timing_get_default(&gotp, ui); 335 336 /* 337 * The value of counter for HS Ths-exit 338 * Ths-exit = Tpin_txbyteclkhs * value 339 */ 340 hs_exit = DIV_ROUND_UP(gotp.hsexit, t_txbyteclkhs); 341 /* 342 * The value of counter for HS Tclk-post 343 * Tclk-post = Tpin_txbyteclkhs * value 344 */ 345 clk_post = DIV_ROUND_UP(gotp.clkpost, t_txbyteclkhs); 346 /* 347 * The value of counter for HS Tclk-pre 348 * Tclk-pre = Tpin_txbyteclkhs * value 349 */ 350 clk_pre = DIV_ROUND_UP(gotp.clkpre, t_txbyteclkhs); 351 352 /* 353 * The value of counter for HS Tlpx Time 354 * Tlpx = Tpin_txbyteclkhs * (2 + value) 355 */ 356 lpx = DIV_ROUND_UP(gotp.lpx, t_txbyteclkhs); 357 if (lpx >= 2) 358 lpx -= 2; 359 360 /* 361 * The value of counter for HS Tta-go 362 * Tta-go for turnaround 363 * Tta-go = Ttxclkesc * value 364 */ 365 ta_go = DIV_ROUND_UP(gotp.tago, t_txclkesc); 366 /* 367 * The value of counter for HS Tta-sure 368 * Tta-sure for turnaround 369 * Tta-sure = Ttxclkesc * value 370 */ 371 ta_sure = DIV_ROUND_UP(gotp.tasure, t_txclkesc); 372 /* 373 * The value of counter for HS Tta-wait 374 * Tta-wait for turnaround 375 * Tta-wait = Ttxclkesc * value 376 */ 377 ta_wait = DIV_ROUND_UP(gotp.taget, t_txclkesc); 378 379 for (i = 0; i < ARRAY_SIZE(timings); i++) 380 if (inno->pll.rate <= timings[i].rate) 381 break; 382 383 if (i == ARRAY_SIZE(timings)) 384 --i; 385 386 hs_prepare = timings[i].hs_prepare; 387 hs_trail = timings[i].hs_trail; 388 clk_lane_hs_zero = timings[i].clk_lane_hs_zero; 389 data_lane_hs_zero = timings[i].data_lane_hs_zero; 390 wakeup = 0x3ff; 391 392 for (i = REGISTER_PART_CLOCK_LANE; i <= REGISTER_PART_DATA3_LANE; i++) { 393 if (i == REGISTER_PART_CLOCK_LANE) 394 hs_zero = clk_lane_hs_zero; 395 else 396 hs_zero = data_lane_hs_zero; 397 398 phy_update_bits(inno, i, 0x05, T_LPX_CNT_MASK, 399 T_LPX_CNT(lpx)); 400 phy_update_bits(inno, i, 0x06, T_HS_PREPARE_CNT_MASK, 401 T_HS_PREPARE_CNT(hs_prepare)); 402 phy_update_bits(inno, i, 0x07, T_HS_ZERO_CNT_MASK, 403 T_HS_ZERO_CNT(hs_zero)); 404 phy_update_bits(inno, i, 0x08, T_HS_TRAIL_CNT_MASK, 405 T_HS_TRAIL_CNT(hs_trail)); 406 phy_update_bits(inno, i, 0x09, T_HS_EXIT_CNT_MASK, 407 T_HS_EXIT_CNT(hs_exit)); 408 phy_update_bits(inno, i, 0x0a, T_CLK_POST_CNT_MASK, 409 T_CLK_POST_CNT(clk_post)); 410 phy_update_bits(inno, i, 0x0e, T_CLK_PRE_CNT_MASK, 411 T_CLK_PRE_CNT(clk_pre)); 412 phy_update_bits(inno, i, 0x0c, T_WAKEUP_CNT_HI_MASK, 413 T_WAKEUP_CNT_HI(wakeup >> 8)); 414 phy_update_bits(inno, i, 0x0d, T_WAKEUP_CNT_LO_MASK, 415 T_WAKEUP_CNT_LO(wakeup)); 416 phy_update_bits(inno, i, 0x10, T_TA_GO_CNT_MASK, 417 T_TA_GO_CNT(ta_go)); 418 phy_update_bits(inno, i, 0x11, T_TA_SURE_CNT_MASK, 419 T_TA_SURE_CNT(ta_sure)); 420 phy_update_bits(inno, i, 0x12, T_TA_WAIT_CNT_MASK, 421 T_TA_WAIT_CNT(ta_wait)); 422 } 423 424 /* Enable all lanes on analog part */ 425 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 426 LANE_EN_MASK, LANE_EN_CK | LANE_EN_3 | LANE_EN_2 | 427 LANE_EN_1 | LANE_EN_0); 428 } 429 430 static void inno_dsidphy_lvds_mode_enable(struct inno_dsidphy *inno) 431 { 432 u8 prediv = 2; 433 u16 fbdiv = 28; 434 435 /* Sample clock reverse direction */ 436 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x08, 437 SAMPLE_CLOCK_DIRECTION_MASK, 438 SAMPLE_CLOCK_DIRECTION_REVERSE); 439 440 /* Select LVDS mode */ 441 phy_update_bits(inno, REGISTER_PART_LVDS, 0x03, 442 MODE_ENABLE_MASK, LVDS_MODE_ENABLE); 443 /* Configure PLL */ 444 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 445 REG_PREDIV_MASK, REG_PREDIV(prediv)); 446 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x03, 447 REG_FBDIV_HI_MASK, REG_FBDIV_HI(fbdiv)); 448 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x04, 449 REG_FBDIV_LO_MASK, REG_FBDIV_LO(fbdiv)); 450 phy_update_bits(inno, REGISTER_PART_LVDS, 0x08, 0xff, 0xfc); 451 /* Enable PLL and Bandgap */ 452 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 453 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, 454 LVDS_PLL_POWER_ON | LVDS_BANDGAP_POWER_ON); 455 456 msleep(20); 457 458 /* Reset LVDS digital logic */ 459 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 460 LVDS_DIGITAL_INTERNAL_RESET_MASK, 461 LVDS_DIGITAL_INTERNAL_RESET_ENABLE); 462 udelay(1); 463 phy_update_bits(inno, REGISTER_PART_LVDS, 0x00, 464 LVDS_DIGITAL_INTERNAL_RESET_MASK, 465 LVDS_DIGITAL_INTERNAL_RESET_DISABLE); 466 /* Enable LVDS digital logic */ 467 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 468 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 469 LVDS_DIGITAL_INTERNAL_ENABLE); 470 /* Enable LVDS analog driver */ 471 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 472 LVDS_LANE_EN_MASK, LVDS_CLK_LANE_EN | 473 LVDS_DATA_LANE0_EN | LVDS_DATA_LANE1_EN | 474 LVDS_DATA_LANE2_EN | LVDS_DATA_LANE3_EN); 475 } 476 477 static int inno_dsidphy_power_on(struct phy *phy) 478 { 479 struct inno_dsidphy *inno = phy_get_drvdata(phy); 480 481 clk_prepare_enable(inno->pclk_phy); 482 pm_runtime_get_sync(inno->dev); 483 484 /* Bandgap power on */ 485 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 486 BANDGAP_POWER_MASK, BANDGAP_POWER_ON); 487 /* Enable power work */ 488 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 489 POWER_WORK_MASK, POWER_WORK_ENABLE); 490 491 switch (inno->mode) { 492 case PHY_MODE_MIPI_DPHY: 493 inno_dsidphy_mipi_mode_enable(inno); 494 break; 495 case PHY_MODE_LVDS: 496 inno_dsidphy_lvds_mode_enable(inno); 497 break; 498 default: 499 return -EINVAL; 500 } 501 502 return 0; 503 } 504 505 static int inno_dsidphy_power_off(struct phy *phy) 506 { 507 struct inno_dsidphy *inno = phy_get_drvdata(phy); 508 509 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, LANE_EN_MASK, 0); 510 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x01, 511 REG_LDOPD_MASK | REG_PLLPD_MASK, 512 REG_LDOPD_POWER_DOWN | REG_PLLPD_POWER_DOWN); 513 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 514 POWER_WORK_MASK, POWER_WORK_DISABLE); 515 phy_update_bits(inno, REGISTER_PART_ANALOG, 0x00, 516 BANDGAP_POWER_MASK, BANDGAP_POWER_DOWN); 517 518 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, LVDS_LANE_EN_MASK, 0); 519 phy_update_bits(inno, REGISTER_PART_LVDS, 0x01, 520 LVDS_DIGITAL_INTERNAL_ENABLE_MASK, 521 LVDS_DIGITAL_INTERNAL_DISABLE); 522 phy_update_bits(inno, REGISTER_PART_LVDS, 0x0b, 523 LVDS_PLL_POWER_MASK | LVDS_BANDGAP_POWER_MASK, 524 LVDS_PLL_POWER_OFF | LVDS_BANDGAP_POWER_DOWN); 525 526 pm_runtime_put(inno->dev); 527 clk_disable_unprepare(inno->pclk_phy); 528 529 return 0; 530 } 531 532 static int inno_dsidphy_set_mode(struct phy *phy, enum phy_mode mode, 533 int submode) 534 { 535 struct inno_dsidphy *inno = phy_get_drvdata(phy); 536 537 switch (mode) { 538 case PHY_MODE_MIPI_DPHY: 539 case PHY_MODE_LVDS: 540 inno->mode = mode; 541 break; 542 default: 543 return -EINVAL; 544 } 545 546 return 0; 547 } 548 549 static const struct phy_ops inno_dsidphy_ops = { 550 .set_mode = inno_dsidphy_set_mode, 551 .power_on = inno_dsidphy_power_on, 552 .power_off = inno_dsidphy_power_off, 553 .owner = THIS_MODULE, 554 }; 555 556 static unsigned long inno_dsidphy_pll_round_rate(struct inno_dsidphy *inno, 557 unsigned long prate, 558 unsigned long rate, 559 u8 *prediv, u16 *fbdiv) 560 { 561 unsigned long best_freq = 0; 562 unsigned long fref, fout; 563 u8 min_prediv, max_prediv; 564 u8 _prediv, best_prediv = 1; 565 u16 _fbdiv, best_fbdiv = 1; 566 u32 min_delta = UINT_MAX; 567 568 /* 569 * The PLL output frequency can be calculated using a simple formula: 570 * PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2 571 * PLL_Output_Frequency: it is equal to DDR-Clock-Frequency * 2 572 */ 573 fref = prate / 2; 574 if (rate > 1000000000UL) 575 fout = 1000000000UL; 576 else 577 fout = rate; 578 579 /* 5Mhz < Fref / prediv < 40MHz */ 580 min_prediv = DIV_ROUND_UP(fref, 40000000); 581 max_prediv = fref / 5000000; 582 583 for (_prediv = min_prediv; _prediv <= max_prediv; _prediv++) { 584 u64 tmp; 585 u32 delta; 586 587 tmp = (u64)fout * _prediv; 588 do_div(tmp, fref); 589 _fbdiv = tmp; 590 591 /* 592 * The possible settings of feedback divider are 593 * 12, 13, 14, 16, ~ 511 594 */ 595 if (_fbdiv == 15) 596 continue; 597 598 if (_fbdiv < 12 || _fbdiv > 511) 599 continue; 600 601 tmp = (u64)_fbdiv * fref; 602 do_div(tmp, _prediv); 603 604 delta = abs(fout - tmp); 605 if (!delta) { 606 best_prediv = _prediv; 607 best_fbdiv = _fbdiv; 608 best_freq = tmp; 609 break; 610 } else if (delta < min_delta) { 611 best_prediv = _prediv; 612 best_fbdiv = _fbdiv; 613 best_freq = tmp; 614 min_delta = delta; 615 } 616 } 617 618 if (best_freq) { 619 *prediv = best_prediv; 620 *fbdiv = best_fbdiv; 621 } 622 623 return best_freq; 624 } 625 626 static long inno_dsidphy_pll_clk_round_rate(struct clk_hw *hw, 627 unsigned long rate, 628 unsigned long *prate) 629 { 630 struct inno_dsidphy *inno = hw_to_inno(hw); 631 unsigned long fout; 632 u16 fbdiv = 1; 633 u8 prediv = 1; 634 635 fout = inno_dsidphy_pll_round_rate(inno, *prate, rate, 636 &prediv, &fbdiv); 637 638 return fout; 639 } 640 641 static int inno_dsidphy_pll_clk_set_rate(struct clk_hw *hw, 642 unsigned long rate, 643 unsigned long parent_rate) 644 { 645 struct inno_dsidphy *inno = hw_to_inno(hw); 646 unsigned long fout; 647 u16 fbdiv = 1; 648 u8 prediv = 1; 649 650 fout = inno_dsidphy_pll_round_rate(inno, parent_rate, rate, 651 &prediv, &fbdiv); 652 653 dev_dbg(inno->dev, "fin=%lu, fout=%lu, prediv=%u, fbdiv=%u\n", 654 parent_rate, fout, prediv, fbdiv); 655 656 inno->pll.prediv = prediv; 657 inno->pll.fbdiv = fbdiv; 658 inno->pll.rate = fout; 659 660 return 0; 661 } 662 663 static unsigned long 664 inno_dsidphy_pll_clk_recalc_rate(struct clk_hw *hw, unsigned long prate) 665 { 666 struct inno_dsidphy *inno = hw_to_inno(hw); 667 668 /* PLL_Output_Frequency = (FREF / PREDIV * FBDIV) / 2 */ 669 return (prate / inno->pll.prediv * inno->pll.fbdiv) / 2; 670 } 671 672 static const struct clk_ops inno_dsidphy_pll_clk_ops = { 673 .round_rate = inno_dsidphy_pll_clk_round_rate, 674 .set_rate = inno_dsidphy_pll_clk_set_rate, 675 .recalc_rate = inno_dsidphy_pll_clk_recalc_rate, 676 }; 677 678 static int inno_dsidphy_pll_register(struct inno_dsidphy *inno) 679 { 680 struct device *dev = inno->dev; 681 struct clk *clk; 682 const char *parent_name; 683 struct clk_init_data init; 684 int ret; 685 686 parent_name = __clk_get_name(inno->ref_clk); 687 688 init.name = "mipi_dphy_pll"; 689 ret = of_property_read_string(dev->of_node, "clock-output-names", 690 &init.name); 691 if (ret < 0) 692 dev_dbg(dev, "phy should set clock-output-names property\n"); 693 694 init.ops = &inno_dsidphy_pll_clk_ops; 695 init.parent_names = &parent_name; 696 init.num_parents = 1; 697 init.flags = 0; 698 699 inno->pll.hw.init = &init; 700 clk = devm_clk_register(dev, &inno->pll.hw); 701 if (IS_ERR(clk)) { 702 ret = PTR_ERR(clk); 703 dev_err(dev, "failed to register PLL: %d\n", ret); 704 return ret; 705 } 706 707 return devm_of_clk_add_hw_provider(dev, of_clk_hw_simple_get, 708 &inno->pll.hw); 709 } 710 711 static int inno_dsidphy_probe(struct platform_device *pdev) 712 { 713 struct device *dev = &pdev->dev; 714 struct inno_dsidphy *inno; 715 struct phy_provider *phy_provider; 716 struct phy *phy; 717 int ret; 718 719 inno = devm_kzalloc(dev, sizeof(*inno), GFP_KERNEL); 720 if (!inno) 721 return -ENOMEM; 722 723 inno->dev = dev; 724 platform_set_drvdata(pdev, inno); 725 726 inno->phy_base = devm_platform_ioremap_resource(pdev, 0); 727 if (!inno->phy_base) 728 return -ENOMEM; 729 730 inno->ref_clk = devm_clk_get(dev, "ref"); 731 if (IS_ERR(inno->ref_clk)) { 732 ret = PTR_ERR(inno->ref_clk); 733 dev_err(dev, "failed to get ref clock: %d\n", ret); 734 return ret; 735 } 736 737 inno->pclk_phy = devm_clk_get(dev, "pclk"); 738 if (IS_ERR(inno->pclk_phy)) { 739 ret = PTR_ERR(inno->pclk_phy); 740 dev_err(dev, "failed to get phy pclk: %d\n", ret); 741 return ret; 742 } 743 744 inno->rst = devm_reset_control_get(dev, "apb"); 745 if (IS_ERR(inno->rst)) { 746 ret = PTR_ERR(inno->rst); 747 dev_err(dev, "failed to get system reset control: %d\n", ret); 748 return ret; 749 } 750 751 phy = devm_phy_create(dev, NULL, &inno_dsidphy_ops); 752 if (IS_ERR(phy)) { 753 ret = PTR_ERR(phy); 754 dev_err(dev, "failed to create phy: %d\n", ret); 755 return ret; 756 } 757 758 phy_set_drvdata(phy, inno); 759 760 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 761 if (IS_ERR(phy_provider)) { 762 ret = PTR_ERR(phy_provider); 763 dev_err(dev, "failed to register phy provider: %d\n", ret); 764 return ret; 765 } 766 767 ret = inno_dsidphy_pll_register(inno); 768 if (ret) 769 return ret; 770 771 pm_runtime_enable(dev); 772 773 return 0; 774 } 775 776 static int inno_dsidphy_remove(struct platform_device *pdev) 777 { 778 struct inno_dsidphy *inno = platform_get_drvdata(pdev); 779 780 pm_runtime_disable(inno->dev); 781 782 return 0; 783 } 784 785 static const struct of_device_id inno_dsidphy_of_match[] = { 786 { .compatible = "rockchip,px30-dsi-dphy", }, 787 { .compatible = "rockchip,rk3128-dsi-dphy", }, 788 { .compatible = "rockchip,rk3368-dsi-dphy", }, 789 {} 790 }; 791 MODULE_DEVICE_TABLE(of, inno_dsidphy_of_match); 792 793 static struct platform_driver inno_dsidphy_driver = { 794 .driver = { 795 .name = "inno-dsidphy", 796 .of_match_table = of_match_ptr(inno_dsidphy_of_match), 797 }, 798 .probe = inno_dsidphy_probe, 799 .remove = inno_dsidphy_remove, 800 }; 801 module_platform_driver(inno_dsidphy_driver); 802 803 MODULE_AUTHOR("Wyon Bi <bivvy.bi@rock-chips.com>"); 804 MODULE_DESCRIPTION("Innosilicon MIPI/LVDS/TTL Video Combo PHY driver"); 805 MODULE_LICENSE("GPL v2"); 806