1 // SPDX-License-Identifier: GPL-2.0-only 2 /* 3 * Rockchip emmc PHY driver 4 * 5 * Copyright (C) 2016 Shawn Lin <shawn.lin@rock-chips.com> 6 * Copyright (C) 2016 ROCKCHIP, Inc. 7 */ 8 9 #include <linux/clk.h> 10 #include <linux/delay.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/of.h> 14 #include <linux/of_address.h> 15 #include <linux/phy/phy.h> 16 #include <linux/platform_device.h> 17 #include <linux/regmap.h> 18 19 /* 20 * The higher 16-bit of this register is used for write protection 21 * only if BIT(x + 16) set to 1 the BIT(x) can be written. 22 */ 23 #define HIWORD_UPDATE(val, mask, shift) \ 24 ((val) << (shift) | (mask) << ((shift) + 16)) 25 26 /* Register definition */ 27 #define GRF_EMMCPHY_CON0 0x0 28 #define GRF_EMMCPHY_CON1 0x4 29 #define GRF_EMMCPHY_CON2 0x8 30 #define GRF_EMMCPHY_CON3 0xc 31 #define GRF_EMMCPHY_CON4 0x10 32 #define GRF_EMMCPHY_CON5 0x14 33 #define GRF_EMMCPHY_CON6 0x18 34 #define GRF_EMMCPHY_STATUS 0x20 35 36 #define PHYCTRL_PDB_MASK 0x1 37 #define PHYCTRL_PDB_SHIFT 0x0 38 #define PHYCTRL_PDB_PWR_ON 0x1 39 #define PHYCTRL_PDB_PWR_OFF 0x0 40 #define PHYCTRL_ENDLL_MASK 0x1 41 #define PHYCTRL_ENDLL_SHIFT 0x1 42 #define PHYCTRL_ENDLL_ENABLE 0x1 43 #define PHYCTRL_ENDLL_DISABLE 0x0 44 #define PHYCTRL_CALDONE_MASK 0x1 45 #define PHYCTRL_CALDONE_SHIFT 0x6 46 #define PHYCTRL_CALDONE_DONE 0x1 47 #define PHYCTRL_CALDONE_GOING 0x0 48 #define PHYCTRL_DLLRDY_MASK 0x1 49 #define PHYCTRL_DLLRDY_SHIFT 0x5 50 #define PHYCTRL_DLLRDY_DONE 0x1 51 #define PHYCTRL_DLLRDY_GOING 0x0 52 #define PHYCTRL_FREQSEL_200M 0x0 53 #define PHYCTRL_FREQSEL_50M 0x1 54 #define PHYCTRL_FREQSEL_100M 0x2 55 #define PHYCTRL_FREQSEL_150M 0x3 56 #define PHYCTRL_FREQSEL_MASK 0x3 57 #define PHYCTRL_FREQSEL_SHIFT 0xc 58 #define PHYCTRL_DR_MASK 0x7 59 #define PHYCTRL_DR_SHIFT 0x4 60 #define PHYCTRL_DR_50OHM 0x0 61 #define PHYCTRL_DR_33OHM 0x1 62 #define PHYCTRL_DR_66OHM 0x2 63 #define PHYCTRL_DR_100OHM 0x3 64 #define PHYCTRL_DR_40OHM 0x4 65 #define PHYCTRL_OTAPDLYENA 0x1 66 #define PHYCTRL_OTAPDLYENA_MASK 0x1 67 #define PHYCTRL_OTAPDLYENA_SHIFT 0xb 68 #define PHYCTRL_OTAPDLYSEL_MASK 0xf 69 #define PHYCTRL_OTAPDLYSEL_SHIFT 0x7 70 71 #define PHYCTRL_IS_CALDONE(x) \ 72 ((((x) >> PHYCTRL_CALDONE_SHIFT) & \ 73 PHYCTRL_CALDONE_MASK) == PHYCTRL_CALDONE_DONE) 74 #define PHYCTRL_IS_DLLRDY(x) \ 75 ((((x) >> PHYCTRL_DLLRDY_SHIFT) & \ 76 PHYCTRL_DLLRDY_MASK) == PHYCTRL_DLLRDY_DONE) 77 78 struct rockchip_emmc_phy { 79 unsigned int reg_offset; 80 struct regmap *reg_base; 81 struct clk *emmcclk; 82 unsigned int drive_impedance; 83 }; 84 85 static int rockchip_emmc_phy_power(struct phy *phy, bool on_off) 86 { 87 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); 88 unsigned int caldone; 89 unsigned int dllrdy; 90 unsigned int freqsel = PHYCTRL_FREQSEL_200M; 91 unsigned long rate; 92 int ret; 93 94 /* 95 * Keep phyctrl_pdb and phyctrl_endll low to allow 96 * initialization of CALIO state M/C DFFs 97 */ 98 regmap_write(rk_phy->reg_base, 99 rk_phy->reg_offset + GRF_EMMCPHY_CON6, 100 HIWORD_UPDATE(PHYCTRL_PDB_PWR_OFF, 101 PHYCTRL_PDB_MASK, 102 PHYCTRL_PDB_SHIFT)); 103 regmap_write(rk_phy->reg_base, 104 rk_phy->reg_offset + GRF_EMMCPHY_CON6, 105 HIWORD_UPDATE(PHYCTRL_ENDLL_DISABLE, 106 PHYCTRL_ENDLL_MASK, 107 PHYCTRL_ENDLL_SHIFT)); 108 109 /* Already finish power_off above */ 110 if (on_off == PHYCTRL_PDB_PWR_OFF) 111 return 0; 112 113 rate = clk_get_rate(rk_phy->emmcclk); 114 115 if (rate != 0) { 116 unsigned long ideal_rate; 117 unsigned long diff; 118 119 switch (rate) { 120 case 1 ... 74999999: 121 ideal_rate = 50000000; 122 freqsel = PHYCTRL_FREQSEL_50M; 123 break; 124 case 75000000 ... 124999999: 125 ideal_rate = 100000000; 126 freqsel = PHYCTRL_FREQSEL_100M; 127 break; 128 case 125000000 ... 174999999: 129 ideal_rate = 150000000; 130 freqsel = PHYCTRL_FREQSEL_150M; 131 break; 132 default: 133 ideal_rate = 200000000; 134 break; 135 } 136 137 diff = (rate > ideal_rate) ? 138 rate - ideal_rate : ideal_rate - rate; 139 140 /* 141 * In order for tuning delays to be accurate we need to be 142 * pretty spot on for the DLL range, so warn if we're too 143 * far off. Also warn if we're above the 200 MHz max. Don't 144 * warn for really slow rates since we won't be tuning then. 145 */ 146 if ((rate > 50000000 && diff > 15000000) || (rate > 200000000)) 147 dev_warn(&phy->dev, "Unsupported rate: %lu\n", rate); 148 } 149 150 /* 151 * According to the user manual, calpad calibration 152 * cycle takes more than 2us without the minimal recommended 153 * value, so we may need a little margin here 154 */ 155 udelay(3); 156 regmap_write(rk_phy->reg_base, 157 rk_phy->reg_offset + GRF_EMMCPHY_CON6, 158 HIWORD_UPDATE(PHYCTRL_PDB_PWR_ON, 159 PHYCTRL_PDB_MASK, 160 PHYCTRL_PDB_SHIFT)); 161 162 /* 163 * According to the user manual, it asks driver to wait 5us for 164 * calpad busy trimming. However it is documented that this value is 165 * PVT(A.K.A process,voltage and temperature) relevant, so some 166 * failure cases are found which indicates we should be more tolerant 167 * to calpad busy trimming. 168 */ 169 ret = regmap_read_poll_timeout(rk_phy->reg_base, 170 rk_phy->reg_offset + GRF_EMMCPHY_STATUS, 171 caldone, PHYCTRL_IS_CALDONE(caldone), 172 0, 50); 173 if (ret) { 174 pr_err("%s: caldone failed, ret=%d\n", __func__, ret); 175 return ret; 176 } 177 178 /* Set the frequency of the DLL operation */ 179 regmap_write(rk_phy->reg_base, 180 rk_phy->reg_offset + GRF_EMMCPHY_CON0, 181 HIWORD_UPDATE(freqsel, PHYCTRL_FREQSEL_MASK, 182 PHYCTRL_FREQSEL_SHIFT)); 183 184 /* Turn on the DLL */ 185 regmap_write(rk_phy->reg_base, 186 rk_phy->reg_offset + GRF_EMMCPHY_CON6, 187 HIWORD_UPDATE(PHYCTRL_ENDLL_ENABLE, 188 PHYCTRL_ENDLL_MASK, 189 PHYCTRL_ENDLL_SHIFT)); 190 191 /* 192 * We turned on the DLL even though the rate was 0 because we the 193 * clock might be turned on later. ...but we can't wait for the DLL 194 * to lock when the rate is 0 because it will never lock with no 195 * input clock. 196 * 197 * Technically we should be checking the lock later when the clock 198 * is turned on, but for now we won't. 199 */ 200 if (rate == 0) 201 return 0; 202 203 /* 204 * After enabling analog DLL circuits docs say that we need 10.2 us if 205 * our source clock is at 50 MHz and that lock time scales linearly 206 * with clock speed. If we are powering on the PHY and the card clock 207 * is super slow (like 100 kHZ) this could take as long as 5.1 ms as 208 * per the math: 10.2 us * (50000000 Hz / 100000 Hz) => 5.1 ms 209 * Hopefully we won't be running at 100 kHz, but we should still make 210 * sure we wait long enough. 211 * 212 * NOTE: There appear to be corner cases where the DLL seems to take 213 * extra long to lock for reasons that aren't understood. In some 214 * extreme cases we've seen it take up to over 10ms (!). We'll be 215 * generous and give it 50ms. 216 */ 217 ret = regmap_read_poll_timeout(rk_phy->reg_base, 218 rk_phy->reg_offset + GRF_EMMCPHY_STATUS, 219 dllrdy, PHYCTRL_IS_DLLRDY(dllrdy), 220 0, 50 * USEC_PER_MSEC); 221 if (ret) { 222 pr_err("%s: dllrdy failed. ret=%d\n", __func__, ret); 223 return ret; 224 } 225 226 return 0; 227 } 228 229 static int rockchip_emmc_phy_init(struct phy *phy) 230 { 231 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); 232 int ret = 0; 233 234 /* 235 * We purposely get the clock here and not in probe to avoid the 236 * circular dependency problem. We expect: 237 * - PHY driver to probe 238 * - SDHCI driver to start probe 239 * - SDHCI driver to register it's clock 240 * - SDHCI driver to get the PHY 241 * - SDHCI driver to init the PHY 242 * 243 * The clock is optional, so upon any error we just set to NULL. 244 * 245 * NOTE: we don't do anything special for EPROBE_DEFER here. Given the 246 * above expected use case, EPROBE_DEFER isn't sensible to expect, so 247 * it's just like any other error. 248 */ 249 rk_phy->emmcclk = clk_get(&phy->dev, "emmcclk"); 250 if (IS_ERR(rk_phy->emmcclk)) { 251 dev_dbg(&phy->dev, "Error getting emmcclk: %d\n", ret); 252 rk_phy->emmcclk = NULL; 253 } 254 255 return ret; 256 } 257 258 static int rockchip_emmc_phy_exit(struct phy *phy) 259 { 260 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); 261 262 clk_put(rk_phy->emmcclk); 263 264 return 0; 265 } 266 267 static int rockchip_emmc_phy_power_off(struct phy *phy) 268 { 269 /* Power down emmc phy analog blocks */ 270 return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_OFF); 271 } 272 273 static int rockchip_emmc_phy_power_on(struct phy *phy) 274 { 275 struct rockchip_emmc_phy *rk_phy = phy_get_drvdata(phy); 276 277 /* Drive impedance: from DTS */ 278 regmap_write(rk_phy->reg_base, 279 rk_phy->reg_offset + GRF_EMMCPHY_CON6, 280 HIWORD_UPDATE(rk_phy->drive_impedance, 281 PHYCTRL_DR_MASK, 282 PHYCTRL_DR_SHIFT)); 283 284 /* Output tap delay: enable */ 285 regmap_write(rk_phy->reg_base, 286 rk_phy->reg_offset + GRF_EMMCPHY_CON0, 287 HIWORD_UPDATE(PHYCTRL_OTAPDLYENA, 288 PHYCTRL_OTAPDLYENA_MASK, 289 PHYCTRL_OTAPDLYENA_SHIFT)); 290 291 /* Output tap delay */ 292 regmap_write(rk_phy->reg_base, 293 rk_phy->reg_offset + GRF_EMMCPHY_CON0, 294 HIWORD_UPDATE(4, 295 PHYCTRL_OTAPDLYSEL_MASK, 296 PHYCTRL_OTAPDLYSEL_SHIFT)); 297 298 /* Power up emmc phy analog blocks */ 299 return rockchip_emmc_phy_power(phy, PHYCTRL_PDB_PWR_ON); 300 } 301 302 static const struct phy_ops ops = { 303 .init = rockchip_emmc_phy_init, 304 .exit = rockchip_emmc_phy_exit, 305 .power_on = rockchip_emmc_phy_power_on, 306 .power_off = rockchip_emmc_phy_power_off, 307 .owner = THIS_MODULE, 308 }; 309 310 static u32 convert_drive_impedance_ohm(struct platform_device *pdev, u32 dr_ohm) 311 { 312 switch (dr_ohm) { 313 case 100: 314 return PHYCTRL_DR_100OHM; 315 case 66: 316 return PHYCTRL_DR_66OHM; 317 case 50: 318 return PHYCTRL_DR_50OHM; 319 case 40: 320 return PHYCTRL_DR_40OHM; 321 case 33: 322 return PHYCTRL_DR_33OHM; 323 } 324 325 dev_warn(&pdev->dev, "Invalid value %u for drive-impedance-ohm.\n", 326 dr_ohm); 327 return PHYCTRL_DR_50OHM; 328 } 329 330 static int rockchip_emmc_phy_probe(struct platform_device *pdev) 331 { 332 struct device *dev = &pdev->dev; 333 struct rockchip_emmc_phy *rk_phy; 334 struct phy *generic_phy; 335 struct phy_provider *phy_provider; 336 struct regmap *grf; 337 unsigned int reg_offset; 338 u32 val; 339 340 if (!dev->parent || !dev->parent->of_node) 341 return -ENODEV; 342 343 grf = syscon_node_to_regmap(dev->parent->of_node); 344 if (IS_ERR(grf)) { 345 dev_err(dev, "Missing rockchip,grf property\n"); 346 return PTR_ERR(grf); 347 } 348 349 rk_phy = devm_kzalloc(dev, sizeof(*rk_phy), GFP_KERNEL); 350 if (!rk_phy) 351 return -ENOMEM; 352 353 if (of_property_read_u32(dev->of_node, "reg", ®_offset)) { 354 dev_err(dev, "missing reg property in node %pOFn\n", 355 dev->of_node); 356 return -EINVAL; 357 } 358 359 rk_phy->reg_offset = reg_offset; 360 rk_phy->reg_base = grf; 361 rk_phy->drive_impedance = PHYCTRL_DR_50OHM; 362 363 if (!of_property_read_u32(dev->of_node, "drive-impedance-ohm", &val)) 364 rk_phy->drive_impedance = convert_drive_impedance_ohm(pdev, val); 365 366 generic_phy = devm_phy_create(dev, dev->of_node, &ops); 367 if (IS_ERR(generic_phy)) { 368 dev_err(dev, "failed to create PHY\n"); 369 return PTR_ERR(generic_phy); 370 } 371 372 phy_set_drvdata(generic_phy, rk_phy); 373 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 374 375 return PTR_ERR_OR_ZERO(phy_provider); 376 } 377 378 static const struct of_device_id rockchip_emmc_phy_dt_ids[] = { 379 { .compatible = "rockchip,rk3399-emmc-phy" }, 380 {} 381 }; 382 383 MODULE_DEVICE_TABLE(of, rockchip_emmc_phy_dt_ids); 384 385 static struct platform_driver rockchip_emmc_driver = { 386 .probe = rockchip_emmc_phy_probe, 387 .driver = { 388 .name = "rockchip-emmc-phy", 389 .of_match_table = rockchip_emmc_phy_dt_ids, 390 }, 391 }; 392 393 module_platform_driver(rockchip_emmc_driver); 394 395 MODULE_AUTHOR("Shawn Lin <shawn.lin@rock-chips.com>"); 396 MODULE_DESCRIPTION("Rockchip EMMC PHY driver"); 397 MODULE_LICENSE("GPL v2"); 398