1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Renesas R-Car Gen2 PHY driver
4  *
5  * Copyright (C) 2014 Renesas Solutions Corp.
6  * Copyright (C) 2014 Cogent Embedded, Inc.
7  */
8 
9 #include <linux/clk.h>
10 #include <linux/delay.h>
11 #include <linux/io.h>
12 #include <linux/module.h>
13 #include <linux/of.h>
14 #include <linux/phy/phy.h>
15 #include <linux/platform_device.h>
16 #include <linux/spinlock.h>
17 #include <linux/atomic.h>
18 
19 #define USBHS_LPSTS			0x02
20 #define USBHS_UGCTRL			0x80
21 #define USBHS_UGCTRL2			0x84
22 #define USBHS_UGSTS			0x88	/* From technical update */
23 
24 /* Low Power Status register (LPSTS) */
25 #define USBHS_LPSTS_SUSPM		0x4000
26 
27 /* USB General control register (UGCTRL) */
28 #define USBHS_UGCTRL_CONNECT		0x00000004
29 #define USBHS_UGCTRL_PLLRESET		0x00000001
30 
31 /* USB General control register 2 (UGCTRL2) */
32 #define USBHS_UGCTRL2_USB2SEL		0x80000000
33 #define USBHS_UGCTRL2_USB2SEL_PCI	0x00000000
34 #define USBHS_UGCTRL2_USB2SEL_USB30	0x80000000
35 #define USBHS_UGCTRL2_USB0SEL		0x00000030
36 #define USBHS_UGCTRL2_USB0SEL_PCI	0x00000010
37 #define USBHS_UGCTRL2_USB0SEL_HS_USB	0x00000030
38 
39 /* USB General status register (UGSTS) */
40 #define USBHS_UGSTS_LOCK		0x00000100 /* From technical update */
41 
42 #define PHYS_PER_CHANNEL	2
43 
44 struct rcar_gen2_phy {
45 	struct phy *phy;
46 	struct rcar_gen2_channel *channel;
47 	int number;
48 	u32 select_value;
49 };
50 
51 struct rcar_gen2_channel {
52 	struct device_node *of_node;
53 	struct rcar_gen2_phy_driver *drv;
54 	struct rcar_gen2_phy phys[PHYS_PER_CHANNEL];
55 	int selected_phy;
56 	u32 select_mask;
57 };
58 
59 struct rcar_gen2_phy_driver {
60 	void __iomem *base;
61 	struct clk *clk;
62 	spinlock_t lock;
63 	int num_channels;
64 	struct rcar_gen2_channel *channels;
65 };
66 
67 static int rcar_gen2_phy_init(struct phy *p)
68 {
69 	struct rcar_gen2_phy *phy = phy_get_drvdata(p);
70 	struct rcar_gen2_channel *channel = phy->channel;
71 	struct rcar_gen2_phy_driver *drv = channel->drv;
72 	unsigned long flags;
73 	u32 ugctrl2;
74 
75 	/*
76 	 * Try to acquire exclusive access to PHY.  The first driver calling
77 	 * phy_init()  on a given channel wins, and all attempts  to use another
78 	 * PHY on this channel will fail until phy_exit() is called by the first
79 	 * driver.   Achieving this with cmpxcgh() should be SMP-safe.
80 	 */
81 	if (cmpxchg(&channel->selected_phy, -1, phy->number) != -1)
82 		return -EBUSY;
83 
84 	clk_prepare_enable(drv->clk);
85 
86 	spin_lock_irqsave(&drv->lock, flags);
87 	ugctrl2 = readl(drv->base + USBHS_UGCTRL2);
88 	ugctrl2 &= ~channel->select_mask;
89 	ugctrl2 |= phy->select_value;
90 	writel(ugctrl2, drv->base + USBHS_UGCTRL2);
91 	spin_unlock_irqrestore(&drv->lock, flags);
92 	return 0;
93 }
94 
95 static int rcar_gen2_phy_exit(struct phy *p)
96 {
97 	struct rcar_gen2_phy *phy = phy_get_drvdata(p);
98 	struct rcar_gen2_channel *channel = phy->channel;
99 
100 	clk_disable_unprepare(channel->drv->clk);
101 
102 	channel->selected_phy = -1;
103 
104 	return 0;
105 }
106 
107 static int rcar_gen2_phy_power_on(struct phy *p)
108 {
109 	struct rcar_gen2_phy *phy = phy_get_drvdata(p);
110 	struct rcar_gen2_phy_driver *drv = phy->channel->drv;
111 	void __iomem *base = drv->base;
112 	unsigned long flags;
113 	u32 value;
114 	int err = 0, i;
115 
116 	/* Skip if it's not USBHS */
117 	if (phy->select_value != USBHS_UGCTRL2_USB0SEL_HS_USB)
118 		return 0;
119 
120 	spin_lock_irqsave(&drv->lock, flags);
121 
122 	/* Power on USBHS PHY */
123 	value = readl(base + USBHS_UGCTRL);
124 	value &= ~USBHS_UGCTRL_PLLRESET;
125 	writel(value, base + USBHS_UGCTRL);
126 
127 	value = readw(base + USBHS_LPSTS);
128 	value |= USBHS_LPSTS_SUSPM;
129 	writew(value, base + USBHS_LPSTS);
130 
131 	for (i = 0; i < 20; i++) {
132 		value = readl(base + USBHS_UGSTS);
133 		if ((value & USBHS_UGSTS_LOCK) == USBHS_UGSTS_LOCK) {
134 			value = readl(base + USBHS_UGCTRL);
135 			value |= USBHS_UGCTRL_CONNECT;
136 			writel(value, base + USBHS_UGCTRL);
137 			goto out;
138 		}
139 		udelay(1);
140 	}
141 
142 	/* Timed out waiting for the PLL lock */
143 	err = -ETIMEDOUT;
144 
145 out:
146 	spin_unlock_irqrestore(&drv->lock, flags);
147 
148 	return err;
149 }
150 
151 static int rcar_gen2_phy_power_off(struct phy *p)
152 {
153 	struct rcar_gen2_phy *phy = phy_get_drvdata(p);
154 	struct rcar_gen2_phy_driver *drv = phy->channel->drv;
155 	void __iomem *base = drv->base;
156 	unsigned long flags;
157 	u32 value;
158 
159 	/* Skip if it's not USBHS */
160 	if (phy->select_value != USBHS_UGCTRL2_USB0SEL_HS_USB)
161 		return 0;
162 
163 	spin_lock_irqsave(&drv->lock, flags);
164 
165 	/* Power off USBHS PHY */
166 	value = readl(base + USBHS_UGCTRL);
167 	value &= ~USBHS_UGCTRL_CONNECT;
168 	writel(value, base + USBHS_UGCTRL);
169 
170 	value = readw(base + USBHS_LPSTS);
171 	value &= ~USBHS_LPSTS_SUSPM;
172 	writew(value, base + USBHS_LPSTS);
173 
174 	value = readl(base + USBHS_UGCTRL);
175 	value |= USBHS_UGCTRL_PLLRESET;
176 	writel(value, base + USBHS_UGCTRL);
177 
178 	spin_unlock_irqrestore(&drv->lock, flags);
179 
180 	return 0;
181 }
182 
183 static const struct phy_ops rcar_gen2_phy_ops = {
184 	.init		= rcar_gen2_phy_init,
185 	.exit		= rcar_gen2_phy_exit,
186 	.power_on	= rcar_gen2_phy_power_on,
187 	.power_off	= rcar_gen2_phy_power_off,
188 	.owner		= THIS_MODULE,
189 };
190 
191 static const struct of_device_id rcar_gen2_phy_match_table[] = {
192 	{ .compatible = "renesas,usb-phy-r8a7790" },
193 	{ .compatible = "renesas,usb-phy-r8a7791" },
194 	{ .compatible = "renesas,usb-phy-r8a7794" },
195 	{ .compatible = "renesas,rcar-gen2-usb-phy" },
196 	{ }
197 };
198 MODULE_DEVICE_TABLE(of, rcar_gen2_phy_match_table);
199 
200 static struct phy *rcar_gen2_phy_xlate(struct device *dev,
201 				       struct of_phandle_args *args)
202 {
203 	struct rcar_gen2_phy_driver *drv;
204 	struct device_node *np = args->np;
205 	int i;
206 
207 	drv = dev_get_drvdata(dev);
208 	if (!drv)
209 		return ERR_PTR(-EINVAL);
210 
211 	for (i = 0; i < drv->num_channels; i++) {
212 		if (np == drv->channels[i].of_node)
213 			break;
214 	}
215 
216 	if (i >= drv->num_channels || args->args[0] >= 2)
217 		return ERR_PTR(-ENODEV);
218 
219 	return drv->channels[i].phys[args->args[0]].phy;
220 }
221 
222 static const u32 select_mask[] = {
223 	[0]	= USBHS_UGCTRL2_USB0SEL,
224 	[2]	= USBHS_UGCTRL2_USB2SEL,
225 };
226 
227 static const u32 select_value[][PHYS_PER_CHANNEL] = {
228 	[0]	= { USBHS_UGCTRL2_USB0SEL_PCI, USBHS_UGCTRL2_USB0SEL_HS_USB },
229 	[2]	= { USBHS_UGCTRL2_USB2SEL_PCI, USBHS_UGCTRL2_USB2SEL_USB30 },
230 };
231 
232 static int rcar_gen2_phy_probe(struct platform_device *pdev)
233 {
234 	struct device *dev = &pdev->dev;
235 	struct rcar_gen2_phy_driver *drv;
236 	struct phy_provider *provider;
237 	struct device_node *np;
238 	struct resource *res;
239 	void __iomem *base;
240 	struct clk *clk;
241 	int i = 0;
242 
243 	if (!dev->of_node) {
244 		dev_err(dev,
245 			"This driver is required to be instantiated from device tree\n");
246 		return -EINVAL;
247 	}
248 
249 	clk = devm_clk_get(dev, "usbhs");
250 	if (IS_ERR(clk)) {
251 		dev_err(dev, "Can't get USBHS clock\n");
252 		return PTR_ERR(clk);
253 	}
254 
255 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
256 	base = devm_ioremap_resource(dev, res);
257 	if (IS_ERR(base))
258 		return PTR_ERR(base);
259 
260 	drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
261 	if (!drv)
262 		return -ENOMEM;
263 
264 	spin_lock_init(&drv->lock);
265 
266 	drv->clk = clk;
267 	drv->base = base;
268 
269 	drv->num_channels = of_get_child_count(dev->of_node);
270 	drv->channels = devm_kcalloc(dev, drv->num_channels,
271 				     sizeof(struct rcar_gen2_channel),
272 				     GFP_KERNEL);
273 	if (!drv->channels)
274 		return -ENOMEM;
275 
276 	for_each_child_of_node(dev->of_node, np) {
277 		struct rcar_gen2_channel *channel = drv->channels + i;
278 		u32 channel_num;
279 		int error, n;
280 
281 		channel->of_node = np;
282 		channel->drv = drv;
283 		channel->selected_phy = -1;
284 
285 		error = of_property_read_u32(np, "reg", &channel_num);
286 		if (error || channel_num > 2) {
287 			dev_err(dev, "Invalid \"reg\" property\n");
288 			return error;
289 		}
290 		channel->select_mask = select_mask[channel_num];
291 
292 		for (n = 0; n < PHYS_PER_CHANNEL; n++) {
293 			struct rcar_gen2_phy *phy = &channel->phys[n];
294 
295 			phy->channel = channel;
296 			phy->number = n;
297 			phy->select_value = select_value[channel_num][n];
298 
299 			phy->phy = devm_phy_create(dev, NULL,
300 						   &rcar_gen2_phy_ops);
301 			if (IS_ERR(phy->phy)) {
302 				dev_err(dev, "Failed to create PHY\n");
303 				return PTR_ERR(phy->phy);
304 			}
305 			phy_set_drvdata(phy->phy, phy);
306 		}
307 
308 		i++;
309 	}
310 
311 	provider = devm_of_phy_provider_register(dev, rcar_gen2_phy_xlate);
312 	if (IS_ERR(provider)) {
313 		dev_err(dev, "Failed to register PHY provider\n");
314 		return PTR_ERR(provider);
315 	}
316 
317 	dev_set_drvdata(dev, drv);
318 
319 	return 0;
320 }
321 
322 static struct platform_driver rcar_gen2_phy_driver = {
323 	.driver = {
324 		.name		= "phy_rcar_gen2",
325 		.of_match_table	= rcar_gen2_phy_match_table,
326 	},
327 	.probe	= rcar_gen2_phy_probe,
328 };
329 
330 module_platform_driver(rcar_gen2_phy_driver);
331 
332 MODULE_LICENSE("GPL v2");
333 MODULE_DESCRIPTION("Renesas R-Car Gen2 PHY");
334 MODULE_AUTHOR("Sergei Shtylyov <sergei.shtylyov@cogentembedded.com>");
335