1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2020, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/kernel.h> 11 #include <linux/module.h> 12 #include <linux/of.h> 13 #include <linux/of_device.h> 14 #include <linux/phy/phy.h> 15 #include <linux/platform_device.h> 16 #include <linux/regmap.h> 17 #include <linux/regulator/consumer.h> 18 #include <linux/reset.h> 19 #include <linux/slab.h> 20 21 #define USB2_PHY_USB_PHY_UTMI_CTRL0 (0x3c) 22 #define SLEEPM BIT(0) 23 #define OPMODE_MASK GENMASK(4, 3) 24 #define OPMODE_NORMAL (0x00) 25 #define OPMODE_NONDRIVING BIT(3) 26 #define TERMSEL BIT(5) 27 28 #define USB2_PHY_USB_PHY_UTMI_CTRL1 (0x40) 29 #define XCVRSEL BIT(0) 30 31 #define USB2_PHY_USB_PHY_UTMI_CTRL5 (0x50) 32 #define POR BIT(1) 33 34 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0 (0x54) 35 #define SIDDQ BIT(2) 36 #define RETENABLEN BIT(3) 37 #define FSEL_MASK GENMASK(6, 4) 38 #define FSEL_DEFAULT (0x3 << 4) 39 40 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1 (0x58) 41 #define VBUSVLDEXTSEL0 BIT(4) 42 #define PLLBTUNE BIT(5) 43 44 #define USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2 (0x5c) 45 #define VREGBYPASS BIT(0) 46 47 #define USB2_PHY_USB_PHY_HS_PHY_CTRL1 (0x60) 48 #define VBUSVLDEXT0 BIT(0) 49 50 #define USB2_PHY_USB_PHY_HS_PHY_CTRL2 (0x64) 51 #define USB2_AUTO_RESUME BIT(0) 52 #define USB2_SUSPEND_N BIT(2) 53 #define USB2_SUSPEND_N_SEL BIT(3) 54 55 #define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0 (0x6c) 56 #define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1 (0x70) 57 #define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2 (0x74) 58 #define USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3 (0x78) 59 #define PARAM_OVRD_MASK 0xFF 60 61 #define USB2_PHY_USB_PHY_CFG0 (0x94) 62 #define UTMI_PHY_DATAPATH_CTRL_OVERRIDE_EN BIT(0) 63 #define UTMI_PHY_CMN_CTRL_OVERRIDE_EN BIT(1) 64 65 #define USB2_PHY_USB_PHY_REFCLK_CTRL (0xa0) 66 #define REFCLK_SEL_MASK GENMASK(1, 0) 67 #define REFCLK_SEL_DEFAULT (0x2 << 0) 68 69 #define HS_DISCONNECT_MASK GENMASK(2, 0) 70 #define SQUELCH_DETECTOR_MASK GENMASK(7, 5) 71 72 #define HS_AMPLITUDE_MASK GENMASK(3, 0) 73 #define PREEMPHASIS_DURATION_MASK BIT(5) 74 #define PREEMPHASIS_AMPLITUDE_MASK GENMASK(7, 6) 75 76 #define HS_RISE_FALL_MASK GENMASK(1, 0) 77 #define HS_CROSSOVER_VOLTAGE_MASK GENMASK(3, 2) 78 #define HS_OUTPUT_IMPEDANCE_MASK GENMASK(5, 4) 79 80 #define LS_FS_OUTPUT_IMPEDANCE_MASK GENMASK(3, 0) 81 82 static const char * const qcom_snps_hsphy_vreg_names[] = { 83 "vdda-pll", "vdda33", "vdda18", 84 }; 85 86 #define SNPS_HS_NUM_VREGS ARRAY_SIZE(qcom_snps_hsphy_vreg_names) 87 88 struct override_param { 89 s32 value; 90 u8 reg_val; 91 }; 92 93 struct override_param_map { 94 const char *prop_name; 95 const struct override_param *param_table; 96 u8 table_size; 97 u8 reg_offset; 98 u8 param_mask; 99 }; 100 101 struct phy_override_seq { 102 bool need_update; 103 u8 offset; 104 u8 value; 105 u8 mask; 106 }; 107 108 #define NUM_HSPHY_TUNING_PARAMS (9) 109 110 /** 111 * struct qcom_snps_hsphy - snps hs phy attributes 112 * 113 * @dev: device structure 114 * 115 * @phy: generic phy 116 * @base: iomapped memory space for snps hs phy 117 * 118 * @num_clks: number of clocks 119 * @clks: array of clocks 120 * @phy_reset: phy reset control 121 * @vregs: regulator supplies bulk data 122 * @phy_initialized: if PHY has been initialized correctly 123 * @mode: contains the current mode the PHY is in 124 * @update_seq_cfg: tuning parameters for phy init 125 */ 126 struct qcom_snps_hsphy { 127 struct device *dev; 128 129 struct phy *phy; 130 void __iomem *base; 131 132 int num_clks; 133 struct clk_bulk_data *clks; 134 struct reset_control *phy_reset; 135 struct regulator_bulk_data vregs[SNPS_HS_NUM_VREGS]; 136 137 bool phy_initialized; 138 enum phy_mode mode; 139 struct phy_override_seq update_seq_cfg[NUM_HSPHY_TUNING_PARAMS]; 140 }; 141 142 static int qcom_snps_hsphy_clk_init(struct qcom_snps_hsphy *hsphy) 143 { 144 struct device *dev = hsphy->dev; 145 146 hsphy->num_clks = 2; 147 hsphy->clks = devm_kcalloc(dev, hsphy->num_clks, sizeof(*hsphy->clks), GFP_KERNEL); 148 if (!hsphy->clks) 149 return -ENOMEM; 150 151 /* 152 * TODO: Currently no device tree instantiation of the PHY is using the clock. 153 * This needs to be fixed in order for this code to be able to use devm_clk_bulk_get(). 154 */ 155 hsphy->clks[0].id = "cfg_ahb"; 156 hsphy->clks[0].clk = devm_clk_get_optional(dev, "cfg_ahb"); 157 if (IS_ERR(hsphy->clks[0].clk)) 158 return dev_err_probe(dev, PTR_ERR(hsphy->clks[0].clk), 159 "failed to get cfg_ahb clk\n"); 160 161 hsphy->clks[1].id = "ref"; 162 hsphy->clks[1].clk = devm_clk_get(dev, "ref"); 163 if (IS_ERR(hsphy->clks[1].clk)) 164 return dev_err_probe(dev, PTR_ERR(hsphy->clks[1].clk), 165 "failed to get ref clk\n"); 166 167 return 0; 168 } 169 170 static inline void qcom_snps_hsphy_write_mask(void __iomem *base, u32 offset, 171 u32 mask, u32 val) 172 { 173 u32 reg; 174 175 reg = readl_relaxed(base + offset); 176 reg &= ~mask; 177 reg |= val & mask; 178 writel_relaxed(reg, base + offset); 179 180 /* Ensure above write is completed */ 181 readl_relaxed(base + offset); 182 } 183 184 static int qcom_snps_hsphy_suspend(struct qcom_snps_hsphy *hsphy) 185 { 186 dev_dbg(&hsphy->phy->dev, "Suspend QCOM SNPS PHY\n"); 187 188 if (hsphy->mode == PHY_MODE_USB_HOST) { 189 /* Enable auto-resume to meet remote wakeup timing */ 190 qcom_snps_hsphy_write_mask(hsphy->base, 191 USB2_PHY_USB_PHY_HS_PHY_CTRL2, 192 USB2_AUTO_RESUME, 193 USB2_AUTO_RESUME); 194 usleep_range(500, 1000); 195 qcom_snps_hsphy_write_mask(hsphy->base, 196 USB2_PHY_USB_PHY_HS_PHY_CTRL2, 197 0, USB2_AUTO_RESUME); 198 } 199 200 return 0; 201 } 202 203 static int qcom_snps_hsphy_resume(struct qcom_snps_hsphy *hsphy) 204 { 205 dev_dbg(&hsphy->phy->dev, "Resume QCOM SNPS PHY, mode\n"); 206 207 return 0; 208 } 209 210 static int __maybe_unused qcom_snps_hsphy_runtime_suspend(struct device *dev) 211 { 212 struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev); 213 214 if (!hsphy->phy_initialized) 215 return 0; 216 217 return qcom_snps_hsphy_suspend(hsphy); 218 } 219 220 static int __maybe_unused qcom_snps_hsphy_runtime_resume(struct device *dev) 221 { 222 struct qcom_snps_hsphy *hsphy = dev_get_drvdata(dev); 223 224 if (!hsphy->phy_initialized) 225 return 0; 226 227 return qcom_snps_hsphy_resume(hsphy); 228 } 229 230 static int qcom_snps_hsphy_set_mode(struct phy *phy, enum phy_mode mode, 231 int submode) 232 { 233 struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); 234 235 hsphy->mode = mode; 236 return 0; 237 } 238 239 static const struct override_param hs_disconnect_sc7280[] = { 240 { -272, 0 }, 241 { 0, 1 }, 242 { 317, 2 }, 243 { 630, 3 }, 244 { 973, 4 }, 245 { 1332, 5 }, 246 { 1743, 6 }, 247 { 2156, 7 }, 248 }; 249 250 static const struct override_param squelch_det_threshold_sc7280[] = { 251 { -2090, 7 }, 252 { -1560, 6 }, 253 { -1030, 5 }, 254 { -530, 4 }, 255 { 0, 3 }, 256 { 530, 2 }, 257 { 1060, 1 }, 258 { 1590, 0 }, 259 }; 260 261 static const struct override_param hs_amplitude_sc7280[] = { 262 { -660, 0 }, 263 { -440, 1 }, 264 { -220, 2 }, 265 { 0, 3 }, 266 { 230, 4 }, 267 { 440, 5 }, 268 { 650, 6 }, 269 { 890, 7 }, 270 { 1110, 8 }, 271 { 1330, 9 }, 272 { 1560, 10 }, 273 { 1780, 11 }, 274 { 2000, 12 }, 275 { 2220, 13 }, 276 { 2430, 14 }, 277 { 2670, 15 }, 278 }; 279 280 static const struct override_param preemphasis_duration_sc7280[] = { 281 { 10000, 1 }, 282 { 20000, 0 }, 283 }; 284 285 static const struct override_param preemphasis_amplitude_sc7280[] = { 286 { 10000, 1 }, 287 { 20000, 2 }, 288 { 30000, 3 }, 289 { 40000, 0 }, 290 }; 291 292 static const struct override_param hs_rise_fall_time_sc7280[] = { 293 { -4100, 3 }, 294 { 0, 2 }, 295 { 2810, 1 }, 296 { 5430, 0 }, 297 }; 298 299 static const struct override_param hs_crossover_voltage_sc7280[] = { 300 { -31000, 1 }, 301 { 0, 3 }, 302 { 28000, 2 }, 303 }; 304 305 static const struct override_param hs_output_impedance_sc7280[] = { 306 { -2300000, 3 }, 307 { 0, 2 }, 308 { 2600000, 1 }, 309 { 6100000, 0 }, 310 }; 311 312 static const struct override_param ls_fs_output_impedance_sc7280[] = { 313 { -1053, 15 }, 314 { -557, 7 }, 315 { 0, 3 }, 316 { 612, 1 }, 317 { 1310, 0 }, 318 }; 319 320 static const struct override_param_map sc7280_snps_7nm_phy[] = { 321 { 322 "qcom,hs-disconnect-bp", 323 hs_disconnect_sc7280, 324 ARRAY_SIZE(hs_disconnect_sc7280), 325 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0, 326 HS_DISCONNECT_MASK 327 }, 328 { 329 "qcom,squelch-detector-bp", 330 squelch_det_threshold_sc7280, 331 ARRAY_SIZE(squelch_det_threshold_sc7280), 332 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X0, 333 SQUELCH_DETECTOR_MASK 334 }, 335 { 336 "qcom,hs-amplitude-bp", 337 hs_amplitude_sc7280, 338 ARRAY_SIZE(hs_amplitude_sc7280), 339 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1, 340 HS_AMPLITUDE_MASK 341 }, 342 { 343 "qcom,pre-emphasis-duration-bp", 344 preemphasis_duration_sc7280, 345 ARRAY_SIZE(preemphasis_duration_sc7280), 346 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1, 347 PREEMPHASIS_DURATION_MASK, 348 }, 349 { 350 "qcom,pre-emphasis-amplitude-bp", 351 preemphasis_amplitude_sc7280, 352 ARRAY_SIZE(preemphasis_amplitude_sc7280), 353 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X1, 354 PREEMPHASIS_AMPLITUDE_MASK, 355 }, 356 { 357 "qcom,hs-rise-fall-time-bp", 358 hs_rise_fall_time_sc7280, 359 ARRAY_SIZE(hs_rise_fall_time_sc7280), 360 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2, 361 HS_RISE_FALL_MASK 362 }, 363 { 364 "qcom,hs-crossover-voltage-microvolt", 365 hs_crossover_voltage_sc7280, 366 ARRAY_SIZE(hs_crossover_voltage_sc7280), 367 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2, 368 HS_CROSSOVER_VOLTAGE_MASK 369 }, 370 { 371 "qcom,hs-output-impedance-micro-ohms", 372 hs_output_impedance_sc7280, 373 ARRAY_SIZE(hs_output_impedance_sc7280), 374 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X2, 375 HS_OUTPUT_IMPEDANCE_MASK, 376 }, 377 { 378 "qcom,ls-fs-output-impedance-bp", 379 ls_fs_output_impedance_sc7280, 380 ARRAY_SIZE(ls_fs_output_impedance_sc7280), 381 USB2_PHY_USB_PHY_HS_PHY_OVERRIDE_X3, 382 LS_FS_OUTPUT_IMPEDANCE_MASK, 383 }, 384 {}, 385 }; 386 387 static int qcom_snps_hsphy_init(struct phy *phy) 388 { 389 struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); 390 int ret, i; 391 392 dev_vdbg(&phy->dev, "%s(): Initializing SNPS HS phy\n", __func__); 393 394 ret = regulator_bulk_enable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); 395 if (ret) 396 return ret; 397 398 ret = clk_bulk_prepare_enable(hsphy->num_clks, hsphy->clks); 399 if (ret) { 400 dev_err(&phy->dev, "failed to enable clocks, %d\n", ret); 401 goto poweroff_phy; 402 } 403 404 ret = reset_control_assert(hsphy->phy_reset); 405 if (ret) { 406 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); 407 goto disable_clks; 408 } 409 410 usleep_range(100, 150); 411 412 ret = reset_control_deassert(hsphy->phy_reset); 413 if (ret) { 414 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); 415 goto disable_clks; 416 } 417 418 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, 419 UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 420 UTMI_PHY_CMN_CTRL_OVERRIDE_EN); 421 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, 422 POR, POR); 423 qcom_snps_hsphy_write_mask(hsphy->base, 424 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, 425 FSEL_MASK, 0); 426 qcom_snps_hsphy_write_mask(hsphy->base, 427 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, 428 PLLBTUNE, PLLBTUNE); 429 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_REFCLK_CTRL, 430 REFCLK_SEL_DEFAULT, REFCLK_SEL_MASK); 431 qcom_snps_hsphy_write_mask(hsphy->base, 432 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON1, 433 VBUSVLDEXTSEL0, VBUSVLDEXTSEL0); 434 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL1, 435 VBUSVLDEXT0, VBUSVLDEXT0); 436 437 for (i = 0; i < ARRAY_SIZE(hsphy->update_seq_cfg); i++) { 438 if (hsphy->update_seq_cfg[i].need_update) 439 qcom_snps_hsphy_write_mask(hsphy->base, 440 hsphy->update_seq_cfg[i].offset, 441 hsphy->update_seq_cfg[i].mask, 442 hsphy->update_seq_cfg[i].value); 443 } 444 445 qcom_snps_hsphy_write_mask(hsphy->base, 446 USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON2, 447 VREGBYPASS, VREGBYPASS); 448 449 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, 450 USB2_SUSPEND_N_SEL | USB2_SUSPEND_N, 451 USB2_SUSPEND_N_SEL | USB2_SUSPEND_N); 452 453 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL0, 454 SLEEPM, SLEEPM); 455 456 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL_COMMON0, 457 SIDDQ, 0); 458 459 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_UTMI_CTRL5, 460 POR, 0); 461 462 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_HS_PHY_CTRL2, 463 USB2_SUSPEND_N_SEL, 0); 464 465 qcom_snps_hsphy_write_mask(hsphy->base, USB2_PHY_USB_PHY_CFG0, 466 UTMI_PHY_CMN_CTRL_OVERRIDE_EN, 0); 467 468 hsphy->phy_initialized = true; 469 470 return 0; 471 472 disable_clks: 473 clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks); 474 poweroff_phy: 475 regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); 476 477 return ret; 478 } 479 480 static int qcom_snps_hsphy_exit(struct phy *phy) 481 { 482 struct qcom_snps_hsphy *hsphy = phy_get_drvdata(phy); 483 484 reset_control_assert(hsphy->phy_reset); 485 clk_bulk_disable_unprepare(hsphy->num_clks, hsphy->clks); 486 regulator_bulk_disable(ARRAY_SIZE(hsphy->vregs), hsphy->vregs); 487 hsphy->phy_initialized = false; 488 489 return 0; 490 } 491 492 static const struct phy_ops qcom_snps_hsphy_gen_ops = { 493 .init = qcom_snps_hsphy_init, 494 .exit = qcom_snps_hsphy_exit, 495 .set_mode = qcom_snps_hsphy_set_mode, 496 .owner = THIS_MODULE, 497 }; 498 499 static const struct of_device_id qcom_snps_hsphy_of_match_table[] = { 500 { .compatible = "qcom,sm8150-usb-hs-phy", }, 501 { .compatible = "qcom,usb-snps-hs-5nm-phy", }, 502 { 503 .compatible = "qcom,usb-snps-hs-7nm-phy", 504 .data = &sc7280_snps_7nm_phy, 505 }, 506 { .compatible = "qcom,usb-snps-femto-v2-phy", }, 507 { } 508 }; 509 MODULE_DEVICE_TABLE(of, qcom_snps_hsphy_of_match_table); 510 511 static const struct dev_pm_ops qcom_snps_hsphy_pm_ops = { 512 SET_RUNTIME_PM_OPS(qcom_snps_hsphy_runtime_suspend, 513 qcom_snps_hsphy_runtime_resume, NULL) 514 }; 515 516 static void qcom_snps_hsphy_override_param_update_val( 517 const struct override_param_map map, 518 s32 dt_val, struct phy_override_seq *seq_entry) 519 { 520 int i; 521 522 /* 523 * Param table for each param is in increasing order 524 * of dt values. We need to iterate over the list to 525 * select the entry that matches the dt value and pick 526 * up the corresponding register value. 527 */ 528 for (i = 0; i < map.table_size - 1; i++) { 529 if (map.param_table[i].value == dt_val) 530 break; 531 } 532 533 seq_entry->need_update = true; 534 seq_entry->offset = map.reg_offset; 535 seq_entry->mask = map.param_mask; 536 seq_entry->value = map.param_table[i].reg_val << __ffs(map.param_mask); 537 } 538 539 static void qcom_snps_hsphy_read_override_param_seq(struct device *dev) 540 { 541 struct device_node *node = dev->of_node; 542 s32 val; 543 int ret, i; 544 struct qcom_snps_hsphy *hsphy; 545 const struct override_param_map *cfg = of_device_get_match_data(dev); 546 547 if (!cfg) 548 return; 549 550 hsphy = dev_get_drvdata(dev); 551 552 for (i = 0; cfg[i].prop_name != NULL; i++) { 553 ret = of_property_read_s32(node, cfg[i].prop_name, &val); 554 if (ret) 555 continue; 556 557 qcom_snps_hsphy_override_param_update_val(cfg[i], val, 558 &hsphy->update_seq_cfg[i]); 559 dev_dbg(&hsphy->phy->dev, "Read param: %s dt_val: %d reg_val: 0x%x\n", 560 cfg[i].prop_name, val, hsphy->update_seq_cfg[i].value); 561 562 } 563 } 564 565 static int qcom_snps_hsphy_probe(struct platform_device *pdev) 566 { 567 struct device *dev = &pdev->dev; 568 struct qcom_snps_hsphy *hsphy; 569 struct phy_provider *phy_provider; 570 struct phy *generic_phy; 571 int ret, i; 572 int num; 573 574 hsphy = devm_kzalloc(dev, sizeof(*hsphy), GFP_KERNEL); 575 if (!hsphy) 576 return -ENOMEM; 577 578 hsphy->dev = dev; 579 580 hsphy->base = devm_platform_ioremap_resource(pdev, 0); 581 if (IS_ERR(hsphy->base)) 582 return PTR_ERR(hsphy->base); 583 584 ret = qcom_snps_hsphy_clk_init(hsphy); 585 if (ret) 586 return dev_err_probe(dev, ret, "failed to initialize clocks\n"); 587 588 hsphy->phy_reset = devm_reset_control_get_exclusive(&pdev->dev, NULL); 589 if (IS_ERR(hsphy->phy_reset)) { 590 dev_err(dev, "failed to get phy core reset\n"); 591 return PTR_ERR(hsphy->phy_reset); 592 } 593 594 num = ARRAY_SIZE(hsphy->vregs); 595 for (i = 0; i < num; i++) 596 hsphy->vregs[i].supply = qcom_snps_hsphy_vreg_names[i]; 597 598 ret = devm_regulator_bulk_get(dev, num, hsphy->vregs); 599 if (ret) 600 return dev_err_probe(dev, ret, 601 "failed to get regulator supplies\n"); 602 603 pm_runtime_set_active(dev); 604 pm_runtime_enable(dev); 605 /* 606 * Prevent runtime pm from being ON by default. Users can enable 607 * it using power/control in sysfs. 608 */ 609 pm_runtime_forbid(dev); 610 611 generic_phy = devm_phy_create(dev, NULL, &qcom_snps_hsphy_gen_ops); 612 if (IS_ERR(generic_phy)) { 613 ret = PTR_ERR(generic_phy); 614 dev_err(dev, "failed to create phy, %d\n", ret); 615 return ret; 616 } 617 hsphy->phy = generic_phy; 618 619 dev_set_drvdata(dev, hsphy); 620 phy_set_drvdata(generic_phy, hsphy); 621 qcom_snps_hsphy_read_override_param_seq(dev); 622 623 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 624 if (!IS_ERR(phy_provider)) 625 dev_dbg(dev, "Registered Qcom-SNPS HS phy\n"); 626 else 627 pm_runtime_disable(dev); 628 629 return PTR_ERR_OR_ZERO(phy_provider); 630 } 631 632 static struct platform_driver qcom_snps_hsphy_driver = { 633 .probe = qcom_snps_hsphy_probe, 634 .driver = { 635 .name = "qcom-snps-hs-femto-v2-phy", 636 .pm = &qcom_snps_hsphy_pm_ops, 637 .of_match_table = qcom_snps_hsphy_of_match_table, 638 }, 639 }; 640 641 module_platform_driver(qcom_snps_hsphy_driver); 642 643 MODULE_DESCRIPTION("Qualcomm SNPS FEMTO USB HS PHY V2 driver"); 644 MODULE_LICENSE("GPL v2"); 645