1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/kernel.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/nvmem-consumer.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 24 25 #define QUSB2PHY_PLL_TEST 0x04 26 #define CLK_REF_SEL BIT(7) 27 28 #define QUSB2PHY_PLL_TUNE 0x08 29 #define QUSB2PHY_PLL_USER_CTL1 0x0c 30 #define QUSB2PHY_PLL_USER_CTL2 0x10 31 #define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c 32 #define QUSB2PHY_PLL_PWR_CTRL 0x18 33 34 /* QUSB2PHY_PLL_STATUS register bits */ 35 #define PLL_LOCKED BIT(5) 36 37 /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ 38 #define CORE_READY_STATUS BIT(0) 39 40 /* QUSB2PHY_PORT_POWERDOWN register bits */ 41 #define CLAMP_N_EN BIT(5) 42 #define FREEZIO_N BIT(1) 43 #define POWER_DOWN BIT(0) 44 45 /* QUSB2PHY_PWR_CTRL1 register bits */ 46 #define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) 47 #define PWR_CTRL1_CLAMP_N_EN BIT(1) 48 49 #define QUSB2PHY_REFCLK_ENABLE BIT(0) 50 51 #define PHY_CLK_SCHEME_SEL BIT(0) 52 53 /* QUSB2PHY_INTR_CTRL register bits */ 54 #define DMSE_INTR_HIGH_SEL BIT(4) 55 #define DPSE_INTR_HIGH_SEL BIT(3) 56 #define CHG_DET_INTR_EN BIT(2) 57 #define DMSE_INTR_EN BIT(1) 58 #define DPSE_INTR_EN BIT(0) 59 60 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ 61 #define CORE_PLL_EN_FROM_RESET BIT(4) 62 #define CORE_RESET BIT(5) 63 #define CORE_RESET_MUX BIT(6) 64 65 /* QUSB2PHY_IMP_CTRL1 register bits */ 66 #define IMP_RES_OFFSET_MASK GENMASK(5, 0) 67 #define IMP_RES_OFFSET_SHIFT 0x0 68 69 /* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ 70 #define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0) 71 #define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0 72 73 /* QUSB2PHY_CHG_CONTROL_2 register bits */ 74 #define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4) 75 #define CHG_CTRL2_OFFSET_SHIFT 0x4 76 77 /* QUSB2PHY_PORT_TUNE1 register bits */ 78 #define HSTX_TRIM_MASK GENMASK(7, 4) 79 #define HSTX_TRIM_SHIFT 0x4 80 #define PREEMPH_WIDTH_HALF_BIT BIT(2) 81 #define PREEMPHASIS_EN_MASK GENMASK(1, 0) 82 #define PREEMPHASIS_EN_SHIFT 0x0 83 84 /* QUSB2PHY_PORT_TUNE2 register bits */ 85 #define HSDISC_TRIM_MASK GENMASK(1, 0) 86 #define HSDISC_TRIM_SHIFT 0x0 87 88 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 89 #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c 90 #define QUSB2PHY_PLL_CMODE 0x2c 91 #define QUSB2PHY_PLL_LOCK_DELAY 0x184 92 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4 93 #define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194 94 #define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198 95 #define QUSB2PHY_PWR_CTRL2 0x214 96 #define QUSB2PHY_IMP_CTRL1 0x220 97 #define QUSB2PHY_IMP_CTRL2 0x224 98 #define QUSB2PHY_CHG_CTRL2 0x23c 99 100 struct qusb2_phy_init_tbl { 101 unsigned int offset; 102 unsigned int val; 103 /* 104 * register part of layout ? 105 * if yes, then offset gives index in the reg-layout 106 */ 107 int in_layout; 108 }; 109 110 #define QUSB2_PHY_INIT_CFG(o, v) \ 111 { \ 112 .offset = o, \ 113 .val = v, \ 114 } 115 116 #define QUSB2_PHY_INIT_CFG_L(o, v) \ 117 { \ 118 .offset = o, \ 119 .val = v, \ 120 .in_layout = 1, \ 121 } 122 123 /* set of registers with offsets different per-PHY */ 124 enum qusb2phy_reg_layout { 125 QUSB2PHY_PLL_CORE_INPUT_OVERRIDE, 126 QUSB2PHY_PLL_STATUS, 127 QUSB2PHY_PORT_TUNE1, 128 QUSB2PHY_PORT_TUNE2, 129 QUSB2PHY_PORT_TUNE3, 130 QUSB2PHY_PORT_TUNE4, 131 QUSB2PHY_PORT_TUNE5, 132 QUSB2PHY_PORT_TEST1, 133 QUSB2PHY_PORT_TEST2, 134 QUSB2PHY_PORT_POWERDOWN, 135 QUSB2PHY_INTR_CTRL, 136 }; 137 138 static const unsigned int msm8996_regs_layout[] = { 139 [QUSB2PHY_PLL_STATUS] = 0x38, 140 [QUSB2PHY_PORT_TUNE1] = 0x80, 141 [QUSB2PHY_PORT_TUNE2] = 0x84, 142 [QUSB2PHY_PORT_TUNE3] = 0x88, 143 [QUSB2PHY_PORT_TUNE4] = 0x8c, 144 [QUSB2PHY_PORT_TUNE5] = 0x90, 145 [QUSB2PHY_PORT_TEST1] = 0xb8, 146 [QUSB2PHY_PORT_TEST2] = 0x9c, 147 [QUSB2PHY_PORT_POWERDOWN] = 0xb4, 148 [QUSB2PHY_INTR_CTRL] = 0xbc, 149 }; 150 151 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = { 152 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), 153 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3), 154 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), 155 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0), 156 157 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 158 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 159 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 160 161 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 162 163 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), 164 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 165 }; 166 167 static const unsigned int msm8998_regs_layout[] = { 168 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, 169 [QUSB2PHY_PLL_STATUS] = 0x1a0, 170 [QUSB2PHY_PORT_TUNE1] = 0x23c, 171 [QUSB2PHY_PORT_TUNE2] = 0x240, 172 [QUSB2PHY_PORT_TUNE3] = 0x244, 173 [QUSB2PHY_PORT_TUNE4] = 0x248, 174 [QUSB2PHY_PORT_TEST1] = 0x24c, 175 [QUSB2PHY_PORT_TEST2] = 0x250, 176 [QUSB2PHY_PORT_POWERDOWN] = 0x210, 177 [QUSB2PHY_INTR_CTRL] = 0x22c, 178 }; 179 180 static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = { 181 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13), 182 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), 183 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), 184 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), 185 186 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5), 187 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09), 188 189 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), 190 }; 191 192 static const unsigned int qusb2_v2_regs_layout[] = { 193 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, 194 [QUSB2PHY_PLL_STATUS] = 0x1a0, 195 [QUSB2PHY_PORT_TUNE1] = 0x240, 196 [QUSB2PHY_PORT_TUNE2] = 0x244, 197 [QUSB2PHY_PORT_TUNE3] = 0x248, 198 [QUSB2PHY_PORT_TUNE4] = 0x24c, 199 [QUSB2PHY_PORT_TUNE5] = 0x250, 200 [QUSB2PHY_PORT_TEST1] = 0x254, 201 [QUSB2PHY_PORT_TEST2] = 0x258, 202 [QUSB2PHY_PORT_POWERDOWN] = 0x210, 203 [QUSB2PHY_INTR_CTRL] = 0x230, 204 }; 205 206 static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { 207 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), 208 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), 209 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), 210 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), 211 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), 212 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40), 213 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20), 214 QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21), 215 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0), 216 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58), 217 218 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30), 219 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29), 220 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca), 221 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04), 222 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03), 223 224 QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), 225 }; 226 227 struct qusb2_phy_cfg { 228 const struct qusb2_phy_init_tbl *tbl; 229 /* number of entries in the table */ 230 unsigned int tbl_num; 231 /* offset to PHY_CLK_SCHEME register in TCSR map */ 232 unsigned int clk_scheme_offset; 233 234 /* array of registers with different offsets */ 235 const unsigned int *regs; 236 unsigned int mask_core_ready; 237 unsigned int disable_ctrl; 238 unsigned int autoresume_en; 239 240 /* true if PHY has PLL_TEST register to select clk_scheme */ 241 bool has_pll_test; 242 243 /* true if TUNE1 register must be updated by fused value, else TUNE2 */ 244 bool update_tune1_with_efuse; 245 246 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */ 247 bool has_pll_override; 248 249 /* true if PHY default clk scheme is single-ended */ 250 bool se_clk_scheme_default; 251 }; 252 253 static const struct qusb2_phy_cfg msm8996_phy_cfg = { 254 .tbl = msm8996_init_tbl, 255 .tbl_num = ARRAY_SIZE(msm8996_init_tbl), 256 .regs = msm8996_regs_layout, 257 258 .has_pll_test = true, 259 .se_clk_scheme_default = true, 260 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 261 .mask_core_ready = PLL_LOCKED, 262 .autoresume_en = BIT(3), 263 }; 264 265 static const struct qusb2_phy_cfg msm8998_phy_cfg = { 266 .tbl = msm8998_init_tbl, 267 .tbl_num = ARRAY_SIZE(msm8998_init_tbl), 268 .regs = msm8998_regs_layout, 269 270 .disable_ctrl = POWER_DOWN, 271 .mask_core_ready = CORE_READY_STATUS, 272 .has_pll_override = true, 273 .se_clk_scheme_default = true, 274 .autoresume_en = BIT(0), 275 .update_tune1_with_efuse = true, 276 }; 277 278 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { 279 .tbl = qusb2_v2_init_tbl, 280 .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), 281 .regs = qusb2_v2_regs_layout, 282 283 .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN | 284 POWER_DOWN), 285 .mask_core_ready = CORE_READY_STATUS, 286 .has_pll_override = true, 287 .se_clk_scheme_default = true, 288 .autoresume_en = BIT(0), 289 .update_tune1_with_efuse = true, 290 }; 291 292 static const struct qusb2_phy_cfg sdm660_phy_cfg = { 293 .tbl = msm8996_init_tbl, 294 .tbl_num = ARRAY_SIZE(msm8996_init_tbl), 295 .regs = msm8996_regs_layout, 296 297 .has_pll_test = true, 298 .se_clk_scheme_default = false, 299 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 300 .mask_core_ready = PLL_LOCKED, 301 .autoresume_en = BIT(3), 302 }; 303 304 static const char * const qusb2_phy_vreg_names[] = { 305 "vdda-pll", "vdda-phy-dpdm", 306 }; 307 308 #define QUSB2_NUM_VREGS ARRAY_SIZE(qusb2_phy_vreg_names) 309 310 /* struct override_param - structure holding qusb2 v2 phy overriding param 311 * set override true if the device tree property exists and read and assign 312 * to value 313 */ 314 struct override_param { 315 bool override; 316 u8 value; 317 }; 318 319 /*struct override_params - structure holding qusb2 v2 phy overriding params 320 * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register 321 * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register 322 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register 323 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1 324 * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register 325 * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register 326 * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register 327 */ 328 struct override_params { 329 struct override_param imp_res_offset; 330 struct override_param hstx_trim; 331 struct override_param preemphasis; 332 struct override_param preemphasis_width; 333 struct override_param bias_ctrl; 334 struct override_param charge_ctrl; 335 struct override_param hsdisc_trim; 336 }; 337 338 /** 339 * struct qusb2_phy - structure holding qusb2 phy attributes 340 * 341 * @phy: generic phy 342 * @base: iomapped memory space for qubs2 phy 343 * 344 * @cfg_ahb_clk: AHB2PHY interface clock 345 * @ref_clk: phy reference clock 346 * @iface_clk: phy interface clock 347 * @phy_reset: phy reset control 348 * @vregs: regulator supplies bulk data 349 * 350 * @tcsr: TCSR syscon register map 351 * @cell: nvmem cell containing phy tuning value 352 * 353 * @overrides: pointer to structure for all overriding tuning params 354 * 355 * @cfg: phy config data 356 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme 357 * @phy_initialized: indicate if PHY has been initialized 358 * @mode: current PHY mode 359 */ 360 struct qusb2_phy { 361 struct phy *phy; 362 void __iomem *base; 363 364 struct clk *cfg_ahb_clk; 365 struct clk *ref_clk; 366 struct clk *iface_clk; 367 struct reset_control *phy_reset; 368 struct regulator_bulk_data vregs[QUSB2_NUM_VREGS]; 369 370 struct regmap *tcsr; 371 struct nvmem_cell *cell; 372 373 struct override_params overrides; 374 375 const struct qusb2_phy_cfg *cfg; 376 bool has_se_clk_scheme; 377 bool phy_initialized; 378 enum phy_mode mode; 379 }; 380 381 static inline void qusb2_write_mask(void __iomem *base, u32 offset, 382 u32 val, u32 mask) 383 { 384 u32 reg; 385 386 reg = readl(base + offset); 387 reg &= ~mask; 388 reg |= val & mask; 389 writel(reg, base + offset); 390 391 /* Ensure above write is completed */ 392 readl(base + offset); 393 } 394 395 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) 396 { 397 u32 reg; 398 399 reg = readl(base + offset); 400 reg |= val; 401 writel(reg, base + offset); 402 403 /* Ensure above write is completed */ 404 readl(base + offset); 405 } 406 407 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val) 408 { 409 u32 reg; 410 411 reg = readl(base + offset); 412 reg &= ~val; 413 writel(reg, base + offset); 414 415 /* Ensure above write is completed */ 416 readl(base + offset); 417 } 418 419 static inline 420 void qcom_qusb2_phy_configure(void __iomem *base, 421 const unsigned int *regs, 422 const struct qusb2_phy_init_tbl tbl[], int num) 423 { 424 int i; 425 426 for (i = 0; i < num; i++) { 427 if (tbl[i].in_layout) 428 writel(tbl[i].val, base + regs[tbl[i].offset]); 429 else 430 writel(tbl[i].val, base + tbl[i].offset); 431 } 432 } 433 434 /* 435 * Update board specific PHY tuning override values if specified from 436 * device tree. 437 */ 438 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy) 439 { 440 const struct qusb2_phy_cfg *cfg = qphy->cfg; 441 struct override_params *or = &qphy->overrides; 442 443 if (or->imp_res_offset.override) 444 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, 445 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT, 446 IMP_RES_OFFSET_MASK); 447 448 if (or->bias_ctrl.override) 449 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2, 450 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT, 451 BIAS_CTRL2_RES_OFFSET_MASK); 452 453 if (or->charge_ctrl.override) 454 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2, 455 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT, 456 CHG_CTRL2_OFFSET_MASK); 457 458 if (or->hstx_trim.override) 459 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 460 or->hstx_trim.value << HSTX_TRIM_SHIFT, 461 HSTX_TRIM_MASK); 462 463 if (or->preemphasis.override) 464 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 465 or->preemphasis.value << PREEMPHASIS_EN_SHIFT, 466 PREEMPHASIS_EN_MASK); 467 468 if (or->preemphasis_width.override) { 469 if (or->preemphasis_width.value == 470 QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT) 471 qusb2_setbits(qphy->base, 472 cfg->regs[QUSB2PHY_PORT_TUNE1], 473 PREEMPH_WIDTH_HALF_BIT); 474 else 475 qusb2_clrbits(qphy->base, 476 cfg->regs[QUSB2PHY_PORT_TUNE1], 477 PREEMPH_WIDTH_HALF_BIT); 478 } 479 480 if (or->hsdisc_trim.override) 481 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], 482 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT, 483 HSDISC_TRIM_MASK); 484 } 485 486 /* 487 * Fetches HS Tx tuning value from nvmem and sets the 488 * QUSB2PHY_PORT_TUNE1/2 register. 489 * For error case, skip setting the value and use the default value. 490 */ 491 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) 492 { 493 struct device *dev = &qphy->phy->dev; 494 const struct qusb2_phy_cfg *cfg = qphy->cfg; 495 u8 *val; 496 497 /* efuse register is optional */ 498 if (!qphy->cell) 499 return; 500 501 /* 502 * Read efuse register having TUNE2/1 parameter's high nibble. 503 * If efuse register shows value as 0x0 (indicating value is not 504 * fused), or if we fail to find a valid efuse register setting, 505 * then use default value for high nibble that we have already 506 * set while configuring the phy. 507 */ 508 val = nvmem_cell_read(qphy->cell, NULL); 509 if (IS_ERR(val) || !val[0]) { 510 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); 511 return; 512 } 513 514 /* Fused TUNE1/2 value is the higher nibble only */ 515 if (cfg->update_tune1_with_efuse) 516 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 517 val[0] << HSTX_TRIM_SHIFT, 518 HSTX_TRIM_MASK); 519 else 520 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], 521 val[0] << HSTX_TRIM_SHIFT, 522 HSTX_TRIM_MASK); 523 } 524 525 static int qusb2_phy_set_mode(struct phy *phy, 526 enum phy_mode mode, int submode) 527 { 528 struct qusb2_phy *qphy = phy_get_drvdata(phy); 529 530 qphy->mode = mode; 531 532 return 0; 533 } 534 535 static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev) 536 { 537 struct qusb2_phy *qphy = dev_get_drvdata(dev); 538 const struct qusb2_phy_cfg *cfg = qphy->cfg; 539 u32 intr_mask; 540 541 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode); 542 543 if (!qphy->phy_initialized) { 544 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 545 return 0; 546 } 547 548 /* 549 * Enable DP/DM interrupts to detect line state changes based on current 550 * speed. In other words, enable the triggers _opposite_ of what the 551 * current D+/D- levels are e.g. if currently D+ high, D- low 552 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high 553 */ 554 intr_mask = DPSE_INTR_EN | DMSE_INTR_EN; 555 switch (qphy->mode) { 556 case PHY_MODE_USB_HOST_HS: 557 case PHY_MODE_USB_HOST_FS: 558 case PHY_MODE_USB_DEVICE_HS: 559 case PHY_MODE_USB_DEVICE_FS: 560 intr_mask |= DMSE_INTR_HIGH_SEL; 561 break; 562 case PHY_MODE_USB_HOST_LS: 563 case PHY_MODE_USB_DEVICE_LS: 564 intr_mask |= DPSE_INTR_HIGH_SEL; 565 break; 566 default: 567 /* No device connected, enable both DP/DM high interrupt */ 568 intr_mask |= DMSE_INTR_HIGH_SEL; 569 intr_mask |= DPSE_INTR_HIGH_SEL; 570 break; 571 } 572 573 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); 574 575 /* hold core PLL into reset */ 576 if (cfg->has_pll_override) { 577 qusb2_setbits(qphy->base, 578 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], 579 CORE_PLL_EN_FROM_RESET | CORE_RESET | 580 CORE_RESET_MUX); 581 } 582 583 /* enable phy auto-resume only if device is connected on bus */ 584 if (qphy->mode != PHY_MODE_INVALID) { 585 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], 586 cfg->autoresume_en); 587 /* Autoresume bit has to be toggled in order to enable it */ 588 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], 589 cfg->autoresume_en); 590 } 591 592 if (!qphy->has_se_clk_scheme) 593 clk_disable_unprepare(qphy->ref_clk); 594 595 clk_disable_unprepare(qphy->cfg_ahb_clk); 596 clk_disable_unprepare(qphy->iface_clk); 597 598 return 0; 599 } 600 601 static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev) 602 { 603 struct qusb2_phy *qphy = dev_get_drvdata(dev); 604 const struct qusb2_phy_cfg *cfg = qphy->cfg; 605 int ret; 606 607 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode); 608 609 if (!qphy->phy_initialized) { 610 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 611 return 0; 612 } 613 614 ret = clk_prepare_enable(qphy->iface_clk); 615 if (ret) { 616 dev_err(dev, "failed to enable iface_clk, %d\n", ret); 617 return ret; 618 } 619 620 ret = clk_prepare_enable(qphy->cfg_ahb_clk); 621 if (ret) { 622 dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret); 623 goto disable_iface_clk; 624 } 625 626 if (!qphy->has_se_clk_scheme) { 627 ret = clk_prepare_enable(qphy->ref_clk); 628 if (ret) { 629 dev_err(dev, "failed to enable ref clk, %d\n", ret); 630 goto disable_ahb_clk; 631 } 632 } 633 634 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); 635 636 /* bring core PLL out of reset */ 637 if (cfg->has_pll_override) { 638 qusb2_clrbits(qphy->base, 639 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], 640 CORE_RESET | CORE_RESET_MUX); 641 } 642 643 return 0; 644 645 disable_ahb_clk: 646 clk_disable_unprepare(qphy->cfg_ahb_clk); 647 disable_iface_clk: 648 clk_disable_unprepare(qphy->iface_clk); 649 650 return ret; 651 } 652 653 static int qusb2_phy_init(struct phy *phy) 654 { 655 struct qusb2_phy *qphy = phy_get_drvdata(phy); 656 const struct qusb2_phy_cfg *cfg = qphy->cfg; 657 unsigned int val = 0; 658 unsigned int clk_scheme; 659 int ret; 660 661 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__); 662 663 /* turn on regulator supplies */ 664 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 665 if (ret) 666 return ret; 667 668 ret = clk_prepare_enable(qphy->iface_clk); 669 if (ret) { 670 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret); 671 goto poweroff_phy; 672 } 673 674 /* enable ahb interface clock to program phy */ 675 ret = clk_prepare_enable(qphy->cfg_ahb_clk); 676 if (ret) { 677 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); 678 goto disable_iface_clk; 679 } 680 681 /* Perform phy reset */ 682 ret = reset_control_assert(qphy->phy_reset); 683 if (ret) { 684 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); 685 goto disable_ahb_clk; 686 } 687 688 /* 100 us delay to keep PHY in reset mode */ 689 usleep_range(100, 150); 690 691 ret = reset_control_deassert(qphy->phy_reset); 692 if (ret) { 693 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); 694 goto disable_ahb_clk; 695 } 696 697 /* Disable the PHY */ 698 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], 699 qphy->cfg->disable_ctrl); 700 701 if (cfg->has_pll_test) { 702 /* save reset value to override reference clock scheme later */ 703 val = readl(qphy->base + QUSB2PHY_PLL_TEST); 704 } 705 706 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, 707 cfg->tbl_num); 708 709 /* Override board specific PHY tuning values */ 710 qusb2_phy_override_phy_params(qphy); 711 712 /* Set efuse value for tuning the PHY */ 713 qusb2_phy_set_tune2_param(qphy); 714 715 /* Enable the PHY */ 716 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], 717 POWER_DOWN); 718 719 /* Required to get phy pll lock successfully */ 720 usleep_range(150, 160); 721 722 /* 723 * Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME 724 * register in the TCSR so, if there's none, use the default 725 * value hardcoded in the configuration. 726 */ 727 qphy->has_se_clk_scheme = cfg->se_clk_scheme_default; 728 729 /* 730 * read TCSR_PHY_CLK_SCHEME register to check if single-ended 731 * clock scheme is selected. If yes, then disable differential 732 * ref_clk and use single-ended clock, otherwise use differential 733 * ref_clk only. 734 */ 735 if (qphy->tcsr) { 736 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, 737 &clk_scheme); 738 if (ret) { 739 dev_err(&phy->dev, "failed to read clk scheme reg\n"); 740 goto assert_phy_reset; 741 } 742 743 /* is it a differential clock scheme ? */ 744 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) { 745 dev_vdbg(&phy->dev, "%s(): select differential clk\n", 746 __func__); 747 qphy->has_se_clk_scheme = false; 748 } else { 749 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n", 750 __func__); 751 } 752 } 753 754 if (!qphy->has_se_clk_scheme) { 755 ret = clk_prepare_enable(qphy->ref_clk); 756 if (ret) { 757 dev_err(&phy->dev, "failed to enable ref clk, %d\n", 758 ret); 759 goto assert_phy_reset; 760 } 761 } 762 763 if (cfg->has_pll_test) { 764 if (!qphy->has_se_clk_scheme) 765 val &= ~CLK_REF_SEL; 766 else 767 val |= CLK_REF_SEL; 768 769 writel(val, qphy->base + QUSB2PHY_PLL_TEST); 770 771 /* ensure above write is through */ 772 readl(qphy->base + QUSB2PHY_PLL_TEST); 773 } 774 775 /* Required to get phy pll lock successfully */ 776 usleep_range(100, 110); 777 778 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); 779 if (!(val & cfg->mask_core_ready)) { 780 dev_err(&phy->dev, 781 "QUSB2PHY pll lock failed: status reg = %x\n", val); 782 ret = -EBUSY; 783 goto disable_ref_clk; 784 } 785 qphy->phy_initialized = true; 786 787 return 0; 788 789 disable_ref_clk: 790 if (!qphy->has_se_clk_scheme) 791 clk_disable_unprepare(qphy->ref_clk); 792 assert_phy_reset: 793 reset_control_assert(qphy->phy_reset); 794 disable_ahb_clk: 795 clk_disable_unprepare(qphy->cfg_ahb_clk); 796 disable_iface_clk: 797 clk_disable_unprepare(qphy->iface_clk); 798 poweroff_phy: 799 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 800 801 return ret; 802 } 803 804 static int qusb2_phy_exit(struct phy *phy) 805 { 806 struct qusb2_phy *qphy = phy_get_drvdata(phy); 807 808 /* Disable the PHY */ 809 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], 810 qphy->cfg->disable_ctrl); 811 812 if (!qphy->has_se_clk_scheme) 813 clk_disable_unprepare(qphy->ref_clk); 814 815 reset_control_assert(qphy->phy_reset); 816 817 clk_disable_unprepare(qphy->cfg_ahb_clk); 818 clk_disable_unprepare(qphy->iface_clk); 819 820 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 821 822 qphy->phy_initialized = false; 823 824 return 0; 825 } 826 827 static const struct phy_ops qusb2_phy_gen_ops = { 828 .init = qusb2_phy_init, 829 .exit = qusb2_phy_exit, 830 .set_mode = qusb2_phy_set_mode, 831 .owner = THIS_MODULE, 832 }; 833 834 static const struct of_device_id qusb2_phy_of_match_table[] = { 835 { 836 .compatible = "qcom,ipq8074-qusb2-phy", 837 .data = &msm8996_phy_cfg, 838 }, { 839 .compatible = "qcom,msm8996-qusb2-phy", 840 .data = &msm8996_phy_cfg, 841 }, { 842 .compatible = "qcom,msm8998-qusb2-phy", 843 .data = &msm8998_phy_cfg, 844 }, { 845 .compatible = "qcom,sdm660-qusb2-phy", 846 .data = &sdm660_phy_cfg, 847 }, { 848 /* 849 * Deprecated. Only here to support legacy device 850 * trees that didn't include "qcom,qusb2-v2-phy" 851 */ 852 .compatible = "qcom,sdm845-qusb2-phy", 853 .data = &qusb2_v2_phy_cfg, 854 }, { 855 .compatible = "qcom,qusb2-v2-phy", 856 .data = &qusb2_v2_phy_cfg, 857 }, 858 { }, 859 }; 860 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table); 861 862 static const struct dev_pm_ops qusb2_phy_pm_ops = { 863 SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend, 864 qusb2_phy_runtime_resume, NULL) 865 }; 866 867 static int qusb2_phy_probe(struct platform_device *pdev) 868 { 869 struct device *dev = &pdev->dev; 870 struct qusb2_phy *qphy; 871 struct phy_provider *phy_provider; 872 struct phy *generic_phy; 873 int ret, i; 874 int num; 875 u32 value; 876 struct override_params *or; 877 878 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 879 if (!qphy) 880 return -ENOMEM; 881 or = &qphy->overrides; 882 883 qphy->base = devm_platform_ioremap_resource(pdev, 0); 884 if (IS_ERR(qphy->base)) 885 return PTR_ERR(qphy->base); 886 887 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); 888 if (IS_ERR(qphy->cfg_ahb_clk)) { 889 ret = PTR_ERR(qphy->cfg_ahb_clk); 890 if (ret != -EPROBE_DEFER) 891 dev_err(dev, "failed to get cfg ahb clk, %d\n", ret); 892 return ret; 893 } 894 895 qphy->ref_clk = devm_clk_get(dev, "ref"); 896 if (IS_ERR(qphy->ref_clk)) { 897 ret = PTR_ERR(qphy->ref_clk); 898 if (ret != -EPROBE_DEFER) 899 dev_err(dev, "failed to get ref clk, %d\n", ret); 900 return ret; 901 } 902 903 qphy->iface_clk = devm_clk_get_optional(dev, "iface"); 904 if (IS_ERR(qphy->iface_clk)) 905 return PTR_ERR(qphy->iface_clk); 906 907 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0); 908 if (IS_ERR(qphy->phy_reset)) { 909 dev_err(dev, "failed to get phy core reset\n"); 910 return PTR_ERR(qphy->phy_reset); 911 } 912 913 num = ARRAY_SIZE(qphy->vregs); 914 for (i = 0; i < num; i++) 915 qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; 916 917 ret = devm_regulator_bulk_get(dev, num, qphy->vregs); 918 if (ret) { 919 if (ret != -EPROBE_DEFER) 920 dev_err(dev, "failed to get regulator supplies: %d\n", 921 ret); 922 return ret; 923 } 924 925 /* Get the specific init parameters of QMP phy */ 926 qphy->cfg = of_device_get_match_data(dev); 927 928 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, 929 "qcom,tcsr-syscon"); 930 if (IS_ERR(qphy->tcsr)) { 931 dev_dbg(dev, "failed to lookup TCSR regmap\n"); 932 qphy->tcsr = NULL; 933 } 934 935 qphy->cell = devm_nvmem_cell_get(dev, NULL); 936 if (IS_ERR(qphy->cell)) { 937 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER) 938 return -EPROBE_DEFER; 939 qphy->cell = NULL; 940 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n"); 941 } 942 943 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value", 944 &value)) { 945 or->imp_res_offset.value = (u8)value; 946 or->imp_res_offset.override = true; 947 } 948 949 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value", 950 &value)) { 951 or->bias_ctrl.value = (u8)value; 952 or->bias_ctrl.override = true; 953 } 954 955 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value", 956 &value)) { 957 or->charge_ctrl.value = (u8)value; 958 or->charge_ctrl.override = true; 959 } 960 961 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", 962 &value)) { 963 or->hstx_trim.value = (u8)value; 964 or->hstx_trim.override = true; 965 } 966 967 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level", 968 &value)) { 969 or->preemphasis.value = (u8)value; 970 or->preemphasis.override = true; 971 } 972 973 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width", 974 &value)) { 975 or->preemphasis_width.value = (u8)value; 976 or->preemphasis_width.override = true; 977 } 978 979 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value", 980 &value)) { 981 or->hsdisc_trim.value = (u8)value; 982 or->hsdisc_trim.override = true; 983 } 984 985 pm_runtime_set_active(dev); 986 pm_runtime_enable(dev); 987 /* 988 * Prevent runtime pm from being ON by default. Users can enable 989 * it using power/control in sysfs. 990 */ 991 pm_runtime_forbid(dev); 992 993 generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops); 994 if (IS_ERR(generic_phy)) { 995 ret = PTR_ERR(generic_phy); 996 dev_err(dev, "failed to create phy, %d\n", ret); 997 pm_runtime_disable(dev); 998 return ret; 999 } 1000 qphy->phy = generic_phy; 1001 1002 dev_set_drvdata(dev, qphy); 1003 phy_set_drvdata(generic_phy, qphy); 1004 1005 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1006 if (!IS_ERR(phy_provider)) 1007 dev_info(dev, "Registered Qcom-QUSB2 phy\n"); 1008 else 1009 pm_runtime_disable(dev); 1010 1011 return PTR_ERR_OR_ZERO(phy_provider); 1012 } 1013 1014 static struct platform_driver qusb2_phy_driver = { 1015 .probe = qusb2_phy_probe, 1016 .driver = { 1017 .name = "qcom-qusb2-phy", 1018 .pm = &qusb2_phy_pm_ops, 1019 .of_match_table = qusb2_phy_of_match_table, 1020 }, 1021 }; 1022 1023 module_platform_driver(qusb2_phy_driver); 1024 1025 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 1026 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver"); 1027 MODULE_LICENSE("GPL v2"); 1028