1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, 2019, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/kernel.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/nvmem-consumer.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 24 25 #define QUSB2PHY_PLL 0x0 26 #define QUSB2PHY_PLL_TEST 0x04 27 #define CLK_REF_SEL BIT(7) 28 29 #define QUSB2PHY_PLL_TUNE 0x08 30 #define QUSB2PHY_PLL_USER_CTL1 0x0c 31 #define QUSB2PHY_PLL_USER_CTL2 0x10 32 #define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c 33 #define QUSB2PHY_PLL_PWR_CTRL 0x18 34 35 /* QUSB2PHY_PLL_STATUS register bits */ 36 #define PLL_LOCKED BIT(5) 37 38 /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ 39 #define CORE_READY_STATUS BIT(0) 40 41 /* QUSB2PHY_PORT_POWERDOWN register bits */ 42 #define CLAMP_N_EN BIT(5) 43 #define FREEZIO_N BIT(1) 44 #define POWER_DOWN BIT(0) 45 46 /* QUSB2PHY_PWR_CTRL1 register bits */ 47 #define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) 48 #define PWR_CTRL1_CLAMP_N_EN BIT(1) 49 50 #define QUSB2PHY_REFCLK_ENABLE BIT(0) 51 52 #define PHY_CLK_SCHEME_SEL BIT(0) 53 54 /* QUSB2PHY_INTR_CTRL register bits */ 55 #define DMSE_INTR_HIGH_SEL BIT(4) 56 #define DPSE_INTR_HIGH_SEL BIT(3) 57 #define CHG_DET_INTR_EN BIT(2) 58 #define DMSE_INTR_EN BIT(1) 59 #define DPSE_INTR_EN BIT(0) 60 61 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ 62 #define CORE_PLL_EN_FROM_RESET BIT(4) 63 #define CORE_RESET BIT(5) 64 #define CORE_RESET_MUX BIT(6) 65 66 /* QUSB2PHY_IMP_CTRL1 register bits */ 67 #define IMP_RES_OFFSET_MASK GENMASK(5, 0) 68 #define IMP_RES_OFFSET_SHIFT 0x0 69 70 /* QUSB2PHY_PLL_BIAS_CONTROL_2 register bits */ 71 #define BIAS_CTRL2_RES_OFFSET_MASK GENMASK(5, 0) 72 #define BIAS_CTRL2_RES_OFFSET_SHIFT 0x0 73 74 /* QUSB2PHY_CHG_CONTROL_2 register bits */ 75 #define CHG_CTRL2_OFFSET_MASK GENMASK(5, 4) 76 #define CHG_CTRL2_OFFSET_SHIFT 0x4 77 78 /* QUSB2PHY_PORT_TUNE1 register bits */ 79 #define HSTX_TRIM_MASK GENMASK(7, 4) 80 #define HSTX_TRIM_SHIFT 0x4 81 #define PREEMPH_WIDTH_HALF_BIT BIT(2) 82 #define PREEMPHASIS_EN_MASK GENMASK(1, 0) 83 #define PREEMPHASIS_EN_SHIFT 0x0 84 85 /* QUSB2PHY_PORT_TUNE2 register bits */ 86 #define HSDISC_TRIM_MASK GENMASK(1, 0) 87 #define HSDISC_TRIM_SHIFT 0x0 88 89 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 90 #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c 91 #define QUSB2PHY_PLL_CMODE 0x2c 92 #define QUSB2PHY_PLL_LOCK_DELAY 0x184 93 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4 94 #define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194 95 #define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198 96 #define QUSB2PHY_PWR_CTRL2 0x214 97 #define QUSB2PHY_IMP_CTRL1 0x220 98 #define QUSB2PHY_IMP_CTRL2 0x224 99 #define QUSB2PHY_CHG_CTRL2 0x23c 100 101 struct qusb2_phy_init_tbl { 102 unsigned int offset; 103 unsigned int val; 104 /* 105 * register part of layout ? 106 * if yes, then offset gives index in the reg-layout 107 */ 108 int in_layout; 109 }; 110 111 #define QUSB2_PHY_INIT_CFG(o, v) \ 112 { \ 113 .offset = o, \ 114 .val = v, \ 115 } 116 117 #define QUSB2_PHY_INIT_CFG_L(o, v) \ 118 { \ 119 .offset = o, \ 120 .val = v, \ 121 .in_layout = 1, \ 122 } 123 124 /* set of registers with offsets different per-PHY */ 125 enum qusb2phy_reg_layout { 126 QUSB2PHY_PLL_CORE_INPUT_OVERRIDE, 127 QUSB2PHY_PLL_STATUS, 128 QUSB2PHY_PORT_TUNE1, 129 QUSB2PHY_PORT_TUNE2, 130 QUSB2PHY_PORT_TUNE3, 131 QUSB2PHY_PORT_TUNE4, 132 QUSB2PHY_PORT_TUNE5, 133 QUSB2PHY_PORT_TEST1, 134 QUSB2PHY_PORT_TEST2, 135 QUSB2PHY_PORT_POWERDOWN, 136 QUSB2PHY_INTR_CTRL, 137 }; 138 139 static const struct qusb2_phy_init_tbl ipq6018_init_tbl[] = { 140 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL, 0x14), 141 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xF8), 142 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xB3), 143 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), 144 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xC0), 145 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 146 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 147 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 148 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x00), 149 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 150 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 151 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TEST, 0x80), 152 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9F), 153 }; 154 155 static const unsigned int ipq6018_regs_layout[] = { 156 [QUSB2PHY_PLL_STATUS] = 0x38, 157 [QUSB2PHY_PORT_TUNE1] = 0x80, 158 [QUSB2PHY_PORT_TUNE2] = 0x84, 159 [QUSB2PHY_PORT_TUNE3] = 0x88, 160 [QUSB2PHY_PORT_TUNE4] = 0x8C, 161 [QUSB2PHY_PORT_TUNE5] = 0x90, 162 [QUSB2PHY_PORT_TEST1] = 0x98, 163 [QUSB2PHY_PORT_TEST2] = 0x9C, 164 [QUSB2PHY_PORT_POWERDOWN] = 0xB4, 165 [QUSB2PHY_INTR_CTRL] = 0xBC, 166 }; 167 168 static const unsigned int msm8996_regs_layout[] = { 169 [QUSB2PHY_PLL_STATUS] = 0x38, 170 [QUSB2PHY_PORT_TUNE1] = 0x80, 171 [QUSB2PHY_PORT_TUNE2] = 0x84, 172 [QUSB2PHY_PORT_TUNE3] = 0x88, 173 [QUSB2PHY_PORT_TUNE4] = 0x8c, 174 [QUSB2PHY_PORT_TUNE5] = 0x90, 175 [QUSB2PHY_PORT_TEST1] = 0xb8, 176 [QUSB2PHY_PORT_TEST2] = 0x9c, 177 [QUSB2PHY_PORT_POWERDOWN] = 0xb4, 178 [QUSB2PHY_INTR_CTRL] = 0xbc, 179 }; 180 181 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = { 182 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), 183 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3), 184 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), 185 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0), 186 187 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 188 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 189 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 190 191 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 192 193 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), 194 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 195 }; 196 197 static const unsigned int msm8998_regs_layout[] = { 198 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, 199 [QUSB2PHY_PLL_STATUS] = 0x1a0, 200 [QUSB2PHY_PORT_TUNE1] = 0x23c, 201 [QUSB2PHY_PORT_TUNE2] = 0x240, 202 [QUSB2PHY_PORT_TUNE3] = 0x244, 203 [QUSB2PHY_PORT_TUNE4] = 0x248, 204 [QUSB2PHY_PORT_TEST1] = 0x24c, 205 [QUSB2PHY_PORT_TEST2] = 0x250, 206 [QUSB2PHY_PORT_POWERDOWN] = 0x210, 207 [QUSB2PHY_INTR_CTRL] = 0x22c, 208 }; 209 210 static const struct qusb2_phy_init_tbl msm8998_init_tbl[] = { 211 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x13), 212 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), 213 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), 214 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), 215 216 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xa5), 217 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x09), 218 219 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), 220 }; 221 222 static const unsigned int qusb2_v2_regs_layout[] = { 223 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, 224 [QUSB2PHY_PLL_STATUS] = 0x1a0, 225 [QUSB2PHY_PORT_TUNE1] = 0x240, 226 [QUSB2PHY_PORT_TUNE2] = 0x244, 227 [QUSB2PHY_PORT_TUNE3] = 0x248, 228 [QUSB2PHY_PORT_TUNE4] = 0x24c, 229 [QUSB2PHY_PORT_TUNE5] = 0x250, 230 [QUSB2PHY_PORT_TEST1] = 0x254, 231 [QUSB2PHY_PORT_TEST2] = 0x258, 232 [QUSB2PHY_PORT_POWERDOWN] = 0x210, 233 [QUSB2PHY_INTR_CTRL] = 0x230, 234 }; 235 236 static const struct qusb2_phy_init_tbl qusb2_v2_init_tbl[] = { 237 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), 238 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), 239 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), 240 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), 241 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), 242 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40), 243 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20), 244 QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21), 245 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0), 246 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58), 247 248 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30), 249 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29), 250 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca), 251 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04), 252 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03), 253 254 QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), 255 }; 256 257 struct qusb2_phy_cfg { 258 const struct qusb2_phy_init_tbl *tbl; 259 /* number of entries in the table */ 260 unsigned int tbl_num; 261 /* offset to PHY_CLK_SCHEME register in TCSR map */ 262 unsigned int clk_scheme_offset; 263 264 /* array of registers with different offsets */ 265 const unsigned int *regs; 266 unsigned int mask_core_ready; 267 unsigned int disable_ctrl; 268 unsigned int autoresume_en; 269 270 /* true if PHY has PLL_TEST register to select clk_scheme */ 271 bool has_pll_test; 272 273 /* true if TUNE1 register must be updated by fused value, else TUNE2 */ 274 bool update_tune1_with_efuse; 275 276 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */ 277 bool has_pll_override; 278 279 /* true if PHY default clk scheme is single-ended */ 280 bool se_clk_scheme_default; 281 }; 282 283 static const struct qusb2_phy_cfg msm8996_phy_cfg = { 284 .tbl = msm8996_init_tbl, 285 .tbl_num = ARRAY_SIZE(msm8996_init_tbl), 286 .regs = msm8996_regs_layout, 287 288 .has_pll_test = true, 289 .se_clk_scheme_default = true, 290 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 291 .mask_core_ready = PLL_LOCKED, 292 .autoresume_en = BIT(3), 293 }; 294 295 static const struct qusb2_phy_cfg msm8998_phy_cfg = { 296 .tbl = msm8998_init_tbl, 297 .tbl_num = ARRAY_SIZE(msm8998_init_tbl), 298 .regs = msm8998_regs_layout, 299 300 .disable_ctrl = POWER_DOWN, 301 .mask_core_ready = CORE_READY_STATUS, 302 .has_pll_override = true, 303 .se_clk_scheme_default = true, 304 .autoresume_en = BIT(0), 305 .update_tune1_with_efuse = true, 306 }; 307 308 static const struct qusb2_phy_cfg ipq6018_phy_cfg = { 309 .tbl = ipq6018_init_tbl, 310 .tbl_num = ARRAY_SIZE(ipq6018_init_tbl), 311 .regs = ipq6018_regs_layout, 312 313 .disable_ctrl = POWER_DOWN, 314 .mask_core_ready = PLL_LOCKED, 315 /* autoresume not used */ 316 .autoresume_en = BIT(0), 317 }; 318 319 static const struct qusb2_phy_cfg qusb2_v2_phy_cfg = { 320 .tbl = qusb2_v2_init_tbl, 321 .tbl_num = ARRAY_SIZE(qusb2_v2_init_tbl), 322 .regs = qusb2_v2_regs_layout, 323 324 .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN | 325 POWER_DOWN), 326 .mask_core_ready = CORE_READY_STATUS, 327 .has_pll_override = true, 328 .se_clk_scheme_default = true, 329 .autoresume_en = BIT(0), 330 .update_tune1_with_efuse = true, 331 }; 332 333 static const struct qusb2_phy_cfg sdm660_phy_cfg = { 334 .tbl = msm8996_init_tbl, 335 .tbl_num = ARRAY_SIZE(msm8996_init_tbl), 336 .regs = msm8996_regs_layout, 337 338 .has_pll_test = true, 339 .se_clk_scheme_default = false, 340 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 341 .mask_core_ready = PLL_LOCKED, 342 .autoresume_en = BIT(3), 343 }; 344 345 static const char * const qusb2_phy_vreg_names[] = { 346 "vdda-pll", "vdda-phy-dpdm", 347 }; 348 349 #define QUSB2_NUM_VREGS ARRAY_SIZE(qusb2_phy_vreg_names) 350 351 /* struct override_param - structure holding qusb2 v2 phy overriding param 352 * set override true if the device tree property exists and read and assign 353 * to value 354 */ 355 struct override_param { 356 bool override; 357 u8 value; 358 }; 359 360 /*struct override_params - structure holding qusb2 v2 phy overriding params 361 * @imp_res_offset: rescode offset to be updated in IMP_CTRL1 register 362 * @hstx_trim: HSTX_TRIM to be updated in TUNE1 register 363 * @preemphasis: Amplitude Pre-Emphasis to be updated in TUNE1 register 364 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1 365 * @bias_ctrl: bias ctrl to be updated in BIAS_CONTROL_2 register 366 * @charge_ctrl: charge ctrl to be updated in CHG_CTRL2 register 367 * @hsdisc_trim: disconnect threshold to be updated in TUNE2 register 368 */ 369 struct override_params { 370 struct override_param imp_res_offset; 371 struct override_param hstx_trim; 372 struct override_param preemphasis; 373 struct override_param preemphasis_width; 374 struct override_param bias_ctrl; 375 struct override_param charge_ctrl; 376 struct override_param hsdisc_trim; 377 }; 378 379 /** 380 * struct qusb2_phy - structure holding qusb2 phy attributes 381 * 382 * @phy: generic phy 383 * @base: iomapped memory space for qubs2 phy 384 * 385 * @cfg_ahb_clk: AHB2PHY interface clock 386 * @ref_clk: phy reference clock 387 * @iface_clk: phy interface clock 388 * @phy_reset: phy reset control 389 * @vregs: regulator supplies bulk data 390 * 391 * @tcsr: TCSR syscon register map 392 * @cell: nvmem cell containing phy tuning value 393 * 394 * @overrides: pointer to structure for all overriding tuning params 395 * 396 * @cfg: phy config data 397 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme 398 * @phy_initialized: indicate if PHY has been initialized 399 * @mode: current PHY mode 400 */ 401 struct qusb2_phy { 402 struct phy *phy; 403 void __iomem *base; 404 405 struct clk *cfg_ahb_clk; 406 struct clk *ref_clk; 407 struct clk *iface_clk; 408 struct reset_control *phy_reset; 409 struct regulator_bulk_data vregs[QUSB2_NUM_VREGS]; 410 411 struct regmap *tcsr; 412 struct nvmem_cell *cell; 413 414 struct override_params overrides; 415 416 const struct qusb2_phy_cfg *cfg; 417 bool has_se_clk_scheme; 418 bool phy_initialized; 419 enum phy_mode mode; 420 }; 421 422 static inline void qusb2_write_mask(void __iomem *base, u32 offset, 423 u32 val, u32 mask) 424 { 425 u32 reg; 426 427 reg = readl(base + offset); 428 reg &= ~mask; 429 reg |= val & mask; 430 writel(reg, base + offset); 431 432 /* Ensure above write is completed */ 433 readl(base + offset); 434 } 435 436 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) 437 { 438 u32 reg; 439 440 reg = readl(base + offset); 441 reg |= val; 442 writel(reg, base + offset); 443 444 /* Ensure above write is completed */ 445 readl(base + offset); 446 } 447 448 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val) 449 { 450 u32 reg; 451 452 reg = readl(base + offset); 453 reg &= ~val; 454 writel(reg, base + offset); 455 456 /* Ensure above write is completed */ 457 readl(base + offset); 458 } 459 460 static inline 461 void qcom_qusb2_phy_configure(void __iomem *base, 462 const unsigned int *regs, 463 const struct qusb2_phy_init_tbl tbl[], int num) 464 { 465 int i; 466 467 for (i = 0; i < num; i++) { 468 if (tbl[i].in_layout) 469 writel(tbl[i].val, base + regs[tbl[i].offset]); 470 else 471 writel(tbl[i].val, base + tbl[i].offset); 472 } 473 } 474 475 /* 476 * Update board specific PHY tuning override values if specified from 477 * device tree. 478 */ 479 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy) 480 { 481 const struct qusb2_phy_cfg *cfg = qphy->cfg; 482 struct override_params *or = &qphy->overrides; 483 484 if (or->imp_res_offset.override) 485 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, 486 or->imp_res_offset.value << IMP_RES_OFFSET_SHIFT, 487 IMP_RES_OFFSET_MASK); 488 489 if (or->bias_ctrl.override) 490 qusb2_write_mask(qphy->base, QUSB2PHY_PLL_BIAS_CONTROL_2, 491 or->bias_ctrl.value << BIAS_CTRL2_RES_OFFSET_SHIFT, 492 BIAS_CTRL2_RES_OFFSET_MASK); 493 494 if (or->charge_ctrl.override) 495 qusb2_write_mask(qphy->base, QUSB2PHY_CHG_CTRL2, 496 or->charge_ctrl.value << CHG_CTRL2_OFFSET_SHIFT, 497 CHG_CTRL2_OFFSET_MASK); 498 499 if (or->hstx_trim.override) 500 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 501 or->hstx_trim.value << HSTX_TRIM_SHIFT, 502 HSTX_TRIM_MASK); 503 504 if (or->preemphasis.override) 505 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 506 or->preemphasis.value << PREEMPHASIS_EN_SHIFT, 507 PREEMPHASIS_EN_MASK); 508 509 if (or->preemphasis_width.override) { 510 if (or->preemphasis_width.value == 511 QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT) 512 qusb2_setbits(qphy->base, 513 cfg->regs[QUSB2PHY_PORT_TUNE1], 514 PREEMPH_WIDTH_HALF_BIT); 515 else 516 qusb2_clrbits(qphy->base, 517 cfg->regs[QUSB2PHY_PORT_TUNE1], 518 PREEMPH_WIDTH_HALF_BIT); 519 } 520 521 if (or->hsdisc_trim.override) 522 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], 523 or->hsdisc_trim.value << HSDISC_TRIM_SHIFT, 524 HSDISC_TRIM_MASK); 525 } 526 527 /* 528 * Fetches HS Tx tuning value from nvmem and sets the 529 * QUSB2PHY_PORT_TUNE1/2 register. 530 * For error case, skip setting the value and use the default value. 531 */ 532 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) 533 { 534 struct device *dev = &qphy->phy->dev; 535 const struct qusb2_phy_cfg *cfg = qphy->cfg; 536 u8 *val; 537 538 /* efuse register is optional */ 539 if (!qphy->cell) 540 return; 541 542 /* 543 * Read efuse register having TUNE2/1 parameter's high nibble. 544 * If efuse register shows value as 0x0 (indicating value is not 545 * fused), or if we fail to find a valid efuse register setting, 546 * then use default value for high nibble that we have already 547 * set while configuring the phy. 548 */ 549 val = nvmem_cell_read(qphy->cell, NULL); 550 if (IS_ERR(val) || !val[0]) { 551 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); 552 return; 553 } 554 555 /* Fused TUNE1/2 value is the higher nibble only */ 556 if (cfg->update_tune1_with_efuse) 557 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 558 val[0] << HSTX_TRIM_SHIFT, 559 HSTX_TRIM_MASK); 560 else 561 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], 562 val[0] << HSTX_TRIM_SHIFT, 563 HSTX_TRIM_MASK); 564 } 565 566 static int qusb2_phy_set_mode(struct phy *phy, 567 enum phy_mode mode, int submode) 568 { 569 struct qusb2_phy *qphy = phy_get_drvdata(phy); 570 571 qphy->mode = mode; 572 573 return 0; 574 } 575 576 static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev) 577 { 578 struct qusb2_phy *qphy = dev_get_drvdata(dev); 579 const struct qusb2_phy_cfg *cfg = qphy->cfg; 580 u32 intr_mask; 581 582 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode); 583 584 if (!qphy->phy_initialized) { 585 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 586 return 0; 587 } 588 589 /* 590 * Enable DP/DM interrupts to detect line state changes based on current 591 * speed. In other words, enable the triggers _opposite_ of what the 592 * current D+/D- levels are e.g. if currently D+ high, D- low 593 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high 594 */ 595 intr_mask = DPSE_INTR_EN | DMSE_INTR_EN; 596 switch (qphy->mode) { 597 case PHY_MODE_USB_HOST_HS: 598 case PHY_MODE_USB_HOST_FS: 599 case PHY_MODE_USB_DEVICE_HS: 600 case PHY_MODE_USB_DEVICE_FS: 601 intr_mask |= DMSE_INTR_HIGH_SEL; 602 break; 603 case PHY_MODE_USB_HOST_LS: 604 case PHY_MODE_USB_DEVICE_LS: 605 intr_mask |= DPSE_INTR_HIGH_SEL; 606 break; 607 default: 608 /* No device connected, enable both DP/DM high interrupt */ 609 intr_mask |= DMSE_INTR_HIGH_SEL; 610 intr_mask |= DPSE_INTR_HIGH_SEL; 611 break; 612 } 613 614 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); 615 616 /* hold core PLL into reset */ 617 if (cfg->has_pll_override) { 618 qusb2_setbits(qphy->base, 619 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], 620 CORE_PLL_EN_FROM_RESET | CORE_RESET | 621 CORE_RESET_MUX); 622 } 623 624 /* enable phy auto-resume only if device is connected on bus */ 625 if (qphy->mode != PHY_MODE_INVALID) { 626 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], 627 cfg->autoresume_en); 628 /* Autoresume bit has to be toggled in order to enable it */ 629 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], 630 cfg->autoresume_en); 631 } 632 633 if (!qphy->has_se_clk_scheme) 634 clk_disable_unprepare(qphy->ref_clk); 635 636 clk_disable_unprepare(qphy->cfg_ahb_clk); 637 clk_disable_unprepare(qphy->iface_clk); 638 639 return 0; 640 } 641 642 static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev) 643 { 644 struct qusb2_phy *qphy = dev_get_drvdata(dev); 645 const struct qusb2_phy_cfg *cfg = qphy->cfg; 646 int ret; 647 648 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode); 649 650 if (!qphy->phy_initialized) { 651 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 652 return 0; 653 } 654 655 ret = clk_prepare_enable(qphy->iface_clk); 656 if (ret) { 657 dev_err(dev, "failed to enable iface_clk, %d\n", ret); 658 return ret; 659 } 660 661 ret = clk_prepare_enable(qphy->cfg_ahb_clk); 662 if (ret) { 663 dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret); 664 goto disable_iface_clk; 665 } 666 667 if (!qphy->has_se_clk_scheme) { 668 ret = clk_prepare_enable(qphy->ref_clk); 669 if (ret) { 670 dev_err(dev, "failed to enable ref clk, %d\n", ret); 671 goto disable_ahb_clk; 672 } 673 } 674 675 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); 676 677 /* bring core PLL out of reset */ 678 if (cfg->has_pll_override) { 679 qusb2_clrbits(qphy->base, 680 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], 681 CORE_RESET | CORE_RESET_MUX); 682 } 683 684 return 0; 685 686 disable_ahb_clk: 687 clk_disable_unprepare(qphy->cfg_ahb_clk); 688 disable_iface_clk: 689 clk_disable_unprepare(qphy->iface_clk); 690 691 return ret; 692 } 693 694 static int qusb2_phy_init(struct phy *phy) 695 { 696 struct qusb2_phy *qphy = phy_get_drvdata(phy); 697 const struct qusb2_phy_cfg *cfg = qphy->cfg; 698 unsigned int val = 0; 699 unsigned int clk_scheme; 700 int ret; 701 702 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__); 703 704 /* turn on regulator supplies */ 705 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 706 if (ret) 707 return ret; 708 709 ret = clk_prepare_enable(qphy->iface_clk); 710 if (ret) { 711 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret); 712 goto poweroff_phy; 713 } 714 715 /* enable ahb interface clock to program phy */ 716 ret = clk_prepare_enable(qphy->cfg_ahb_clk); 717 if (ret) { 718 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); 719 goto disable_iface_clk; 720 } 721 722 /* Perform phy reset */ 723 ret = reset_control_assert(qphy->phy_reset); 724 if (ret) { 725 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); 726 goto disable_ahb_clk; 727 } 728 729 /* 100 us delay to keep PHY in reset mode */ 730 usleep_range(100, 150); 731 732 ret = reset_control_deassert(qphy->phy_reset); 733 if (ret) { 734 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); 735 goto disable_ahb_clk; 736 } 737 738 /* Disable the PHY */ 739 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], 740 qphy->cfg->disable_ctrl); 741 742 if (cfg->has_pll_test) { 743 /* save reset value to override reference clock scheme later */ 744 val = readl(qphy->base + QUSB2PHY_PLL_TEST); 745 } 746 747 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, 748 cfg->tbl_num); 749 750 /* Override board specific PHY tuning values */ 751 qusb2_phy_override_phy_params(qphy); 752 753 /* Set efuse value for tuning the PHY */ 754 qusb2_phy_set_tune2_param(qphy); 755 756 /* Enable the PHY */ 757 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], 758 POWER_DOWN); 759 760 /* Required to get phy pll lock successfully */ 761 usleep_range(150, 160); 762 763 /* 764 * Not all the SoCs have got a readable TCSR_PHY_CLK_SCHEME 765 * register in the TCSR so, if there's none, use the default 766 * value hardcoded in the configuration. 767 */ 768 qphy->has_se_clk_scheme = cfg->se_clk_scheme_default; 769 770 /* 771 * read TCSR_PHY_CLK_SCHEME register to check if single-ended 772 * clock scheme is selected. If yes, then disable differential 773 * ref_clk and use single-ended clock, otherwise use differential 774 * ref_clk only. 775 */ 776 if (qphy->tcsr) { 777 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, 778 &clk_scheme); 779 if (ret) { 780 dev_err(&phy->dev, "failed to read clk scheme reg\n"); 781 goto assert_phy_reset; 782 } 783 784 /* is it a differential clock scheme ? */ 785 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) { 786 dev_vdbg(&phy->dev, "%s(): select differential clk\n", 787 __func__); 788 qphy->has_se_clk_scheme = false; 789 } else { 790 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n", 791 __func__); 792 } 793 } 794 795 if (!qphy->has_se_clk_scheme) { 796 ret = clk_prepare_enable(qphy->ref_clk); 797 if (ret) { 798 dev_err(&phy->dev, "failed to enable ref clk, %d\n", 799 ret); 800 goto assert_phy_reset; 801 } 802 } 803 804 if (cfg->has_pll_test) { 805 if (!qphy->has_se_clk_scheme) 806 val &= ~CLK_REF_SEL; 807 else 808 val |= CLK_REF_SEL; 809 810 writel(val, qphy->base + QUSB2PHY_PLL_TEST); 811 812 /* ensure above write is through */ 813 readl(qphy->base + QUSB2PHY_PLL_TEST); 814 } 815 816 /* Required to get phy pll lock successfully */ 817 usleep_range(100, 110); 818 819 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); 820 if (!(val & cfg->mask_core_ready)) { 821 dev_err(&phy->dev, 822 "QUSB2PHY pll lock failed: status reg = %x\n", val); 823 ret = -EBUSY; 824 goto disable_ref_clk; 825 } 826 qphy->phy_initialized = true; 827 828 return 0; 829 830 disable_ref_clk: 831 if (!qphy->has_se_clk_scheme) 832 clk_disable_unprepare(qphy->ref_clk); 833 assert_phy_reset: 834 reset_control_assert(qphy->phy_reset); 835 disable_ahb_clk: 836 clk_disable_unprepare(qphy->cfg_ahb_clk); 837 disable_iface_clk: 838 clk_disable_unprepare(qphy->iface_clk); 839 poweroff_phy: 840 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 841 842 return ret; 843 } 844 845 static int qusb2_phy_exit(struct phy *phy) 846 { 847 struct qusb2_phy *qphy = phy_get_drvdata(phy); 848 849 /* Disable the PHY */ 850 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], 851 qphy->cfg->disable_ctrl); 852 853 if (!qphy->has_se_clk_scheme) 854 clk_disable_unprepare(qphy->ref_clk); 855 856 reset_control_assert(qphy->phy_reset); 857 858 clk_disable_unprepare(qphy->cfg_ahb_clk); 859 clk_disable_unprepare(qphy->iface_clk); 860 861 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 862 863 qphy->phy_initialized = false; 864 865 return 0; 866 } 867 868 static const struct phy_ops qusb2_phy_gen_ops = { 869 .init = qusb2_phy_init, 870 .exit = qusb2_phy_exit, 871 .set_mode = qusb2_phy_set_mode, 872 .owner = THIS_MODULE, 873 }; 874 875 static const struct of_device_id qusb2_phy_of_match_table[] = { 876 { 877 .compatible = "qcom,ipq6018-qusb2-phy", 878 .data = &ipq6018_phy_cfg, 879 }, { 880 .compatible = "qcom,ipq8074-qusb2-phy", 881 .data = &msm8996_phy_cfg, 882 }, { 883 .compatible = "qcom,msm8996-qusb2-phy", 884 .data = &msm8996_phy_cfg, 885 }, { 886 .compatible = "qcom,msm8998-qusb2-phy", 887 .data = &msm8998_phy_cfg, 888 }, { 889 .compatible = "qcom,sdm660-qusb2-phy", 890 .data = &sdm660_phy_cfg, 891 }, { 892 /* 893 * Deprecated. Only here to support legacy device 894 * trees that didn't include "qcom,qusb2-v2-phy" 895 */ 896 .compatible = "qcom,sdm845-qusb2-phy", 897 .data = &qusb2_v2_phy_cfg, 898 }, { 899 .compatible = "qcom,qusb2-v2-phy", 900 .data = &qusb2_v2_phy_cfg, 901 }, 902 { }, 903 }; 904 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table); 905 906 static const struct dev_pm_ops qusb2_phy_pm_ops = { 907 SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend, 908 qusb2_phy_runtime_resume, NULL) 909 }; 910 911 static int qusb2_phy_probe(struct platform_device *pdev) 912 { 913 struct device *dev = &pdev->dev; 914 struct qusb2_phy *qphy; 915 struct phy_provider *phy_provider; 916 struct phy *generic_phy; 917 int ret, i; 918 int num; 919 u32 value; 920 struct override_params *or; 921 922 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 923 if (!qphy) 924 return -ENOMEM; 925 or = &qphy->overrides; 926 927 qphy->base = devm_platform_ioremap_resource(pdev, 0); 928 if (IS_ERR(qphy->base)) 929 return PTR_ERR(qphy->base); 930 931 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); 932 if (IS_ERR(qphy->cfg_ahb_clk)) { 933 ret = PTR_ERR(qphy->cfg_ahb_clk); 934 if (ret != -EPROBE_DEFER) 935 dev_err(dev, "failed to get cfg ahb clk, %d\n", ret); 936 return ret; 937 } 938 939 qphy->ref_clk = devm_clk_get(dev, "ref"); 940 if (IS_ERR(qphy->ref_clk)) { 941 ret = PTR_ERR(qphy->ref_clk); 942 if (ret != -EPROBE_DEFER) 943 dev_err(dev, "failed to get ref clk, %d\n", ret); 944 return ret; 945 } 946 947 qphy->iface_clk = devm_clk_get_optional(dev, "iface"); 948 if (IS_ERR(qphy->iface_clk)) 949 return PTR_ERR(qphy->iface_clk); 950 951 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0); 952 if (IS_ERR(qphy->phy_reset)) { 953 dev_err(dev, "failed to get phy core reset\n"); 954 return PTR_ERR(qphy->phy_reset); 955 } 956 957 num = ARRAY_SIZE(qphy->vregs); 958 for (i = 0; i < num; i++) 959 qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; 960 961 ret = devm_regulator_bulk_get(dev, num, qphy->vregs); 962 if (ret) { 963 if (ret != -EPROBE_DEFER) 964 dev_err(dev, "failed to get regulator supplies: %d\n", 965 ret); 966 return ret; 967 } 968 969 /* Get the specific init parameters of QMP phy */ 970 qphy->cfg = of_device_get_match_data(dev); 971 972 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, 973 "qcom,tcsr-syscon"); 974 if (IS_ERR(qphy->tcsr)) { 975 dev_dbg(dev, "failed to lookup TCSR regmap\n"); 976 qphy->tcsr = NULL; 977 } 978 979 qphy->cell = devm_nvmem_cell_get(dev, NULL); 980 if (IS_ERR(qphy->cell)) { 981 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER) 982 return -EPROBE_DEFER; 983 qphy->cell = NULL; 984 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n"); 985 } 986 987 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value", 988 &value)) { 989 or->imp_res_offset.value = (u8)value; 990 or->imp_res_offset.override = true; 991 } 992 993 if (!of_property_read_u32(dev->of_node, "qcom,bias-ctrl-value", 994 &value)) { 995 or->bias_ctrl.value = (u8)value; 996 or->bias_ctrl.override = true; 997 } 998 999 if (!of_property_read_u32(dev->of_node, "qcom,charge-ctrl-value", 1000 &value)) { 1001 or->charge_ctrl.value = (u8)value; 1002 or->charge_ctrl.override = true; 1003 } 1004 1005 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", 1006 &value)) { 1007 or->hstx_trim.value = (u8)value; 1008 or->hstx_trim.override = true; 1009 } 1010 1011 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level", 1012 &value)) { 1013 or->preemphasis.value = (u8)value; 1014 or->preemphasis.override = true; 1015 } 1016 1017 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width", 1018 &value)) { 1019 or->preemphasis_width.value = (u8)value; 1020 or->preemphasis_width.override = true; 1021 } 1022 1023 if (!of_property_read_u32(dev->of_node, "qcom,hsdisc-trim-value", 1024 &value)) { 1025 or->hsdisc_trim.value = (u8)value; 1026 or->hsdisc_trim.override = true; 1027 } 1028 1029 pm_runtime_set_active(dev); 1030 pm_runtime_enable(dev); 1031 /* 1032 * Prevent runtime pm from being ON by default. Users can enable 1033 * it using power/control in sysfs. 1034 */ 1035 pm_runtime_forbid(dev); 1036 1037 generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops); 1038 if (IS_ERR(generic_phy)) { 1039 ret = PTR_ERR(generic_phy); 1040 dev_err(dev, "failed to create phy, %d\n", ret); 1041 pm_runtime_disable(dev); 1042 return ret; 1043 } 1044 qphy->phy = generic_phy; 1045 1046 dev_set_drvdata(dev, qphy); 1047 phy_set_drvdata(generic_phy, qphy); 1048 1049 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 1050 if (!IS_ERR(phy_provider)) 1051 dev_info(dev, "Registered Qcom-QUSB2 phy\n"); 1052 else 1053 pm_runtime_disable(dev); 1054 1055 return PTR_ERR_OR_ZERO(phy_provider); 1056 } 1057 1058 static struct platform_driver qusb2_phy_driver = { 1059 .probe = qusb2_phy_probe, 1060 .driver = { 1061 .name = "qcom-qusb2-phy", 1062 .pm = &qusb2_phy_pm_ops, 1063 .of_match_table = qusb2_phy_of_match_table, 1064 }, 1065 }; 1066 1067 module_platform_driver(qusb2_phy_driver); 1068 1069 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 1070 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver"); 1071 MODULE_LICENSE("GPL v2"); 1072