1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/delay.h> 8 #include <linux/err.h> 9 #include <linux/io.h> 10 #include <linux/kernel.h> 11 #include <linux/mfd/syscon.h> 12 #include <linux/module.h> 13 #include <linux/nvmem-consumer.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/phy/phy.h> 17 #include <linux/platform_device.h> 18 #include <linux/regmap.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include <dt-bindings/phy/phy-qcom-qusb2.h> 24 25 #define QUSB2PHY_PLL_TEST 0x04 26 #define CLK_REF_SEL BIT(7) 27 28 #define QUSB2PHY_PLL_TUNE 0x08 29 #define QUSB2PHY_PLL_USER_CTL1 0x0c 30 #define QUSB2PHY_PLL_USER_CTL2 0x10 31 #define QUSB2PHY_PLL_AUTOPGM_CTL1 0x1c 32 #define QUSB2PHY_PLL_PWR_CTRL 0x18 33 34 /* QUSB2PHY_PLL_STATUS register bits */ 35 #define PLL_LOCKED BIT(5) 36 37 /* QUSB2PHY_PLL_COMMON_STATUS_ONE register bits */ 38 #define CORE_READY_STATUS BIT(0) 39 40 /* QUSB2PHY_PORT_POWERDOWN register bits */ 41 #define CLAMP_N_EN BIT(5) 42 #define FREEZIO_N BIT(1) 43 #define POWER_DOWN BIT(0) 44 45 /* QUSB2PHY_PWR_CTRL1 register bits */ 46 #define PWR_CTRL1_VREF_SUPPLY_TRIM BIT(5) 47 #define PWR_CTRL1_CLAMP_N_EN BIT(1) 48 49 #define QUSB2PHY_REFCLK_ENABLE BIT(0) 50 51 #define PHY_CLK_SCHEME_SEL BIT(0) 52 53 /* QUSB2PHY_INTR_CTRL register bits */ 54 #define DMSE_INTR_HIGH_SEL BIT(4) 55 #define DPSE_INTR_HIGH_SEL BIT(3) 56 #define CHG_DET_INTR_EN BIT(2) 57 #define DMSE_INTR_EN BIT(1) 58 #define DPSE_INTR_EN BIT(0) 59 60 /* QUSB2PHY_PLL_CORE_INPUT_OVERRIDE register bits */ 61 #define CORE_PLL_EN_FROM_RESET BIT(4) 62 #define CORE_RESET BIT(5) 63 #define CORE_RESET_MUX BIT(6) 64 65 /* QUSB2PHY_IMP_CTRL1 register bits */ 66 #define IMP_RES_OFFSET_MASK GENMASK(5, 0) 67 #define IMP_RES_OFFSET_SHIFT 0x0 68 69 /* QUSB2PHY_PORT_TUNE1 register bits */ 70 #define HSTX_TRIM_MASK GENMASK(7, 4) 71 #define HSTX_TRIM_SHIFT 0x4 72 #define PREEMPH_WIDTH_HALF_BIT BIT(2) 73 #define PREEMPHASIS_EN_MASK GENMASK(1, 0) 74 #define PREEMPHASIS_EN_SHIFT 0x0 75 76 #define QUSB2PHY_PLL_ANALOG_CONTROLS_TWO 0x04 77 #define QUSB2PHY_PLL_CLOCK_INVERTERS 0x18c 78 #define QUSB2PHY_PLL_CMODE 0x2c 79 #define QUSB2PHY_PLL_LOCK_DELAY 0x184 80 #define QUSB2PHY_PLL_DIGITAL_TIMERS_TWO 0xb4 81 #define QUSB2PHY_PLL_BIAS_CONTROL_1 0x194 82 #define QUSB2PHY_PLL_BIAS_CONTROL_2 0x198 83 #define QUSB2PHY_PWR_CTRL2 0x214 84 #define QUSB2PHY_IMP_CTRL1 0x220 85 #define QUSB2PHY_IMP_CTRL2 0x224 86 #define QUSB2PHY_CHG_CTRL2 0x23c 87 88 struct qusb2_phy_init_tbl { 89 unsigned int offset; 90 unsigned int val; 91 /* 92 * register part of layout ? 93 * if yes, then offset gives index in the reg-layout 94 */ 95 int in_layout; 96 }; 97 98 #define QUSB2_PHY_INIT_CFG(o, v) \ 99 { \ 100 .offset = o, \ 101 .val = v, \ 102 } 103 104 #define QUSB2_PHY_INIT_CFG_L(o, v) \ 105 { \ 106 .offset = o, \ 107 .val = v, \ 108 .in_layout = 1, \ 109 } 110 111 /* set of registers with offsets different per-PHY */ 112 enum qusb2phy_reg_layout { 113 QUSB2PHY_PLL_CORE_INPUT_OVERRIDE, 114 QUSB2PHY_PLL_STATUS, 115 QUSB2PHY_PORT_TUNE1, 116 QUSB2PHY_PORT_TUNE2, 117 QUSB2PHY_PORT_TUNE3, 118 QUSB2PHY_PORT_TUNE4, 119 QUSB2PHY_PORT_TUNE5, 120 QUSB2PHY_PORT_TEST1, 121 QUSB2PHY_PORT_TEST2, 122 QUSB2PHY_PORT_POWERDOWN, 123 QUSB2PHY_INTR_CTRL, 124 }; 125 126 static const unsigned int msm8996_regs_layout[] = { 127 [QUSB2PHY_PLL_STATUS] = 0x38, 128 [QUSB2PHY_PORT_TUNE1] = 0x80, 129 [QUSB2PHY_PORT_TUNE2] = 0x84, 130 [QUSB2PHY_PORT_TUNE3] = 0x88, 131 [QUSB2PHY_PORT_TUNE4] = 0x8c, 132 [QUSB2PHY_PORT_TUNE5] = 0x90, 133 [QUSB2PHY_PORT_TEST1] = 0xb8, 134 [QUSB2PHY_PORT_TEST2] = 0x9c, 135 [QUSB2PHY_PORT_POWERDOWN] = 0xb4, 136 [QUSB2PHY_INTR_CTRL] = 0xbc, 137 }; 138 139 static const struct qusb2_phy_init_tbl msm8996_init_tbl[] = { 140 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0xf8), 141 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0xb3), 142 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0x83), 143 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0xc0), 144 145 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_TUNE, 0x30), 146 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL1, 0x79), 147 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_USER_CTL2, 0x21), 148 149 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TEST2, 0x14), 150 151 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_AUTOPGM_CTL1, 0x9f), 152 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_PWR_CTRL, 0x00), 153 }; 154 155 static const unsigned int sdm845_regs_layout[] = { 156 [QUSB2PHY_PLL_CORE_INPUT_OVERRIDE] = 0xa8, 157 [QUSB2PHY_PLL_STATUS] = 0x1a0, 158 [QUSB2PHY_PORT_TUNE1] = 0x240, 159 [QUSB2PHY_PORT_TUNE2] = 0x244, 160 [QUSB2PHY_PORT_TUNE3] = 0x248, 161 [QUSB2PHY_PORT_TUNE4] = 0x24c, 162 [QUSB2PHY_PORT_TUNE5] = 0x250, 163 [QUSB2PHY_PORT_TEST1] = 0x254, 164 [QUSB2PHY_PORT_TEST2] = 0x258, 165 [QUSB2PHY_PORT_POWERDOWN] = 0x210, 166 [QUSB2PHY_INTR_CTRL] = 0x230, 167 }; 168 169 static const struct qusb2_phy_init_tbl sdm845_init_tbl[] = { 170 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_ANALOG_CONTROLS_TWO, 0x03), 171 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CLOCK_INVERTERS, 0x7c), 172 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_CMODE, 0x80), 173 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_LOCK_DELAY, 0x0a), 174 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_DIGITAL_TIMERS_TWO, 0x19), 175 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_1, 0x40), 176 QUSB2_PHY_INIT_CFG(QUSB2PHY_PLL_BIAS_CONTROL_2, 0x20), 177 QUSB2_PHY_INIT_CFG(QUSB2PHY_PWR_CTRL2, 0x21), 178 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL1, 0x0), 179 QUSB2_PHY_INIT_CFG(QUSB2PHY_IMP_CTRL2, 0x58), 180 181 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE1, 0x30), 182 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE2, 0x29), 183 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE3, 0xca), 184 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE4, 0x04), 185 QUSB2_PHY_INIT_CFG_L(QUSB2PHY_PORT_TUNE5, 0x03), 186 187 QUSB2_PHY_INIT_CFG(QUSB2PHY_CHG_CTRL2, 0x0), 188 }; 189 190 struct qusb2_phy_cfg { 191 const struct qusb2_phy_init_tbl *tbl; 192 /* number of entries in the table */ 193 unsigned int tbl_num; 194 /* offset to PHY_CLK_SCHEME register in TCSR map */ 195 unsigned int clk_scheme_offset; 196 197 /* array of registers with different offsets */ 198 const unsigned int *regs; 199 unsigned int mask_core_ready; 200 unsigned int disable_ctrl; 201 unsigned int autoresume_en; 202 203 /* true if PHY has PLL_TEST register to select clk_scheme */ 204 bool has_pll_test; 205 206 /* true if TUNE1 register must be updated by fused value, else TUNE2 */ 207 bool update_tune1_with_efuse; 208 209 /* true if PHY has PLL_CORE_INPUT_OVERRIDE register to reset PLL */ 210 bool has_pll_override; 211 }; 212 213 static const struct qusb2_phy_cfg msm8996_phy_cfg = { 214 .tbl = msm8996_init_tbl, 215 .tbl_num = ARRAY_SIZE(msm8996_init_tbl), 216 .regs = msm8996_regs_layout, 217 218 .has_pll_test = true, 219 .disable_ctrl = (CLAMP_N_EN | FREEZIO_N | POWER_DOWN), 220 .mask_core_ready = PLL_LOCKED, 221 .autoresume_en = BIT(3), 222 }; 223 224 static const struct qusb2_phy_cfg sdm845_phy_cfg = { 225 .tbl = sdm845_init_tbl, 226 .tbl_num = ARRAY_SIZE(sdm845_init_tbl), 227 .regs = sdm845_regs_layout, 228 229 .disable_ctrl = (PWR_CTRL1_VREF_SUPPLY_TRIM | PWR_CTRL1_CLAMP_N_EN | 230 POWER_DOWN), 231 .mask_core_ready = CORE_READY_STATUS, 232 .has_pll_override = true, 233 .autoresume_en = BIT(0), 234 .update_tune1_with_efuse = true, 235 }; 236 237 static const char * const qusb2_phy_vreg_names[] = { 238 "vdda-pll", "vdda-phy-dpdm", 239 }; 240 241 #define QUSB2_NUM_VREGS ARRAY_SIZE(qusb2_phy_vreg_names) 242 243 /** 244 * struct qusb2_phy - structure holding qusb2 phy attributes 245 * 246 * @phy: generic phy 247 * @base: iomapped memory space for qubs2 phy 248 * 249 * @cfg_ahb_clk: AHB2PHY interface clock 250 * @ref_clk: phy reference clock 251 * @iface_clk: phy interface clock 252 * @phy_reset: phy reset control 253 * @vregs: regulator supplies bulk data 254 * 255 * @tcsr: TCSR syscon register map 256 * @cell: nvmem cell containing phy tuning value 257 * 258 * @override_imp_res_offset: PHY should use different rescode offset 259 * @imp_res_offset_value: rescode offset to be updated in IMP_CTRL1 register 260 * @override_hstx_trim: PHY should use different HSTX o/p current value 261 * @hstx_trim_value: HSTX_TRIM value to be updated in TUNE1 register 262 * @override_preemphasis: PHY should use different pre-amphasis amplitude 263 * @preemphasis_level: Amplitude Pre-Emphasis to be updated in TUNE1 register 264 * @override_preemphasis_width: PHY should use different pre-emphasis duration 265 * @preemphasis_width: half/full-width Pre-Emphasis updated via TUNE1 266 * 267 * @cfg: phy config data 268 * @has_se_clk_scheme: indicate if PHY has single-ended ref clock scheme 269 * @phy_initialized: indicate if PHY has been initialized 270 * @mode: current PHY mode 271 */ 272 struct qusb2_phy { 273 struct phy *phy; 274 void __iomem *base; 275 276 struct clk *cfg_ahb_clk; 277 struct clk *ref_clk; 278 struct clk *iface_clk; 279 struct reset_control *phy_reset; 280 struct regulator_bulk_data vregs[QUSB2_NUM_VREGS]; 281 282 struct regmap *tcsr; 283 struct nvmem_cell *cell; 284 285 bool override_imp_res_offset; 286 u8 imp_res_offset_value; 287 bool override_hstx_trim; 288 u8 hstx_trim_value; 289 bool override_preemphasis; 290 u8 preemphasis_level; 291 bool override_preemphasis_width; 292 u8 preemphasis_width; 293 294 const struct qusb2_phy_cfg *cfg; 295 bool has_se_clk_scheme; 296 bool phy_initialized; 297 enum phy_mode mode; 298 }; 299 300 static inline void qusb2_write_mask(void __iomem *base, u32 offset, 301 u32 val, u32 mask) 302 { 303 u32 reg; 304 305 reg = readl(base + offset); 306 reg &= ~mask; 307 reg |= val & mask; 308 writel(reg, base + offset); 309 310 /* Ensure above write is completed */ 311 readl(base + offset); 312 } 313 314 static inline void qusb2_setbits(void __iomem *base, u32 offset, u32 val) 315 { 316 u32 reg; 317 318 reg = readl(base + offset); 319 reg |= val; 320 writel(reg, base + offset); 321 322 /* Ensure above write is completed */ 323 readl(base + offset); 324 } 325 326 static inline void qusb2_clrbits(void __iomem *base, u32 offset, u32 val) 327 { 328 u32 reg; 329 330 reg = readl(base + offset); 331 reg &= ~val; 332 writel(reg, base + offset); 333 334 /* Ensure above write is completed */ 335 readl(base + offset); 336 } 337 338 static inline 339 void qcom_qusb2_phy_configure(void __iomem *base, 340 const unsigned int *regs, 341 const struct qusb2_phy_init_tbl tbl[], int num) 342 { 343 int i; 344 345 for (i = 0; i < num; i++) { 346 if (tbl[i].in_layout) 347 writel(tbl[i].val, base + regs[tbl[i].offset]); 348 else 349 writel(tbl[i].val, base + tbl[i].offset); 350 } 351 } 352 353 /* 354 * Update board specific PHY tuning override values if specified from 355 * device tree. 356 */ 357 static void qusb2_phy_override_phy_params(struct qusb2_phy *qphy) 358 { 359 const struct qusb2_phy_cfg *cfg = qphy->cfg; 360 361 if (qphy->override_imp_res_offset) 362 qusb2_write_mask(qphy->base, QUSB2PHY_IMP_CTRL1, 363 qphy->imp_res_offset_value << IMP_RES_OFFSET_SHIFT, 364 IMP_RES_OFFSET_MASK); 365 366 if (qphy->override_hstx_trim) 367 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 368 qphy->hstx_trim_value << HSTX_TRIM_SHIFT, 369 HSTX_TRIM_MASK); 370 371 if (qphy->override_preemphasis) 372 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 373 qphy->preemphasis_level << PREEMPHASIS_EN_SHIFT, 374 PREEMPHASIS_EN_MASK); 375 376 if (qphy->override_preemphasis_width) { 377 if (qphy->preemphasis_width == 378 QUSB2_V2_PREEMPHASIS_WIDTH_HALF_BIT) 379 qusb2_setbits(qphy->base, 380 cfg->regs[QUSB2PHY_PORT_TUNE1], 381 PREEMPH_WIDTH_HALF_BIT); 382 else 383 qusb2_clrbits(qphy->base, 384 cfg->regs[QUSB2PHY_PORT_TUNE1], 385 PREEMPH_WIDTH_HALF_BIT); 386 } 387 } 388 389 /* 390 * Fetches HS Tx tuning value from nvmem and sets the 391 * QUSB2PHY_PORT_TUNE1/2 register. 392 * For error case, skip setting the value and use the default value. 393 */ 394 static void qusb2_phy_set_tune2_param(struct qusb2_phy *qphy) 395 { 396 struct device *dev = &qphy->phy->dev; 397 const struct qusb2_phy_cfg *cfg = qphy->cfg; 398 u8 *val; 399 400 /* efuse register is optional */ 401 if (!qphy->cell) 402 return; 403 404 /* 405 * Read efuse register having TUNE2/1 parameter's high nibble. 406 * If efuse register shows value as 0x0 (indicating value is not 407 * fused), or if we fail to find a valid efuse register setting, 408 * then use default value for high nibble that we have already 409 * set while configuring the phy. 410 */ 411 val = nvmem_cell_read(qphy->cell, NULL); 412 if (IS_ERR(val) || !val[0]) { 413 dev_dbg(dev, "failed to read a valid hs-tx trim value\n"); 414 return; 415 } 416 417 /* Fused TUNE1/2 value is the higher nibble only */ 418 if (cfg->update_tune1_with_efuse) 419 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE1], 420 val[0] << HSTX_TRIM_SHIFT, 421 HSTX_TRIM_MASK); 422 else 423 qusb2_write_mask(qphy->base, cfg->regs[QUSB2PHY_PORT_TUNE2], 424 val[0] << HSTX_TRIM_SHIFT, 425 HSTX_TRIM_MASK); 426 } 427 428 static int qusb2_phy_set_mode(struct phy *phy, 429 enum phy_mode mode, int submode) 430 { 431 struct qusb2_phy *qphy = phy_get_drvdata(phy); 432 433 qphy->mode = mode; 434 435 return 0; 436 } 437 438 static int __maybe_unused qusb2_phy_runtime_suspend(struct device *dev) 439 { 440 struct qusb2_phy *qphy = dev_get_drvdata(dev); 441 const struct qusb2_phy_cfg *cfg = qphy->cfg; 442 u32 intr_mask; 443 444 dev_vdbg(dev, "Suspending QUSB2 Phy, mode:%d\n", qphy->mode); 445 446 if (!qphy->phy_initialized) { 447 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 448 return 0; 449 } 450 451 /* 452 * Enable DP/DM interrupts to detect line state changes based on current 453 * speed. In other words, enable the triggers _opposite_ of what the 454 * current D+/D- levels are e.g. if currently D+ high, D- low 455 * (HS 'J'/Suspend), configure the mask to trigger on D+ low OR D- high 456 */ 457 intr_mask = DPSE_INTR_EN | DMSE_INTR_EN; 458 switch (qphy->mode) { 459 case PHY_MODE_USB_HOST_HS: 460 case PHY_MODE_USB_HOST_FS: 461 case PHY_MODE_USB_DEVICE_HS: 462 case PHY_MODE_USB_DEVICE_FS: 463 intr_mask |= DMSE_INTR_HIGH_SEL; 464 break; 465 case PHY_MODE_USB_HOST_LS: 466 case PHY_MODE_USB_DEVICE_LS: 467 intr_mask |= DPSE_INTR_HIGH_SEL; 468 break; 469 default: 470 /* No device connected, enable both DP/DM high interrupt */ 471 intr_mask |= DMSE_INTR_HIGH_SEL; 472 intr_mask |= DPSE_INTR_HIGH_SEL; 473 break; 474 } 475 476 writel(intr_mask, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); 477 478 /* hold core PLL into reset */ 479 if (cfg->has_pll_override) { 480 qusb2_setbits(qphy->base, 481 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], 482 CORE_PLL_EN_FROM_RESET | CORE_RESET | 483 CORE_RESET_MUX); 484 } 485 486 /* enable phy auto-resume only if device is connected on bus */ 487 if (qphy->mode != PHY_MODE_INVALID) { 488 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], 489 cfg->autoresume_en); 490 /* Autoresume bit has to be toggled in order to enable it */ 491 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_TEST1], 492 cfg->autoresume_en); 493 } 494 495 if (!qphy->has_se_clk_scheme) 496 clk_disable_unprepare(qphy->ref_clk); 497 498 clk_disable_unprepare(qphy->cfg_ahb_clk); 499 clk_disable_unprepare(qphy->iface_clk); 500 501 return 0; 502 } 503 504 static int __maybe_unused qusb2_phy_runtime_resume(struct device *dev) 505 { 506 struct qusb2_phy *qphy = dev_get_drvdata(dev); 507 const struct qusb2_phy_cfg *cfg = qphy->cfg; 508 int ret; 509 510 dev_vdbg(dev, "Resuming QUSB2 phy, mode:%d\n", qphy->mode); 511 512 if (!qphy->phy_initialized) { 513 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 514 return 0; 515 } 516 517 ret = clk_prepare_enable(qphy->iface_clk); 518 if (ret) { 519 dev_err(dev, "failed to enable iface_clk, %d\n", ret); 520 return ret; 521 } 522 523 ret = clk_prepare_enable(qphy->cfg_ahb_clk); 524 if (ret) { 525 dev_err(dev, "failed to enable cfg ahb clock, %d\n", ret); 526 goto disable_iface_clk; 527 } 528 529 if (!qphy->has_se_clk_scheme) { 530 clk_prepare_enable(qphy->ref_clk); 531 if (ret) { 532 dev_err(dev, "failed to enable ref clk, %d\n", ret); 533 goto disable_ahb_clk; 534 } 535 } 536 537 writel(0x0, qphy->base + cfg->regs[QUSB2PHY_INTR_CTRL]); 538 539 /* bring core PLL out of reset */ 540 if (cfg->has_pll_override) { 541 qusb2_clrbits(qphy->base, 542 cfg->regs[QUSB2PHY_PLL_CORE_INPUT_OVERRIDE], 543 CORE_RESET | CORE_RESET_MUX); 544 } 545 546 return 0; 547 548 disable_ahb_clk: 549 clk_disable_unprepare(qphy->cfg_ahb_clk); 550 disable_iface_clk: 551 clk_disable_unprepare(qphy->iface_clk); 552 553 return ret; 554 } 555 556 static int qusb2_phy_init(struct phy *phy) 557 { 558 struct qusb2_phy *qphy = phy_get_drvdata(phy); 559 const struct qusb2_phy_cfg *cfg = qphy->cfg; 560 unsigned int val = 0; 561 unsigned int clk_scheme; 562 int ret; 563 564 dev_vdbg(&phy->dev, "%s(): Initializing QUSB2 phy\n", __func__); 565 566 /* turn on regulator supplies */ 567 ret = regulator_bulk_enable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 568 if (ret) 569 return ret; 570 571 ret = clk_prepare_enable(qphy->iface_clk); 572 if (ret) { 573 dev_err(&phy->dev, "failed to enable iface_clk, %d\n", ret); 574 goto poweroff_phy; 575 } 576 577 /* enable ahb interface clock to program phy */ 578 ret = clk_prepare_enable(qphy->cfg_ahb_clk); 579 if (ret) { 580 dev_err(&phy->dev, "failed to enable cfg ahb clock, %d\n", ret); 581 goto disable_iface_clk; 582 } 583 584 /* Perform phy reset */ 585 ret = reset_control_assert(qphy->phy_reset); 586 if (ret) { 587 dev_err(&phy->dev, "failed to assert phy_reset, %d\n", ret); 588 goto disable_ahb_clk; 589 } 590 591 /* 100 us delay to keep PHY in reset mode */ 592 usleep_range(100, 150); 593 594 ret = reset_control_deassert(qphy->phy_reset); 595 if (ret) { 596 dev_err(&phy->dev, "failed to de-assert phy_reset, %d\n", ret); 597 goto disable_ahb_clk; 598 } 599 600 /* Disable the PHY */ 601 qusb2_setbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], 602 qphy->cfg->disable_ctrl); 603 604 if (cfg->has_pll_test) { 605 /* save reset value to override reference clock scheme later */ 606 val = readl(qphy->base + QUSB2PHY_PLL_TEST); 607 } 608 609 qcom_qusb2_phy_configure(qphy->base, cfg->regs, cfg->tbl, 610 cfg->tbl_num); 611 612 /* Override board specific PHY tuning values */ 613 qusb2_phy_override_phy_params(qphy); 614 615 /* Set efuse value for tuning the PHY */ 616 qusb2_phy_set_tune2_param(qphy); 617 618 /* Enable the PHY */ 619 qusb2_clrbits(qphy->base, cfg->regs[QUSB2PHY_PORT_POWERDOWN], 620 POWER_DOWN); 621 622 /* Required to get phy pll lock successfully */ 623 usleep_range(150, 160); 624 625 /* Default is single-ended clock on msm8996 */ 626 qphy->has_se_clk_scheme = true; 627 /* 628 * read TCSR_PHY_CLK_SCHEME register to check if single-ended 629 * clock scheme is selected. If yes, then disable differential 630 * ref_clk and use single-ended clock, otherwise use differential 631 * ref_clk only. 632 */ 633 if (qphy->tcsr) { 634 ret = regmap_read(qphy->tcsr, qphy->cfg->clk_scheme_offset, 635 &clk_scheme); 636 if (ret) { 637 dev_err(&phy->dev, "failed to read clk scheme reg\n"); 638 goto assert_phy_reset; 639 } 640 641 /* is it a differential clock scheme ? */ 642 if (!(clk_scheme & PHY_CLK_SCHEME_SEL)) { 643 dev_vdbg(&phy->dev, "%s(): select differential clk\n", 644 __func__); 645 qphy->has_se_clk_scheme = false; 646 } else { 647 dev_vdbg(&phy->dev, "%s(): select single-ended clk\n", 648 __func__); 649 } 650 } 651 652 if (!qphy->has_se_clk_scheme) { 653 ret = clk_prepare_enable(qphy->ref_clk); 654 if (ret) { 655 dev_err(&phy->dev, "failed to enable ref clk, %d\n", 656 ret); 657 goto assert_phy_reset; 658 } 659 } 660 661 if (cfg->has_pll_test) { 662 if (!qphy->has_se_clk_scheme) 663 val &= ~CLK_REF_SEL; 664 else 665 val |= CLK_REF_SEL; 666 667 writel(val, qphy->base + QUSB2PHY_PLL_TEST); 668 669 /* ensure above write is through */ 670 readl(qphy->base + QUSB2PHY_PLL_TEST); 671 } 672 673 /* Required to get phy pll lock successfully */ 674 usleep_range(100, 110); 675 676 val = readb(qphy->base + cfg->regs[QUSB2PHY_PLL_STATUS]); 677 if (!(val & cfg->mask_core_ready)) { 678 dev_err(&phy->dev, 679 "QUSB2PHY pll lock failed: status reg = %x\n", val); 680 ret = -EBUSY; 681 goto disable_ref_clk; 682 } 683 qphy->phy_initialized = true; 684 685 return 0; 686 687 disable_ref_clk: 688 if (!qphy->has_se_clk_scheme) 689 clk_disable_unprepare(qphy->ref_clk); 690 assert_phy_reset: 691 reset_control_assert(qphy->phy_reset); 692 disable_ahb_clk: 693 clk_disable_unprepare(qphy->cfg_ahb_clk); 694 disable_iface_clk: 695 clk_disable_unprepare(qphy->iface_clk); 696 poweroff_phy: 697 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 698 699 return ret; 700 } 701 702 static int qusb2_phy_exit(struct phy *phy) 703 { 704 struct qusb2_phy *qphy = phy_get_drvdata(phy); 705 706 /* Disable the PHY */ 707 qusb2_setbits(qphy->base, qphy->cfg->regs[QUSB2PHY_PORT_POWERDOWN], 708 qphy->cfg->disable_ctrl); 709 710 if (!qphy->has_se_clk_scheme) 711 clk_disable_unprepare(qphy->ref_clk); 712 713 reset_control_assert(qphy->phy_reset); 714 715 clk_disable_unprepare(qphy->cfg_ahb_clk); 716 clk_disable_unprepare(qphy->iface_clk); 717 718 regulator_bulk_disable(ARRAY_SIZE(qphy->vregs), qphy->vregs); 719 720 qphy->phy_initialized = false; 721 722 return 0; 723 } 724 725 static const struct phy_ops qusb2_phy_gen_ops = { 726 .init = qusb2_phy_init, 727 .exit = qusb2_phy_exit, 728 .set_mode = qusb2_phy_set_mode, 729 .owner = THIS_MODULE, 730 }; 731 732 static const struct of_device_id qusb2_phy_of_match_table[] = { 733 { 734 .compatible = "qcom,msm8996-qusb2-phy", 735 .data = &msm8996_phy_cfg, 736 }, { 737 .compatible = "qcom,sdm845-qusb2-phy", 738 .data = &sdm845_phy_cfg, 739 }, 740 { }, 741 }; 742 MODULE_DEVICE_TABLE(of, qusb2_phy_of_match_table); 743 744 static const struct dev_pm_ops qusb2_phy_pm_ops = { 745 SET_RUNTIME_PM_OPS(qusb2_phy_runtime_suspend, 746 qusb2_phy_runtime_resume, NULL) 747 }; 748 749 static int qusb2_phy_probe(struct platform_device *pdev) 750 { 751 struct device *dev = &pdev->dev; 752 struct qusb2_phy *qphy; 753 struct phy_provider *phy_provider; 754 struct phy *generic_phy; 755 struct resource *res; 756 int ret, i; 757 int num; 758 u32 value; 759 760 qphy = devm_kzalloc(dev, sizeof(*qphy), GFP_KERNEL); 761 if (!qphy) 762 return -ENOMEM; 763 764 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 765 qphy->base = devm_ioremap_resource(dev, res); 766 if (IS_ERR(qphy->base)) 767 return PTR_ERR(qphy->base); 768 769 qphy->cfg_ahb_clk = devm_clk_get(dev, "cfg_ahb"); 770 if (IS_ERR(qphy->cfg_ahb_clk)) { 771 ret = PTR_ERR(qphy->cfg_ahb_clk); 772 if (ret != -EPROBE_DEFER) 773 dev_err(dev, "failed to get cfg ahb clk, %d\n", ret); 774 return ret; 775 } 776 777 qphy->ref_clk = devm_clk_get(dev, "ref"); 778 if (IS_ERR(qphy->ref_clk)) { 779 ret = PTR_ERR(qphy->ref_clk); 780 if (ret != -EPROBE_DEFER) 781 dev_err(dev, "failed to get ref clk, %d\n", ret); 782 return ret; 783 } 784 785 qphy->iface_clk = devm_clk_get(dev, "iface"); 786 if (IS_ERR(qphy->iface_clk)) { 787 ret = PTR_ERR(qphy->iface_clk); 788 if (ret == -EPROBE_DEFER) 789 return ret; 790 qphy->iface_clk = NULL; 791 dev_dbg(dev, "failed to get iface clk, %d\n", ret); 792 } 793 794 qphy->phy_reset = devm_reset_control_get_by_index(&pdev->dev, 0); 795 if (IS_ERR(qphy->phy_reset)) { 796 dev_err(dev, "failed to get phy core reset\n"); 797 return PTR_ERR(qphy->phy_reset); 798 } 799 800 num = ARRAY_SIZE(qphy->vregs); 801 for (i = 0; i < num; i++) 802 qphy->vregs[i].supply = qusb2_phy_vreg_names[i]; 803 804 ret = devm_regulator_bulk_get(dev, num, qphy->vregs); 805 if (ret) { 806 if (ret != -EPROBE_DEFER) 807 dev_err(dev, "failed to get regulator supplies: %d\n", 808 ret); 809 return ret; 810 } 811 812 /* Get the specific init parameters of QMP phy */ 813 qphy->cfg = of_device_get_match_data(dev); 814 815 qphy->tcsr = syscon_regmap_lookup_by_phandle(dev->of_node, 816 "qcom,tcsr-syscon"); 817 if (IS_ERR(qphy->tcsr)) { 818 dev_dbg(dev, "failed to lookup TCSR regmap\n"); 819 qphy->tcsr = NULL; 820 } 821 822 qphy->cell = devm_nvmem_cell_get(dev, NULL); 823 if (IS_ERR(qphy->cell)) { 824 if (PTR_ERR(qphy->cell) == -EPROBE_DEFER) 825 return -EPROBE_DEFER; 826 qphy->cell = NULL; 827 dev_dbg(dev, "failed to lookup tune2 hstx trim value\n"); 828 } 829 830 if (!of_property_read_u32(dev->of_node, "qcom,imp-res-offset-value", 831 &value)) { 832 qphy->imp_res_offset_value = (u8)value; 833 qphy->override_imp_res_offset = true; 834 } 835 836 if (!of_property_read_u32(dev->of_node, "qcom,hstx-trim-value", 837 &value)) { 838 qphy->hstx_trim_value = (u8)value; 839 qphy->override_hstx_trim = true; 840 } 841 842 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-level", 843 &value)) { 844 qphy->preemphasis_level = (u8)value; 845 qphy->override_preemphasis = true; 846 } 847 848 if (!of_property_read_u32(dev->of_node, "qcom,preemphasis-width", 849 &value)) { 850 qphy->preemphasis_width = (u8)value; 851 qphy->override_preemphasis_width = true; 852 } 853 854 pm_runtime_set_active(dev); 855 pm_runtime_enable(dev); 856 /* 857 * Prevent runtime pm from being ON by default. Users can enable 858 * it using power/control in sysfs. 859 */ 860 pm_runtime_forbid(dev); 861 862 generic_phy = devm_phy_create(dev, NULL, &qusb2_phy_gen_ops); 863 if (IS_ERR(generic_phy)) { 864 ret = PTR_ERR(generic_phy); 865 dev_err(dev, "failed to create phy, %d\n", ret); 866 pm_runtime_disable(dev); 867 return ret; 868 } 869 qphy->phy = generic_phy; 870 871 dev_set_drvdata(dev, qphy); 872 phy_set_drvdata(generic_phy, qphy); 873 874 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 875 if (!IS_ERR(phy_provider)) 876 dev_info(dev, "Registered Qcom-QUSB2 phy\n"); 877 else 878 pm_runtime_disable(dev); 879 880 return PTR_ERR_OR_ZERO(phy_provider); 881 } 882 883 static struct platform_driver qusb2_phy_driver = { 884 .probe = qusb2_phy_probe, 885 .driver = { 886 .name = "qcom-qusb2-phy", 887 .pm = &qusb2_phy_pm_ops, 888 .of_match_table = qusb2_phy_of_match_table, 889 }, 890 }; 891 892 module_platform_driver(qusb2_phy_driver); 893 894 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 895 MODULE_DESCRIPTION("Qualcomm QUSB2 PHY driver"); 896 MODULE_LICENSE("GPL v2"); 897