1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef QCOM_PHY_QMP_H_ 7 #define QCOM_PHY_QMP_H_ 8 9 /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ 10 11 #define QSERDES_PLL_BG_TIMER 0x00c 12 #define QSERDES_PLL_SSC_PER1 0x01c 13 #define QSERDES_PLL_SSC_PER2 0x020 14 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 15 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 16 #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 17 #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 18 #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 19 #define QSERDES_PLL_CLK_ENABLE1 0x040 20 #define QSERDES_PLL_SYS_CLK_CTRL 0x044 21 #define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 22 #define QSERDES_PLL_PLL_IVCO 0x050 23 #define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 24 #define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 25 #define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 26 #define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 27 #define QSERDES_PLL_BG_TRIM 0x074 28 #define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 29 #define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c 30 #define QSERDES_PLL_CP_CTRL_MODE0 0x080 31 #define QSERDES_PLL_CP_CTRL_MODE1 0x084 32 #define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 33 #define QSERDES_PLL_PLL_RCTRL_MODE1 0x08C 34 #define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 35 #define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 36 #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 37 #define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 38 #define QSERDES_PLL_RESETSM_CNTRL 0x0b0 39 #define QSERDES_PLL_LOCK_CMP_EN 0x0c4 40 #define QSERDES_PLL_DEC_START_MODE0 0x0cc 41 #define QSERDES_PLL_DEC_START_MODE1 0x0d0 42 #define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 43 #define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc 44 #define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 45 #define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 46 #define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 47 #define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0eC 48 #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 49 #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 50 #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 51 #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c 52 #define QSERDES_PLL_VCO_TUNE_MAP 0x120 53 #define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 54 #define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 55 #define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c 56 #define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 57 #define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c 58 #define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 59 #define QSERDES_PLL_CLK_SELECT 0x16c 60 #define QSERDES_PLL_HSCLK_SEL 0x170 61 #define QSERDES_PLL_CORECLK_DIV 0x17c 62 #define QSERDES_PLL_CORE_CLK_EN 0x184 63 #define QSERDES_PLL_CMN_CONFIG 0x18c 64 #define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 65 #define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 66 67 /* QMP V2 PHY for PCIE gen3 ports - QSERDES TX registers */ 68 69 #define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX 0x03c 70 #define QSERDES_TX0_HIGHZ_DRVR_EN 0x058 71 #define QSERDES_TX0_LANE_MODE_1 0x084 72 #define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c 73 74 /* QMP V2 PHY for PCIE gen3 ports - QSERDES RX registers */ 75 76 #define QSERDES_RX0_UCDR_FO_GAIN 0x008 77 #define QSERDES_RX0_UCDR_SO_GAIN 0x014 78 #define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE 0x034 79 #define QSERDES_RX0_UCDR_PI_CONTROLS 0x044 80 #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 0x0ec 81 #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 0x0f0 82 #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 0x0f4 83 #define QSERDES_RX0_RX_IDAC_TSETTLE_LOW 0x0f8 84 #define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH 0x0fc 85 #define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 86 #define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 0x114 87 #define QSERDES_RX0_SIGDET_ENABLES 0x118 88 #define QSERDES_RX0_SIGDET_CNTRL 0x11c 89 #define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL 0x124 90 #define QSERDES_RX0_RX_MODE_00_LOW 0x170 91 #define QSERDES_RX0_RX_MODE_00_HIGH 0x174 92 #define QSERDES_RX0_RX_MODE_00_HIGH2 0x178 93 #define QSERDES_RX0_RX_MODE_00_HIGH3 0x17c 94 #define QSERDES_RX0_RX_MODE_00_HIGH4 0x180 95 #define QSERDES_RX0_RX_MODE_01_LOW 0x184 96 #define QSERDES_RX0_RX_MODE_01_HIGH 0x188 97 #define QSERDES_RX0_RX_MODE_01_HIGH2 0x18c 98 #define QSERDES_RX0_RX_MODE_01_HIGH3 0x190 99 #define QSERDES_RX0_RX_MODE_01_HIGH4 0x194 100 #define QSERDES_RX0_RX_MODE_10_LOW 0x198 101 #define QSERDES_RX0_RX_MODE_10_HIGH 0x19c 102 #define QSERDES_RX0_RX_MODE_10_HIGH2 0x1a0 103 #define QSERDES_RX0_RX_MODE_10_HIGH3 0x1a4 104 #define QSERDES_RX0_RX_MODE_10_HIGH4 0x1a8 105 #define QSERDES_RX0_DFE_EN_TIMER 0x1b4 106 107 /* QMP V2 PHY for PCIE gen3 ports - PCS registers */ 108 109 #define PCS_COM_FLL_CNTRL1 0x098 110 #define PCS_COM_FLL_CNTRL2 0x09c 111 #define PCS_COM_FLL_CNT_VAL_L 0x0a0 112 #define PCS_COM_FLL_CNT_VAL_H_TOL 0x0a4 113 #define PCS_COM_FLL_MAN_CODE 0x0a8 114 #define PCS_COM_REFGEN_REQ_CONFIG1 0x0dc 115 #define PCS_COM_G12S1_TXDEEMPH_M3P5DB 0x16c 116 #define PCS_COM_RX_SIGDET_LVL 0x188 117 #define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 118 #define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 119 #define PCS_COM_RX_DCC_CAL_CONFIG 0x1d8 120 #define PCS_COM_EQ_CONFIG5 0x1ec 121 122 /* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */ 123 124 #define PCS_PCIE_POWER_STATE_CONFIG2 0x40c 125 #define PCS_PCIE_POWER_STATE_CONFIG4 0x414 126 #define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c 127 #define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440 128 #define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444 129 #define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448 130 #define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c 131 #define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c 132 #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478 133 #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480 134 #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484 135 #define PCS_PCIE_OSC_DTCT_ACTIONS 0x490 136 #define PCS_PCIE_EQ_CONFIG1 0x4a0 137 #define PCS_PCIE_EQ_CONFIG2 0x4a4 138 #define PCS_PCIE_PRESET_P10_PRE 0x4bc 139 #define PCS_PCIE_PRESET_P10_POST 0x4e0 140 141 /* Only for QMP V2 PHY - QSERDES COM registers */ 142 #define QSERDES_COM_BG_TIMER 0x00c 143 #define QSERDES_COM_SSC_EN_CENTER 0x010 144 #define QSERDES_COM_SSC_ADJ_PER1 0x014 145 #define QSERDES_COM_SSC_ADJ_PER2 0x018 146 #define QSERDES_COM_SSC_PER1 0x01c 147 #define QSERDES_COM_SSC_PER2 0x020 148 #define QSERDES_COM_SSC_STEP_SIZE1 0x024 149 #define QSERDES_COM_SSC_STEP_SIZE2 0x028 150 #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 151 #define QSERDES_COM_CLK_ENABLE1 0x038 152 #define QSERDES_COM_SYS_CLK_CTRL 0x03c 153 #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 154 #define QSERDES_COM_PLL_IVCO 0x048 155 #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 156 #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 157 #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 158 #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 159 #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 160 #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 161 #define QSERDES_COM_BG_TRIM 0x070 162 #define QSERDES_COM_CLK_EP_DIV 0x074 163 #define QSERDES_COM_CP_CTRL_MODE0 0x078 164 #define QSERDES_COM_CP_CTRL_MODE1 0x07c 165 #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 166 #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 167 #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 168 #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 169 #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 170 #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 171 #define QSERDES_COM_RESETSM_CNTRL 0x0b4 172 #define QSERDES_COM_RESETSM_CNTRL2 0x0b8 173 #define QSERDES_COM_RESTRIM_CTRL 0x0bc 174 #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 175 #define QSERDES_COM_LOCK_CMP_EN 0x0c8 176 #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 177 #define QSERDES_COM_DEC_START_MODE0 0x0d0 178 #define QSERDES_COM_DEC_START_MODE1 0x0d4 179 #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 180 #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 181 #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 182 #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 183 #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 184 #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 185 #define QSERDES_COM_INTEGLOOP_INITVAL 0x100 186 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 187 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 188 #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 189 #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 190 #define QSERDES_COM_VCO_TUNE_CTRL 0x124 191 #define QSERDES_COM_VCO_TUNE_MAP 0x128 192 #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 193 #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 194 #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 195 #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 196 #define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c 197 #define QSERDES_COM_VCO_TUNE_INITVAL2 0x140 198 #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 199 #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 200 #define QSERDES_COM_BG_CTRL 0x170 201 #define QSERDES_COM_CLK_SELECT 0x174 202 #define QSERDES_COM_HSCLK_SEL 0x178 203 #define QSERDES_COM_CORECLK_DIV 0x184 204 #define QSERDES_COM_CORE_CLK_EN 0x18c 205 #define QSERDES_COM_C_READY_STATUS 0x190 206 #define QSERDES_COM_CMN_CONFIG 0x194 207 #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 208 #define QSERDES_COM_DEBUG_BUS0 0x1a0 209 #define QSERDES_COM_DEBUG_BUS1 0x1a4 210 #define QSERDES_COM_DEBUG_BUS2 0x1a8 211 #define QSERDES_COM_DEBUG_BUS3 0x1ac 212 #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 213 #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 214 215 /* Only for QMP V2 PHY - TX registers */ 216 #define QSERDES_TX_EMP_POST1_LVL 0x018 217 #define QSERDES_TX_SLEW_CNTL 0x040 218 #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 219 #define QSERDES_TX_DEBUG_BUS_SEL 0x064 220 #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 221 #define QSERDES_TX_LANE_MODE 0x094 222 #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 223 224 /* Only for QMP V2 PHY - RX registers */ 225 #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 226 #define QSERDES_RX_UCDR_SO_GAIN 0x01c 227 #define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030 228 #define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034 229 #define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038 230 #define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c 231 #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 232 #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 233 #define QSERDES_RX_RX_TERM_BW 0x090 234 #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 235 #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 236 #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 237 #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 238 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 239 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 240 #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 241 #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 242 #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 243 #define QSERDES_RX_SIGDET_ENABLES 0x110 244 #define QSERDES_RX_SIGDET_CNTRL 0x114 245 #define QSERDES_RX_SIGDET_LVL 0x118 246 #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 247 #define QSERDES_RX_RX_BAND 0x120 248 #define QSERDES_RX_RX_INTERFACE_MODE 0x12c 249 250 /* Only for QMP V2 PHY - PCS registers */ 251 #define QPHY_POWER_DOWN_CONTROL 0x04 252 #define QPHY_TXDEEMPH_M6DB_V0 0x24 253 #define QPHY_TXDEEMPH_M3P5DB_V0 0x28 254 #define QPHY_TX_LARGE_AMP_DRV_LVL 0x34 255 #define QPHY_TX_LARGE_AMP_POST_EMP_LVL 0x38 256 #define QPHY_TX_SMALL_AMP_DRV_LVL 0x3c 257 #define QPHY_TX_SMALL_AMP_POST_EMP_LVL 0x40 258 #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 259 #define QPHY_RX_IDLE_DTCT_CNTRL 0x58 260 #define QPHY_POWER_STATE_CONFIG1 0x60 261 #define QPHY_POWER_STATE_CONFIG2 0x64 262 #define QPHY_POWER_STATE_CONFIG4 0x6c 263 #define QPHY_LOCK_DETECT_CONFIG1 0x80 264 #define QPHY_LOCK_DETECT_CONFIG2 0x84 265 #define QPHY_LOCK_DETECT_CONFIG3 0x88 266 #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 267 #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 268 #define QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc 269 #define QPHY_RX_SYM_RESYNC_CTRL 0x13c 270 #define QPHY_RX_MIN_HIBERN8_TIME 0x140 271 #define QPHY_RX_SIGDET_CTRL2 0x148 272 #define QPHY_RX_PWM_GEAR_BAND 0x154 273 #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 274 #define QPHY_OSC_DTCT_ACTIONS 0x1AC 275 #define QPHY_RX_SIGDET_LVL 0x1D8 276 #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC 277 #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 278 279 /* Only for QMP V3 & V4 PHY - DP COM registers */ 280 #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 281 #define QPHY_V3_DP_COM_SW_RESET 0x04 282 #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 283 #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 284 #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 285 #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 286 #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 287 288 /* Only for QMP V3 PHY - QSERDES COM registers */ 289 #define QSERDES_V3_COM_ATB_SEL1 0x000 290 #define QSERDES_V3_COM_ATB_SEL2 0x004 291 #define QSERDES_V3_COM_FREQ_UPDATE 0x008 292 #define QSERDES_V3_COM_BG_TIMER 0x00c 293 #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 294 #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 295 #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 296 #define QSERDES_V3_COM_SSC_PER1 0x01c 297 #define QSERDES_V3_COM_SSC_PER2 0x020 298 #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 299 #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 300 #define QSERDES_V3_COM_POST_DIV 0x02c 301 #define QSERDES_V3_COM_POST_DIV_MUX 0x030 302 #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 303 # define QSERDES_V3_COM_BIAS_EN 0x0001 304 # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 305 # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 306 # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 307 # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 308 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 309 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 310 #define QSERDES_V3_COM_CLK_ENABLE1 0x038 311 #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 312 #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 313 #define QSERDES_V3_COM_PLL_EN 0x044 314 #define QSERDES_V3_COM_PLL_IVCO 0x048 315 #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 316 #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 317 #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 318 #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 319 #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 320 #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 321 #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 322 #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 323 #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 324 #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 325 #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 326 #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 327 #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 328 #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 329 #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 330 #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 331 #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 332 #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 333 #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 334 #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 335 #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 336 #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 337 #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 338 #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 339 #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 340 #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 341 #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 342 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 343 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 344 #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 345 #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 346 #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 347 #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 348 #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 349 #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 350 #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 351 #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 352 #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 353 #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 354 #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 355 #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 356 #define QSERDES_V3_COM_CLK_SELECT 0x138 357 #define QSERDES_V3_COM_HSCLK_SEL 0x13c 358 #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 359 #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 360 #define QSERDES_V3_COM_CORE_CLK_EN 0x154 361 #define QSERDES_V3_COM_C_READY_STATUS 0x158 362 #define QSERDES_V3_COM_CMN_CONFIG 0x15c 363 #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 364 #define QSERDES_V3_COM_DEBUG_BUS0 0x168 365 #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 366 #define QSERDES_V3_COM_DEBUG_BUS2 0x170 367 #define QSERDES_V3_COM_DEBUG_BUS3 0x174 368 #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 369 #define QSERDES_V3_COM_CMN_MODE 0x184 370 371 /* Only for QMP V3 PHY - TX registers */ 372 #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 373 #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 374 #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c 375 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 376 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 377 378 #define QSERDES_V3_TX_TX_DRV_LVL 0x01c 379 # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 380 # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 381 382 #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 383 #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 384 385 #define QSERDES_V3_TX_TX_BAND 0x02c 386 #define QSERDES_V3_TX_SLEW_CNTL 0x030 387 #define QSERDES_V3_TX_INTERFACE_SELECT 0x034 388 #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c 389 #define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 390 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 391 #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 392 #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 393 #define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c 394 #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 395 #define QSERDES_V3_TX_TX_POL_INV 0x064 396 #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 397 #define QSERDES_V3_TX_LANE_MODE_1 0x08c 398 #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 399 #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 400 #define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 401 #define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 402 403 /* Only for QMP V3 PHY - RX registers */ 404 #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 405 #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 406 #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 407 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 408 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 409 #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 410 #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 411 #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 412 #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 413 #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 414 #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 415 #define QSERDES_V3_RX_RX_TERM_BW 0x07c 416 #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 417 #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 418 #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 419 #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 420 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 421 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 422 #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 423 #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 424 #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 425 #define QSERDES_V3_RX_SIGDET_ENABLES 0x100 426 #define QSERDES_V3_RX_SIGDET_CNTRL 0x104 427 #define QSERDES_V3_RX_SIGDET_LVL 0x108 428 #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 429 #define QSERDES_V3_RX_RX_BAND 0x110 430 #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 431 #define QSERDES_V3_RX_RX_MODE_00 0x164 432 #define QSERDES_V3_RX_RX_MODE_01 0x168 433 434 /* Only for QMP V3 PHY - PCS registers */ 435 #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 436 #define QPHY_V3_PCS_TXMGN_V0 0x00c 437 #define QPHY_V3_PCS_TXMGN_V1 0x010 438 #define QPHY_V3_PCS_TXMGN_V2 0x014 439 #define QPHY_V3_PCS_TXMGN_V3 0x018 440 #define QPHY_V3_PCS_TXMGN_V4 0x01c 441 #define QPHY_V3_PCS_TXMGN_LS 0x020 442 #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 443 #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 444 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 445 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 446 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 447 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 448 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 449 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 450 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 451 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 452 #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 453 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 454 #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 455 #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 456 #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 457 #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 458 #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 459 #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 460 #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 461 #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 462 #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 463 #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 464 #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 465 #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 466 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 467 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 468 #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 469 #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 470 #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 471 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 472 #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 473 #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 474 #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 475 #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 476 #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 477 #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 478 #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 479 #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 480 #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 481 #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 482 #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 483 #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 484 #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 485 #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 486 #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 487 #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 488 #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 489 #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 490 #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 491 #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 492 #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 493 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 494 #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 495 496 /* Only for QMP V3 PHY - PCS_MISC registers */ 497 #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 498 #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 499 #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 500 #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 501 #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 502 #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 503 504 /* QMP PHY - DP PHY registers */ 505 #define QSERDES_DP_PHY_REVISION_ID0 0x000 506 #define QSERDES_DP_PHY_REVISION_ID1 0x004 507 #define QSERDES_DP_PHY_REVISION_ID2 0x008 508 #define QSERDES_DP_PHY_REVISION_ID3 0x00c 509 #define QSERDES_DP_PHY_CFG 0x010 510 #define QSERDES_DP_PHY_PD_CTL 0x018 511 # define DP_PHY_PD_CTL_PWRDN 0x001 512 # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 513 # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 514 # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 515 # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 516 # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 517 # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 518 #define QSERDES_DP_PHY_MODE 0x01c 519 #define QSERDES_DP_PHY_AUX_CFG0 0x020 520 #define QSERDES_DP_PHY_AUX_CFG1 0x024 521 #define QSERDES_DP_PHY_AUX_CFG2 0x028 522 #define QSERDES_DP_PHY_AUX_CFG3 0x02c 523 #define QSERDES_DP_PHY_AUX_CFG4 0x030 524 #define QSERDES_DP_PHY_AUX_CFG5 0x034 525 #define QSERDES_DP_PHY_AUX_CFG6 0x038 526 #define QSERDES_DP_PHY_AUX_CFG7 0x03c 527 #define QSERDES_DP_PHY_AUX_CFG8 0x040 528 #define QSERDES_DP_PHY_AUX_CFG9 0x044 529 530 /* Only for QMP V3 PHY - DP PHY registers */ 531 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 532 # define PHY_AUX_STOP_ERR_MASK 0x01 533 # define PHY_AUX_DEC_ERR_MASK 0x02 534 # define PHY_AUX_SYNC_ERR_MASK 0x04 535 # define PHY_AUX_ALIGN_ERR_MASK 0x08 536 # define PHY_AUX_REQ_ERR_MASK 0x10 537 538 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 539 #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 540 541 #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 542 #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 543 #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 544 545 #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 546 #define DP_PHY_SPARE0_MASK 0x0f 547 #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 548 549 #define QSERDES_V3_DP_PHY_STATUS 0x0c0 550 551 /* Only for QMP V4 PHY - QSERDES COM registers */ 552 #define QSERDES_V4_COM_BG_TIMER 0x00c 553 #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 554 #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014 555 #define QSERDES_V4_COM_SSC_PER1 0x01c 556 #define QSERDES_V4_COM_SSC_PER2 0x020 557 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 558 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 559 #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 560 #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 561 #define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 562 #define QSERDES_V4_COM_CLK_ENABLE1 0x048 563 #define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c 564 #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 565 #define QSERDES_V4_COM_PLL_IVCO 0x058 566 #define QSERDES_V4_COM_CMN_IPTRIM 0x060 567 #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 568 #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 569 #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 570 #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 571 #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 572 #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 573 #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 574 #define QSERDES_V4_COM_RESETSM_CNTRL 0x09c 575 #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 576 #define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8 577 #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 578 #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 579 #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 580 #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 581 #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 582 #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 583 #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 584 #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 585 #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 586 #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 587 #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 588 #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 589 #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec 590 #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 591 #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 592 #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 593 #define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 594 #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 595 #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 596 #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 597 #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 598 #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 599 #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 600 #define QSERDES_V4_COM_CMN_STATUS 0x140 601 #define QSERDES_V4_COM_CLK_SELECT 0x154 602 #define QSERDES_V4_COM_HSCLK_SEL 0x158 603 #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 604 #define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 605 #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 606 #define QSERDES_V4_COM_CORE_CLK_EN 0x174 607 #define QSERDES_V4_COM_C_READY_STATUS 0x178 608 #define QSERDES_V4_COM_CMN_CONFIG 0x17c 609 #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 610 #define QSERDES_V4_COM_CMN_MISC1 0x19c 611 #define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0 612 #define QSERDES_V4_COM_CMN_MODE 0x1a4 613 #define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8 614 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 615 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 616 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 617 #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 618 #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 619 620 /* Only for QMP V4 PHY - TX registers */ 621 #define QSERDES_V4_TX_CLKBUF_ENABLE 0x08 622 #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c 623 #define QSERDES_V4_TX_TX_DRV_LVL 0x14 624 #define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c 625 #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20 626 #define QSERDES_V4_TX_TX_BAND 0x24 627 #define QSERDES_V4_TX_INTERFACE_SELECT 0x2c 628 #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 629 #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 630 #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c 631 #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 632 #define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54 633 #define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58 634 #define QSERDES_V4_TX_TX_POL_INV 0x5c 635 #define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 636 #define QSERDES_V4_TX_LANE_MODE_1 0x84 637 #define QSERDES_V4_TX_LANE_MODE_2 0x88 638 #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 639 #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 640 #define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc 641 #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 642 #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC 643 #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 644 #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 645 #define QSERDES_V4_TX_VMODE_CTRL1 0xe8 646 #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 647 648 /* Only for QMP V4_20 PHY - TX registers */ 649 #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 650 #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 651 #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 652 #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 653 #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 654 655 /* Only for QMP V4 PHY - RX registers */ 656 #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 657 #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 658 #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 659 #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 660 #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 661 #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 662 #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 663 #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 664 #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 665 #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 666 #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 667 #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 668 #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 669 #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 670 #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 671 #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 672 #define QSERDES_V4_RX_RX_TERM_BW 0x080 673 #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 674 #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 675 #define QSERDES_V4_RX_GM_CAL 0x0dc 676 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 677 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 678 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 679 #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 680 #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 681 #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 682 #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 683 #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 684 #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 685 #define QSERDES_V4_RX_SIGDET_ENABLES 0x118 686 #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 687 #define QSERDES_V4_RX_SIGDET_LVL 0x120 688 #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 689 #define QSERDES_V4_RX_RX_BAND 0x128 690 #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 691 #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 692 #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 693 #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 694 #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 695 #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 696 #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 697 #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 698 #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 699 #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 700 #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 701 #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 702 #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 703 #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 704 #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 705 #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 706 #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 707 #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 708 #define QSERDES_V4_RX_VTH_CODE 0x1c4 709 710 /* Only for QMP V4 PHY - DP PHY registers */ 711 #define QSERDES_V4_DP_PHY_CFG_1 0x014 712 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 713 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 714 #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 715 #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 716 #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 717 #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 718 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 719 #define QSERDES_V4_DP_PHY_STATUS 0x0dc 720 721 /* Only for QMP V4_20 PHY - RX registers */ 722 #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 723 #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 724 #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 725 #define QSERDES_V4_20_RX_DFE_3 0x110 726 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 727 #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 728 #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 729 #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 730 #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 731 #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 732 #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 733 #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 734 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 735 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 736 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 737 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 738 #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 739 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 740 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 741 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 742 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 743 #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 744 #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 745 #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 746 #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 747 748 /* Only for QMP V4 PHY - UFS PCS registers */ 749 #define QPHY_V4_PCS_UFS_PHY_START 0x000 750 #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 751 #define QPHY_V4_PCS_UFS_SW_RESET 0x008 752 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 753 #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 754 #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 755 #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 756 #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 757 #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 758 #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 759 #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 760 #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 761 #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 762 #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 763 #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 764 #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 765 #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 766 #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 767 #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 768 #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 769 770 /* PCIE GEN3 COM registers */ 771 #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 772 #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 773 #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 774 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 775 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 776 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 777 #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 778 #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 779 #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 780 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 781 #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 782 #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 783 #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 784 #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 785 #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 786 #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 787 #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 788 #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 789 #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 790 #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 791 #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 792 #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 793 #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 794 #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 795 #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 796 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 797 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 798 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 799 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 800 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 801 #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 802 #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 803 #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 804 #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 805 #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 806 #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 807 #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 808 #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 809 #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 810 #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 811 #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 812 #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 813 #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 814 #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 815 #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 816 817 /* PCIE GEN3 QHP Lane registers */ 818 #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 819 #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 820 #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 821 #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 822 #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 823 #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 824 #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 825 #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 826 #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 827 #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 828 #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 829 #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 830 #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 831 #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 832 #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 833 #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 834 #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 835 #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 836 #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 837 #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 838 #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 839 #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 840 #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 841 #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 842 #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 843 #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 844 #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 845 #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 846 #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 847 #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 848 #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 849 #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 850 #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 851 #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 852 #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 853 #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 854 #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 855 #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 856 #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 857 #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 858 #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 859 #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 860 #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 861 #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 862 #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 863 #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 864 #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 865 #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 866 #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 867 #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 868 #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 869 #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 870 #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 871 #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 872 #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 873 #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 874 875 /* PCIE GEN3 PCS registers */ 876 #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 877 #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 878 #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 879 #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 880 #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 881 #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 882 #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 883 884 /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 885 #define QPHY_V4_PCS_SW_RESET 0x000 886 #define QPHY_V4_PCS_REVISION_ID0 0x004 887 #define QPHY_V4_PCS_REVISION_ID1 0x008 888 #define QPHY_V4_PCS_REVISION_ID2 0x00c 889 #define QPHY_V4_PCS_REVISION_ID3 0x010 890 #define QPHY_V4_PCS_PCS_STATUS1 0x014 891 #define QPHY_V4_PCS_PCS_STATUS2 0x018 892 #define QPHY_V4_PCS_PCS_STATUS3 0x01c 893 #define QPHY_V4_PCS_PCS_STATUS4 0x020 894 #define QPHY_V4_PCS_PCS_STATUS5 0x024 895 #define QPHY_V4_PCS_PCS_STATUS6 0x028 896 #define QPHY_V4_PCS_PCS_STATUS7 0x02c 897 #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 898 #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 899 #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 900 #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 901 #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 902 #define QPHY_V4_PCS_START_CONTROL 0x044 903 #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 904 #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 905 #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 906 #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 907 #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 908 #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 909 #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 910 #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 911 #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 912 #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 913 #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 914 #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 915 #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 916 #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 917 #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 918 #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 919 #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 920 #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 921 #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 922 #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 923 #define QPHY_V4_PCS_FLL_CNTRL1 0x098 924 #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 925 #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 926 #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 927 #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 928 #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 929 #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 930 #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 931 #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 932 #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 933 #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 934 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 935 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 936 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 937 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 938 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 939 #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 940 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 941 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 942 #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 943 #define QPHY_V4_PCS_BIST_CTRL 0x0e8 944 #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 945 #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 946 #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 947 #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 948 #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 949 #define QPHY_V4_PCS_FIXED_PAT3 0x100 950 #define QPHY_V4_PCS_FIXED_PAT4 0x104 951 #define QPHY_V4_PCS_FIXED_PAT5 0x108 952 #define QPHY_V4_PCS_FIXED_PAT6 0x10c 953 #define QPHY_V4_PCS_FIXED_PAT7 0x110 954 #define QPHY_V4_PCS_FIXED_PAT8 0x114 955 #define QPHY_V4_PCS_FIXED_PAT9 0x118 956 #define QPHY_V4_PCS_FIXED_PAT10 0x11c 957 #define QPHY_V4_PCS_FIXED_PAT11 0x120 958 #define QPHY_V4_PCS_FIXED_PAT12 0x124 959 #define QPHY_V4_PCS_FIXED_PAT13 0x128 960 #define QPHY_V4_PCS_FIXED_PAT14 0x12c 961 #define QPHY_V4_PCS_FIXED_PAT15 0x130 962 #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 963 #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 964 #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 965 #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 966 #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 967 #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 968 #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 969 #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 970 #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 971 #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 972 #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 973 #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 974 #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 975 #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 976 #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 977 #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 978 #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 979 #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 980 #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 981 #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 982 #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 983 #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 984 #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 985 #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 986 #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 987 #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 988 #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 989 #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 990 #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 991 #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 992 #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 993 #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 994 #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 995 #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 996 #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 997 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 998 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 999 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 1000 #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 1001 #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 1002 #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 1003 #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 1004 #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 1005 #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 1006 #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 1007 #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 1008 #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 1009 #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300 1010 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 1011 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 1012 #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 1013 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 1014 #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 1015 #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 1016 #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c 1017 #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 1018 #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 1019 #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328 1020 #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c 1021 #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330 1022 #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334 1023 #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338 1024 #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c 1025 #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340 1026 #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344 1027 #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348 1028 #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c 1029 #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350 1030 #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 1031 #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 1032 1033 /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 1034 #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 1035 #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 1036 #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 1037 #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 1038 1039 /* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */ 1040 #define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618 1041 #define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638 1042 1043 /* Only for QMP V4 PHY - PCS_MISC registers */ 1044 #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 1045 #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 1046 #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 1047 #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 1048 #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 1049 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 1050 1051 /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 1052 #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 1053 #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 1054 #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 1055 #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 1056 #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 1057 #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 1058 #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 1059 #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 1060 #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 1061 #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 1062 #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 1063 1064 #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 1065 #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 1066 #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 1067 #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 1068 #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 1069 #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 1070 #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 1071 1072 /* Only for QMP V5 PHY - QSERDES COM registers */ 1073 #define QSERDES_V5_COM_SSC_EN_CENTER 0x010 1074 #define QSERDES_V5_COM_SSC_PER1 0x01c 1075 #define QSERDES_V5_COM_SSC_PER2 0x020 1076 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 1077 #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 1078 #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 1079 #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 1080 #define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 1081 #define QSERDES_V5_COM_CLK_ENABLE1 0x048 1082 #define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 1083 #define QSERDES_V5_COM_PLL_IVCO 0x058 1084 #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 1085 #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 1086 #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c 1087 #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 1088 #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 1089 #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 1090 #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 1091 #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 1092 #define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 1093 #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac 1094 #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 1095 #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 1096 #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc 1097 #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 1098 #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 1099 #define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc 1100 #define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 1101 #define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 1102 #define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 1103 #define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc 1104 #define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 1105 #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c 1106 #define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 1107 #define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 1108 #define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 1109 #define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c 1110 #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 1111 #define QSERDES_V5_COM_CLK_SELECT 0x154 1112 #define QSERDES_V5_COM_HSCLK_SEL 0x158 1113 #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c 1114 #define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 1115 #define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c 1116 #define QSERDES_V5_COM_CORE_CLK_EN 0x174 1117 #define QSERDES_V5_COM_CMN_CONFIG 0x17c 1118 #define QSERDES_V5_COM_CMN_MISC1 0x19c 1119 #define QSERDES_V5_COM_CMN_MODE 0x1a4 1120 #define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8 1121 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 1122 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 1123 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 1124 #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 1125 #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 1126 1127 /* Only for QMP V5 PHY - TX registers */ 1128 #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 1129 #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38 1130 #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c 1131 #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40 1132 #define QSERDES_V5_TX_LANE_MODE_1 0x84 1133 #define QSERDES_V5_TX_LANE_MODE_2 0x88 1134 #define QSERDES_V5_TX_LANE_MODE_3 0x8c 1135 #define QSERDES_V5_TX_LANE_MODE_4 0x90 1136 #define QSERDES_V5_TX_LANE_MODE_5 0x94 1137 #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4 1138 #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0 1139 #define QSERDES_V5_TX_PI_QEC_CTRL 0xe4 1140 #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 1141 #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 1142 #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 1143 #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 1144 1145 /* Only for QMP V5_20 PHY - TX registers */ 1146 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 1147 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 1148 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 1149 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 1150 1151 /* Only for QMP V5 PHY - RX registers */ 1152 #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 1153 #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 1154 #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 1155 #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 1156 #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 1157 #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 1158 #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 1159 #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 1160 #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c 1161 #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 1162 #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 1163 #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 1164 #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 1165 #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 1166 #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 1167 #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 1168 #define QSERDES_V5_RX_RX_TERM_BW 0x080 1169 #define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc 1170 #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 1171 #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 1172 #define QSERDES_V5_RX_GM_CAL 0x0dc 1173 #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 1174 #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 1175 #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 1176 #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 1177 #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 1178 #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 1179 #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 1180 #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 1181 #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 1182 #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 1183 #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c 1184 #define QSERDES_V5_RX_SIGDET_LVL 0x120 1185 #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 1186 #define QSERDES_V5_RX_RX_BAND 0x128 1187 #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 1188 #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 1189 #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 1190 #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 1191 #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c 1192 #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 1193 #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 1194 #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 1195 #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c 1196 #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 1197 #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 1198 #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 1199 #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 1200 #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 1201 #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 1202 #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 1203 #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 1204 #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 1205 #define QSERDES_V5_RX_VTH_CODE 0x1b0 1206 1207 /* Only for QMP V5_20 PHY - RX registers */ 1208 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 1209 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c 1210 #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 1211 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c 1212 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 1213 #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c 1214 #define QSERDES_V5_20_RX_DFE_3 0x090 1215 #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 1216 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 1217 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 1218 #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc 1219 #define QSERDES_V5_20_RX_GM_CAL 0x0ec 1220 #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 1221 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 1222 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 1223 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c 1224 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 1225 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 1226 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c 1227 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 1228 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 1229 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 1230 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c 1231 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 1232 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 1233 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 1234 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c 1235 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 1236 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 1237 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 1238 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac 1239 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 1240 #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 1241 #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 1242 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 1243 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 1244 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc 1245 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 1246 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 1247 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 1248 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 1249 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 1250 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 1251 1252 /* Only for QMP V5 PHY - USB/PCIe PCS registers */ 1253 #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc 1254 #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 1255 #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 1256 #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 1257 #define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 1258 #define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 1259 1260 /* Only for QMP V5 PHY - PCS_PCIE registers */ 1261 #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 1262 #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 1263 #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 1264 #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 1265 1266 /* Only for QMP V5_20 PHY - PCIe PCS registers */ 1267 #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 1268 #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 1269 #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 1270 #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 1271 #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 1272 #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 1273 1274 /* Only for QMP V5 PHY - UFS PCS registers */ 1275 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 1276 #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 1277 #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 1278 #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 1279 #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 1280 #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 1281 #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 1282 #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 1283 #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 1284 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 1285 #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 1286 #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 1287 #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 1288 #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 1289 #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 1290 1291 /* Only for QMP V5 PHY - USB3 have different offsets than V4 */ 1292 #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x300 1293 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 1294 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 1295 #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 1296 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 1297 #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 1298 #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 1299 #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x31c 1300 #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 1301 #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 1302 #define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x328 1303 #define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x32c 1304 #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x330 1305 #define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x334 1306 #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x338 1307 #define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x33c 1308 #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x340 1309 #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x344 1310 #define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x348 1311 #define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x34c 1312 #define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x350 1313 #define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x354 1314 #define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x358 1315 #define QPHY_V5_PCS_USB3_TEST_CONTROL 0x35c 1316 #define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x360 1317 1318 /* Only for QMP V5 PHY - UNI has 0x1000 offset for PCS_USB3 regs */ 1319 #define QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x1018 1320 #define QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x103c 1321 1322 #endif 1323