1 /* SPDX-License-Identifier: GPL-2.0 */
2 /*
3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4  */
5 
6 #ifndef QCOM_PHY_QMP_H_
7 #define QCOM_PHY_QMP_H_
8 
9 #include "phy-qcom-qmp-qserdes-com.h"
10 #include "phy-qcom-qmp-qserdes-txrx.h"
11 
12 #include "phy-qcom-qmp-qserdes-com-v3.h"
13 #include "phy-qcom-qmp-qserdes-txrx-v3.h"
14 
15 #include "phy-qcom-qmp-qserdes-com-v4.h"
16 #include "phy-qcom-qmp-qserdes-txrx-v4.h"
17 #include "phy-qcom-qmp-qserdes-txrx-v4_20.h"
18 
19 #include "phy-qcom-qmp-qserdes-com-v5.h"
20 #include "phy-qcom-qmp-qserdes-txrx-v5.h"
21 #include "phy-qcom-qmp-qserdes-txrx-v5_20.h"
22 #include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h"
23 
24 #include "phy-qcom-qmp-qserdes-com-v6.h"
25 #include "phy-qcom-qmp-qserdes-txrx-v6.h"
26 #include "phy-qcom-qmp-qserdes-txrx-v6_20.h"
27 #include "phy-qcom-qmp-qserdes-ln-shrd-v6.h"
28 
29 #include "phy-qcom-qmp-qserdes-pll.h"
30 
31 #include "phy-qcom-qmp-pcs-v2.h"
32 
33 #include "phy-qcom-qmp-pcs-v3.h"
34 
35 #include "phy-qcom-qmp-pcs-v4.h"
36 
37 #include "phy-qcom-qmp-pcs-v4_20.h"
38 
39 #include "phy-qcom-qmp-pcs-v5.h"
40 
41 #include "phy-qcom-qmp-pcs-v5_20.h"
42 
43 #include "phy-qcom-qmp-pcs-v6.h"
44 
45 #include "phy-qcom-qmp-pcs-v6_20.h"
46 
47 /* Only for QMP V3 & V4 PHY - DP COM registers */
48 #define QPHY_V3_DP_COM_PHY_MODE_CTRL			0x00
49 #define QPHY_V3_DP_COM_SW_RESET				0x04
50 #define QPHY_V3_DP_COM_POWER_DOWN_CTRL			0x08
51 #define QPHY_V3_DP_COM_SWI_CTRL				0x0c
52 #define QPHY_V3_DP_COM_TYPEC_CTRL			0x10
53 #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL			0x14
54 #define QPHY_V3_DP_COM_RESET_OVRD_CTRL			0x1c
55 
56 /* QSERDES V3 COM bits */
57 # define QSERDES_V3_COM_BIAS_EN				0x0001
58 # define QSERDES_V3_COM_BIAS_EN_MUX			0x0002
59 # define QSERDES_V3_COM_CLKBUF_R_EN			0x0004
60 # define QSERDES_V3_COM_CLKBUF_L_EN			0x0008
61 # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL		0x0010
62 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L		0x0020
63 # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R		0x0040
64 
65 /* QSERDES V3 TX bits */
66 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK		0x001f
67 # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN		0x0020
68 # define DP_PHY_TXn_TX_DRV_LVL_MASK			0x001f
69 # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN			0x0020
70 
71 /* QMP PHY - DP PHY registers */
72 #define QSERDES_DP_PHY_REVISION_ID0			0x000
73 #define QSERDES_DP_PHY_REVISION_ID1			0x004
74 #define QSERDES_DP_PHY_REVISION_ID2			0x008
75 #define QSERDES_DP_PHY_REVISION_ID3			0x00c
76 #define QSERDES_DP_PHY_CFG				0x010
77 #define QSERDES_DP_PHY_PD_CTL				0x018
78 # define DP_PHY_PD_CTL_PWRDN				0x001
79 # define DP_PHY_PD_CTL_PSR_PWRDN			0x002
80 # define DP_PHY_PD_CTL_AUX_PWRDN			0x004
81 # define DP_PHY_PD_CTL_LANE_0_1_PWRDN			0x008
82 # define DP_PHY_PD_CTL_LANE_2_3_PWRDN			0x010
83 # define DP_PHY_PD_CTL_PLL_PWRDN			0x020
84 # define DP_PHY_PD_CTL_DP_CLAMP_EN			0x040
85 #define QSERDES_DP_PHY_MODE				0x01c
86 #define QSERDES_DP_PHY_AUX_CFG0				0x020
87 #define QSERDES_DP_PHY_AUX_CFG1				0x024
88 #define QSERDES_DP_PHY_AUX_CFG2				0x028
89 #define QSERDES_DP_PHY_AUX_CFG3				0x02c
90 #define QSERDES_DP_PHY_AUX_CFG4				0x030
91 #define QSERDES_DP_PHY_AUX_CFG5				0x034
92 #define QSERDES_DP_PHY_AUX_CFG6				0x038
93 #define QSERDES_DP_PHY_AUX_CFG7				0x03c
94 #define QSERDES_DP_PHY_AUX_CFG8				0x040
95 #define QSERDES_DP_PHY_AUX_CFG9				0x044
96 
97 /* Only for QMP V3 PHY - DP PHY registers */
98 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK		0x048
99 # define PHY_AUX_STOP_ERR_MASK				0x01
100 # define PHY_AUX_DEC_ERR_MASK				0x02
101 # define PHY_AUX_SYNC_ERR_MASK				0x04
102 # define PHY_AUX_ALIGN_ERR_MASK				0x08
103 # define PHY_AUX_REQ_ERR_MASK				0x10
104 
105 #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR		0x04c
106 #define QSERDES_V3_DP_PHY_AUX_BIST_CFG			0x050
107 
108 #define QSERDES_V3_DP_PHY_VCO_DIV			0x064
109 #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL		0x06c
110 #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL		0x088
111 
112 #define QSERDES_V3_DP_PHY_SPARE0			0x0ac
113 #define DP_PHY_SPARE0_MASK				0x0f
114 #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT		0x04(0x0004)
115 
116 #define QSERDES_V3_DP_PHY_STATUS			0x0c0
117 
118 /* Only for QMP V4 PHY - DP PHY registers */
119 #define QSERDES_V4_DP_PHY_CFG_1				0x014
120 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK		0x054
121 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR		0x058
122 #define QSERDES_V4_DP_PHY_VCO_DIV			0x070
123 #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL		0x078
124 #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL		0x09c
125 #define QSERDES_V4_DP_PHY_SPARE0			0x0c8
126 #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS		0x0d8
127 #define QSERDES_V4_DP_PHY_STATUS			0x0dc
128 
129 /* Only for QMP V4 PHY - PCS_MISC registers */
130 #define QPHY_V4_PCS_MISC_TYPEC_CTRL			0x00
131 #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL		0x04
132 #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1		0x08
133 #define QPHY_V4_PCS_MISC_CLAMP_ENABLE			0x0c
134 #define QPHY_V4_PCS_MISC_TYPEC_STATUS			0x10
135 #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS		0x14
136 
137 /* Only for QMP V6 PHY - DP PHY registers */
138 #define QSERDES_V6_DP_PHY_AUX_INTERRUPT_STATUS		0x0e0
139 #define QSERDES_V6_DP_PHY_STATUS			0x0e4
140 
141 #endif
142