1e2248617SManu Gautam // SPDX-License-Identifier: GPL-2.0 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 9e2248617SManu Gautam /* Only for QMP V2 PHY - QSERDES COM registers */ 10e2248617SManu Gautam #define QSERDES_COM_BG_TIMER 0x00c 11e2248617SManu Gautam #define QSERDES_COM_SSC_EN_CENTER 0x010 12e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER1 0x014 13e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER2 0x018 14e2248617SManu Gautam #define QSERDES_COM_SSC_PER1 0x01c 15e2248617SManu Gautam #define QSERDES_COM_SSC_PER2 0x020 16e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE1 0x024 17e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE2 0x028 18e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 19e2248617SManu Gautam #define QSERDES_COM_CLK_ENABLE1 0x038 20e2248617SManu Gautam #define QSERDES_COM_SYS_CLK_CTRL 0x03c 21e2248617SManu Gautam #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 22e2248617SManu Gautam #define QSERDES_COM_PLL_IVCO 0x048 23e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 24e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 25e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 26e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 27e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 28e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 29e2248617SManu Gautam #define QSERDES_COM_BG_TRIM 0x070 30e2248617SManu Gautam #define QSERDES_COM_CLK_EP_DIV 0x074 31e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE0 0x078 32e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE1 0x07c 33e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 34e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 35e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 36e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 37e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 38e2248617SManu Gautam #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 39e2248617SManu Gautam #define QSERDES_COM_RESETSM_CNTRL 0x0b4 40e2248617SManu Gautam #define QSERDES_COM_RESTRIM_CTRL 0x0bc 41e2248617SManu Gautam #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 42e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_EN 0x0c8 43e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 44e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE0 0x0d0 45e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE1 0x0d4 46e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 47e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 48e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 49e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 50e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 51e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 52e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 53e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 54e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 55e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 56e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_CTRL 0x124 57e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_MAP 0x128 58e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 59e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 60e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 61e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 62e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 63e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 64e2248617SManu Gautam #define QSERDES_COM_BG_CTRL 0x170 65e2248617SManu Gautam #define QSERDES_COM_CLK_SELECT 0x174 66e2248617SManu Gautam #define QSERDES_COM_HSCLK_SEL 0x178 67e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV 0x184 68e2248617SManu Gautam #define QSERDES_COM_CORE_CLK_EN 0x18c 69e2248617SManu Gautam #define QSERDES_COM_C_READY_STATUS 0x190 70e2248617SManu Gautam #define QSERDES_COM_CMN_CONFIG 0x194 71e2248617SManu Gautam #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 72e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS0 0x1a0 73e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS1 0x1a4 74e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS2 0x1a8 75e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS3 0x1ac 76e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 77e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 78e2248617SManu Gautam 79e2248617SManu Gautam /* Only for QMP V2 PHY - TX registers */ 80e2248617SManu Gautam #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 81e2248617SManu Gautam #define QSERDES_TX_DEBUG_BUS_SEL 0x064 82e2248617SManu Gautam #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 83e2248617SManu Gautam #define QSERDES_TX_LANE_MODE 0x094 84e2248617SManu Gautam #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 85e2248617SManu Gautam 86e2248617SManu Gautam /* Only for QMP V2 PHY - RX registers */ 87e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 88e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN 0x01c 89e2248617SManu Gautam #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 90e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 91e2248617SManu Gautam #define QSERDES_RX_RX_TERM_BW 0x090 92e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 93e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 94e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 95e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 96e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 97e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 98e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 99e2248617SManu Gautam #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 100e2248617SManu Gautam #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 101e2248617SManu Gautam #define QSERDES_RX_SIGDET_ENABLES 0x110 102e2248617SManu Gautam #define QSERDES_RX_SIGDET_CNTRL 0x114 103e2248617SManu Gautam #define QSERDES_RX_SIGDET_LVL 0x118 104e2248617SManu Gautam #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 105e2248617SManu Gautam #define QSERDES_RX_RX_BAND 0x120 106e2248617SManu Gautam #define QSERDES_RX_RX_INTERFACE_MODE 0x12c 107e2248617SManu Gautam 108e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 109e2248617SManu Gautam #define QPHY_POWER_DOWN_CONTROL 0x04 110e2248617SManu Gautam #define QPHY_TXDEEMPH_M6DB_V0 0x24 111e2248617SManu Gautam #define QPHY_TXDEEMPH_M3P5DB_V0 0x28 112e2248617SManu Gautam #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 113e2248617SManu Gautam #define QPHY_RX_IDLE_DTCT_CNTRL 0x58 114e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG1 0x60 115e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG2 0x64 116e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG4 0x6c 117e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG1 0x80 118e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG2 0x84 119e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG3 0x88 120e2248617SManu Gautam #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 121e2248617SManu Gautam #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 122e2248617SManu Gautam #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 123e2248617SManu Gautam #define QPHY_OSC_DTCT_ACTIONS 0x1AC 124e2248617SManu Gautam #define QPHY_RX_SIGDET_LVL 0x1D8 125e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC 126e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 127e2248617SManu Gautam 128e2248617SManu Gautam #endif 129