1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 9520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ 10520264dbSSelvam Sathappan Periakaruppan 11520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TIMER 0x00c 12520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER1 0x01c 13520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER2 0x020 14520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 15520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 16520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 17520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 18520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 19520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_ENABLE1 0x040 20520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYS_CLK_CTRL 0x044 21520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 22520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_IVCO 0x050 23520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 24520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 25520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 26520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 27520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TRIM 0x074 28520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 29520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c 30520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE0 0x080 31520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE1 0x084 32520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 33520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_RCTRL_MODE1 0x08C 34520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 35520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 36520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 37520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 38520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_RESETSM_CNTRL 0x0b0 39520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP_EN 0x0c4 40520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE0 0x0cc 41520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE1 0x0d0 42520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 43520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc 44520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 45520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 46520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 47520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0eC 48520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 49520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 50520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 51520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c 52520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_MAP 0x120 53520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 54520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 55520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c 56520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 57520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c 58520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 59520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_SELECT 0x16c 60520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_HSCLK_SEL 0x170 61520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV 0x17c 62520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORE_CLK_EN 0x184 63520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CMN_CONFIG 0x18c 64520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 65520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 66520264dbSSelvam Sathappan Periakaruppan 67520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - QSERDES TX registers */ 68520264dbSSelvam Sathappan Periakaruppan 69520264dbSSelvam Sathappan Periakaruppan #define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX 0x03c 70520264dbSSelvam Sathappan Periakaruppan #define QSERDES_TX0_HIGHZ_DRVR_EN 0x058 71520264dbSSelvam Sathappan Periakaruppan #define QSERDES_TX0_LANE_MODE_1 0x084 72520264dbSSelvam Sathappan Periakaruppan #define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c 73520264dbSSelvam Sathappan Periakaruppan 74520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - QSERDES RX registers */ 75520264dbSSelvam Sathappan Periakaruppan 76520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_UCDR_FO_GAIN 0x008 77520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_UCDR_SO_GAIN 0x014 78520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE 0x034 79520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_UCDR_PI_CONTROLS 0x044 80520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 0x0ec 81520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 0x0f0 82520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 0x0f4 83520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_IDAC_TSETTLE_LOW 0x0f8 84520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH 0x0fc 85520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 86520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 0x114 87520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_SIGDET_ENABLES 0x118 88520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_SIGDET_CNTRL 0x11c 89520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL 0x124 90520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_LOW 0x170 91520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_HIGH 0x174 92520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_HIGH2 0x178 93520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_HIGH3 0x17c 94520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_HIGH4 0x180 95520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_LOW 0x184 96520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_HIGH 0x188 97520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_HIGH2 0x18c 98520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_HIGH3 0x190 99520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_HIGH4 0x194 100520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_LOW 0x198 101520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_HIGH 0x19c 102520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_HIGH2 0x1a0 103520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_HIGH3 0x1a4 104520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_HIGH4 0x1a8 105520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_DFE_EN_TIMER 0x1b4 106520264dbSSelvam Sathappan Periakaruppan 107520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - PCS registers */ 108520264dbSSelvam Sathappan Periakaruppan 109520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNTRL1 0x098 110520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNTRL2 0x09c 111520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNT_VAL_L 0x0a0 112520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNT_VAL_H_TOL 0x0a4 113520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_MAN_CODE 0x0a8 114520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_REFGEN_REQ_CONFIG1 0x0dc 115520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_G12S1_TXDEEMPH_M3P5DB 0x16c 116520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_RX_SIGDET_LVL 0x188 117520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 118520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 119520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_RX_DCC_CAL_CONFIG 0x1d8 120520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_EQ_CONFIG5 0x1ec 121520264dbSSelvam Sathappan Periakaruppan 122520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */ 123520264dbSSelvam Sathappan Periakaruppan 124520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_POWER_STATE_CONFIG2 0x40c 125520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_POWER_STATE_CONFIG4 0x414 126520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c 127520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440 128520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444 129520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448 130520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c 131520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c 132520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478 133520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480 134520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484 135520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_ACTIONS 0x490 136520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_EQ_CONFIG1 0x4a0 137520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_EQ_CONFIG2 0x4a4 138520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_PRESET_P10_PRE 0x4bc 139520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_PRESET_P10_POST 0x4e0 140520264dbSSelvam Sathappan Periakaruppan 141e2248617SManu Gautam /* Only for QMP V2 PHY - QSERDES COM registers */ 142e2248617SManu Gautam #define QSERDES_COM_BG_TIMER 0x00c 143e2248617SManu Gautam #define QSERDES_COM_SSC_EN_CENTER 0x010 144e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER1 0x014 145e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER2 0x018 146e2248617SManu Gautam #define QSERDES_COM_SSC_PER1 0x01c 147e2248617SManu Gautam #define QSERDES_COM_SSC_PER2 0x020 148e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE1 0x024 149e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE2 0x028 150e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 151e2248617SManu Gautam #define QSERDES_COM_CLK_ENABLE1 0x038 152e2248617SManu Gautam #define QSERDES_COM_SYS_CLK_CTRL 0x03c 153e2248617SManu Gautam #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 154e2248617SManu Gautam #define QSERDES_COM_PLL_IVCO 0x048 155e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 156e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 157e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 158e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 159e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 160e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 161e2248617SManu Gautam #define QSERDES_COM_BG_TRIM 0x070 162e2248617SManu Gautam #define QSERDES_COM_CLK_EP_DIV 0x074 163e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE0 0x078 164e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE1 0x07c 165e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 166e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 167e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 168e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 169e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 170e2248617SManu Gautam #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 171e2248617SManu Gautam #define QSERDES_COM_RESETSM_CNTRL 0x0b4 172e2248617SManu Gautam #define QSERDES_COM_RESTRIM_CTRL 0x0bc 173e2248617SManu Gautam #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 174e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_EN 0x0c8 175e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 176e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE0 0x0d0 177e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE1 0x0d4 178e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 179e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 180e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 181e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 182e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 183e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 184e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 185e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 186e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 187e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 188e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_CTRL 0x124 189e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_MAP 0x128 190e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 191e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 192e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 193e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 194e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 195e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 196e2248617SManu Gautam #define QSERDES_COM_BG_CTRL 0x170 197e2248617SManu Gautam #define QSERDES_COM_CLK_SELECT 0x174 198e2248617SManu Gautam #define QSERDES_COM_HSCLK_SEL 0x178 199e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV 0x184 200e2248617SManu Gautam #define QSERDES_COM_CORE_CLK_EN 0x18c 201e2248617SManu Gautam #define QSERDES_COM_C_READY_STATUS 0x190 202e2248617SManu Gautam #define QSERDES_COM_CMN_CONFIG 0x194 203e2248617SManu Gautam #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 204e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS0 0x1a0 205e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS1 0x1a4 206e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS2 0x1a8 207e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS3 0x1ac 208e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 209e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 210e2248617SManu Gautam 211e2248617SManu Gautam /* Only for QMP V2 PHY - TX registers */ 212afd55e6dSSivaprakash Murugesan #define QSERDES_TX_EMP_POST1_LVL 0x018 213afd55e6dSSivaprakash Murugesan #define QSERDES_TX_SLEW_CNTL 0x040 214e2248617SManu Gautam #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 215e2248617SManu Gautam #define QSERDES_TX_DEBUG_BUS_SEL 0x064 216e2248617SManu Gautam #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 217e2248617SManu Gautam #define QSERDES_TX_LANE_MODE 0x094 218e2248617SManu Gautam #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 219e2248617SManu Gautam 220e2248617SManu Gautam /* Only for QMP V2 PHY - RX registers */ 221e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 222e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN 0x01c 223e2248617SManu Gautam #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 224e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 225e2248617SManu Gautam #define QSERDES_RX_RX_TERM_BW 0x090 226e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 227e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 228e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 229e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 230e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 231e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 232e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 233e2248617SManu Gautam #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 234e2248617SManu Gautam #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 235e2248617SManu Gautam #define QSERDES_RX_SIGDET_ENABLES 0x110 236e2248617SManu Gautam #define QSERDES_RX_SIGDET_CNTRL 0x114 237e2248617SManu Gautam #define QSERDES_RX_SIGDET_LVL 0x118 238e2248617SManu Gautam #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 239e2248617SManu Gautam #define QSERDES_RX_RX_BAND 0x120 240e2248617SManu Gautam #define QSERDES_RX_RX_INTERFACE_MODE 0x12c 241e2248617SManu Gautam 242e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 243e2248617SManu Gautam #define QPHY_POWER_DOWN_CONTROL 0x04 244e2248617SManu Gautam #define QPHY_TXDEEMPH_M6DB_V0 0x24 245e2248617SManu Gautam #define QPHY_TXDEEMPH_M3P5DB_V0 0x28 246e2248617SManu Gautam #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 247e2248617SManu Gautam #define QPHY_RX_IDLE_DTCT_CNTRL 0x58 248e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG1 0x60 249e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG2 0x64 250e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG4 0x6c 251e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG1 0x80 252e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG2 0x84 253e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG3 0x88 254e2248617SManu Gautam #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 255e2248617SManu Gautam #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 256e2248617SManu Gautam #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 257e2248617SManu Gautam #define QPHY_OSC_DTCT_ACTIONS 0x1AC 258e2248617SManu Gautam #define QPHY_RX_SIGDET_LVL 0x1D8 259e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC 260e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 261e2248617SManu Gautam 2629a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 2639c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 2649c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 2659c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 2669c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 2679c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 2689c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 2699c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 2709c7761a3SManu Gautam 2719c7761a3SManu Gautam /* Only for QMP V3 PHY - QSERDES COM registers */ 27252e013d0SStephen Boyd #define QSERDES_V3_COM_ATB_SEL1 0x000 27352e013d0SStephen Boyd #define QSERDES_V3_COM_ATB_SEL2 0x004 27452e013d0SStephen Boyd #define QSERDES_V3_COM_FREQ_UPDATE 0x008 2759c7761a3SManu Gautam #define QSERDES_V3_COM_BG_TIMER 0x00c 2769c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 2779c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 2789c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 2799c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER1 0x01c 2809c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER2 0x020 2819c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 2829c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 2839c7761a3SManu Gautam #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 28452e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 28552e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 28652e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 28752e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 28852e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 28952e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 29052e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 2919c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_ENABLE1 0x038 2929c7761a3SManu Gautam #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 2939c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 2949c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_IVCO 0x048 2959c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 2969c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 2979c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 2989c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 2999c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 3009c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 3019c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 3029c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 3039c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 3049c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 3059c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 3069c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 3079c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 3089c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 3099c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 3109c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 3119c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 3129c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 3139c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 3149c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 3159c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 3169c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 3179c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 3189c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 3199c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 3209c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 321a51969faSJeffrey Hugo #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 3229c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 3239c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 3249c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 3259c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 3269c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 3279c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 3289c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 3299c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 3309c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 3319c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 332cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 333cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 3349c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 3359c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 3369c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_SELECT 0x138 3379c7761a3SManu Gautam #define QSERDES_V3_COM_HSCLK_SEL 0x13c 3389c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 3399c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 3409c7761a3SManu Gautam #define QSERDES_V3_COM_CORE_CLK_EN 0x154 3419c7761a3SManu Gautam #define QSERDES_V3_COM_C_READY_STATUS 0x158 3429c7761a3SManu Gautam #define QSERDES_V3_COM_CMN_CONFIG 0x15c 3439c7761a3SManu Gautam #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 3449c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS0 0x168 3459c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 3469c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS2 0x170 3479c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS3 0x174 3489c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 349a51969faSJeffrey Hugo #define QSERDES_V3_COM_CMN_MODE 0x184 3509c7761a3SManu Gautam 3519c7761a3SManu Gautam /* Only for QMP V3 PHY - TX registers */ 35252e013d0SStephen Boyd #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 35352e013d0SStephen Boyd #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 35452e013d0SStephen Boyd #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c 35552e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 35652e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 35752e013d0SStephen Boyd 35852e013d0SStephen Boyd #define QSERDES_V3_TX_TX_DRV_LVL 0x01c 35952e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 36052e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 36152e013d0SStephen Boyd 36252e013d0SStephen Boyd #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 36352e013d0SStephen Boyd #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 36452e013d0SStephen Boyd 36552e013d0SStephen Boyd #define QSERDES_V3_TX_TX_BAND 0x02c 36652e013d0SStephen Boyd #define QSERDES_V3_TX_SLEW_CNTL 0x030 36752e013d0SStephen Boyd #define QSERDES_V3_TX_INTERFACE_SELECT 0x034 36852e013d0SStephen Boyd #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c 36952e013d0SStephen Boyd #define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 3709c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 3719c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 3729c7761a3SManu Gautam #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 37352e013d0SStephen Boyd #define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c 3749c7761a3SManu Gautam #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 37552e013d0SStephen Boyd #define QSERDES_V3_TX_TX_POL_INV 0x064 37652e013d0SStephen Boyd #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 3779c7761a3SManu Gautam #define QSERDES_V3_TX_LANE_MODE_1 0x08c 3789c7761a3SManu Gautam #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 37952e013d0SStephen Boyd #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 38052e013d0SStephen Boyd #define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 38152e013d0SStephen Boyd #define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 3829c7761a3SManu Gautam 3839c7761a3SManu Gautam /* Only for QMP V3 PHY - RX registers */ 384a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 3859c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 3869c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 387cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 388cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 389cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 3909c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 3919c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 392cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 393a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 394cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 3959c7761a3SManu Gautam #define QSERDES_V3_RX_RX_TERM_BW 0x07c 396f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 397f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 3989c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 3999c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 4009c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 4019c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 4029c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 4039c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 4049c7761a3SManu Gautam #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 4059c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_ENABLES 0x100 4069c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_CNTRL 0x104 4079c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_LVL 0x108 4089c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 4099c7761a3SManu Gautam #define QSERDES_V3_RX_RX_BAND 0x110 4109c7761a3SManu Gautam #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 411f6721e5cSManu Gautam #define QSERDES_V3_RX_RX_MODE_00 0x164 41273d7ec89SMarc Gonzalez #define QSERDES_V3_RX_RX_MODE_01 0x168 4139c7761a3SManu Gautam 4149c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 4159c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 4169c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 4179c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 4189c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 4199c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 4209c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 4219c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 422cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 423cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 4249c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 4259c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 4269c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 4279c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 4289c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 4299c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 4309c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 4319c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 4329c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 4339c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 4349c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 4359c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 4369c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 4379c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 4389c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 4399c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 4409c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 4419c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 4429c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 4439c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 4449c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 4459c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 4469c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 4479c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 4489c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 4499c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 4509c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 4519c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 45273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 4539c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 4549c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 4559c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 4569c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 4579c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 4589c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 4599c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 4609c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 461cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 462cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 463cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 464cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 46573d7ec89SMarc Gonzalez #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 46673d7ec89SMarc Gonzalez #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 46773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 468cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 469cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 4709c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 47173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 47273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 473f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 474f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 4759c7761a3SManu Gautam 476ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 477ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 47873d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 47973d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 48073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 48173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 48273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 483ac0d2399SManu Gautam 4845c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 4855c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 4865c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 4875c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 4885c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 4895c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 4905c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 49152e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 49252e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 49352e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 49452e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 49552e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 49652e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 49752e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 4985c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 4995c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 5005c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 5015c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 5025c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 5035c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 5045c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 5055c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 5065c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 5075c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 5085c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 50952e013d0SStephen Boyd 5105c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 51152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 51252e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 51352e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 51452e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 51552e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 51652e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 51752e013d0SStephen Boyd 51852e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 51952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 52052e013d0SStephen Boyd 52152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 52252e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 52352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 52452e013d0SStephen Boyd 52552e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 52652e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 52752e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 52852e013d0SStephen Boyd 52952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 53052e013d0SStephen Boyd 531a88c85eeSVinod Koul /* Only for QMP V4 PHY - QSERDES COM registers */ 532aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BG_TIMER 0x00c 5339a24b929SJack Pham #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 5349a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER1 0x01c 5359a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER2 0x020 5369a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 5379a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 5389a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 5399a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 540aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 5416edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_ENABLE1 0x048 542aff188feSDmitry Baryshkov #define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c 5439a24b929SJack Pham #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 544a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_IVCO 0x058 545a88c85eeSVinod Koul #define QSERDES_V4_COM_CMN_IPTRIM 0x060 546a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 547a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 548a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 549a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 550a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 551a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 552a88c85eeSVinod Koul #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 553aff188feSDmitry Baryshkov #define QSERDES_V4_COM_RESETSM_CNTRL 0x09c 554a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 555*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8 556a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 557a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 558a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 559a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 560a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 561a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 5629a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 5639a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 5649a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 5659a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 5669a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 5679a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 568aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec 569aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 570*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 571*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 572aff188feSDmitry Baryshkov #define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 573a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 5749a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 5759a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 5769a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 5779a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 578a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 579aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_STATUS 0x140 5806edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_SELECT 0x154 581a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_SEL 0x158 582a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 583aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 5849a24b929SJack Pham #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 585aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORE_CLK_EN 0x174 586aff188feSDmitry Baryshkov #define QSERDES_V4_COM_C_READY_STATUS 0x178 587aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_CONFIG 0x17c 5889a24b929SJack Pham #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 589*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_CMN_MISC1 0x19c 590*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0 591*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_CMN_MODE 0x1a4 592*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8 593a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 594a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 595a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 596a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 597*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 598a88c85eeSVinod Koul 599a88c85eeSVinod Koul /* Only for QMP V4 PHY - TX registers */ 600aff188feSDmitry Baryshkov #define QSERDES_V4_TX_CLKBUF_ENABLE 0x08 601aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c 602aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_DRV_LVL 0x14 603aff188feSDmitry Baryshkov #define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c 604aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20 605aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_BAND 0x24 606aff188feSDmitry Baryshkov #define QSERDES_V4_TX_INTERFACE_SELECT 0x2c 6079a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 6089a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 6097b675ba1SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c 61090b65347SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 611aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54 612aff188feSDmitry Baryshkov #define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58 613aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_POL_INV 0x5c 614aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 615a88c85eeSVinod Koul #define QSERDES_V4_TX_LANE_MODE_1 0x84 61690b65347SJonathan Marek #define QSERDES_V4_TX_LANE_MODE_2 0x88 6179a24b929SJack Pham #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 618aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 619aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc 620a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 621a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC 622a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 623a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 624aff188feSDmitry Baryshkov #define QSERDES_V4_TX_VMODE_CTRL1 0xe8 6259a24b929SJack Pham #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 626a88c85eeSVinod Koul 627*be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - TX registers */ 628*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 629*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 630*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 631*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 632*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 633*be0ddb5dSManivannan Sadhasivam 634a88c85eeSVinod Koul /* Only for QMP V4 PHY - RX registers */ 635a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 636a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 637a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 638a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 639a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 6409a24b929SJack Pham #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 641a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 642a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 6439a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 6449a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 6459a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 6469a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 6479a24b929SJack Pham #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 6486edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 649a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 650a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 651a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_TERM_BW 0x080 6529a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 6539a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 6549a24b929SJack Pham #define QSERDES_V4_RX_GM_CAL 0x0dc 6556edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 656a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 657a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 658a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 659a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 660a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 661a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 6629a24b929SJack Pham #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 663a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 6646edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_SIGDET_ENABLES 0x118 665a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 666a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_LVL 0x120 667a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 668a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_BAND 0x128 669a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 670a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 671a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 672a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 673a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 674a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 675a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 676a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 677a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 678a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 679a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 680a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 681a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 682a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 683a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 6849a24b929SJack Pham #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 6859a24b929SJack Pham #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 686a88c85eeSVinod Koul #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 6879a24b929SJack Pham #define QSERDES_V4_RX_VTH_CODE 0x1c4 688a88c85eeSVinod Koul 689aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 690aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 691aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 692aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 693aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 694aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 695aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 696aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 697aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 698aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 699aff188feSDmitry Baryshkov 700*be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - RX registers */ 701*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 702*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 703*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 704*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_3 0x110 705*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 706*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 707*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 708*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 709*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 710*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 711*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 712*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 713*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 714*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 715*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 716*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 717*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 718*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 719*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 720*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 721*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 722*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 723*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 724*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 725*be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 726*be0ddb5dSManivannan Sadhasivam 7279a24b929SJack Pham /* Only for QMP V4 PHY - UFS PCS registers */ 72878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PHY_START 0x000 72978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 73078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_SW_RESET 0x008 73178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 73278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 73378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 73478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 73578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 73678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 73778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 73878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 73978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 74078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 74178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 74278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 74378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 74478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 74578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 74678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 74778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 748a88c85eeSVinod Koul 749909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 750909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 751909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 752909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 753909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 754909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 755909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 756909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 757909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 758909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 759909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 760909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 761909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 762909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 763909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 764909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 765909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 766909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 767909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 768909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 769909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 770909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 771909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 772909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 773909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 774909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 775909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 776909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 777909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 778909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 779909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 780909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 781909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 782909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 783909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 784909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 785909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 786909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 787909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 788909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 789909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 790909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 791909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 792909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 793909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 794909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 795909a5c78SBjorn Andersson 796909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 797909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 798909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 799909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 800909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 801909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 802909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 803909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 804909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 805909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 806909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 807909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 808909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 809909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 810909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 811909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 812909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 813909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 814909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 815909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 816909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 817909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 818909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 819909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 820909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 821909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 822909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 823909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 824909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 825909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 826909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 827909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 828909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 829909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 830909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 831909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 832909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 833909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 834909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 835909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 836909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 837909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 838909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 839909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 840909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 841909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 842909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 843909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 844909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 845909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 846909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 847909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 848909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 849909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 850909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 851909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 852909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 853909a5c78SBjorn Andersson 854909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 855909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 856909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 857909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 858909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 859909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 860909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 861909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 862909a5c78SBjorn Andersson 8639a24b929SJack Pham /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 8649a24b929SJack Pham #define QPHY_V4_PCS_SW_RESET 0x000 8659a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID0 0x004 8669a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID1 0x008 8679a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID2 0x00c 8689a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID3 0x010 8699a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS1 0x014 8709a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS2 0x018 8719a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS3 0x01c 8729a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS4 0x020 8739a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS5 0x024 8749a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS6 0x028 8759a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS7 0x02c 8769a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 8779a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 8789a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 8799a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 8809a24b929SJack Pham #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 8819a24b929SJack Pham #define QPHY_V4_PCS_START_CONTROL 0x044 8829a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 8839a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 8849a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 8859a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 8869a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 8879a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 8889a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 8899a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 8909a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 8919a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 8929a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 8939a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 8949a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 8959a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 8969a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 8979a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 8989a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 8999a24b929SJack Pham #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 9009a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 9019a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 9029a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL1 0x098 9039a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 9049a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 9059a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 9069a24b929SJack Pham #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 9079a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 9089a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 9099a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 9109a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 9119a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 9129a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 9139a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 9149a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 9159a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 9169a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 9179a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 9189a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 9199a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 9209a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 9219a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 9229a24b929SJack Pham #define QPHY_V4_PCS_BIST_CTRL 0x0e8 9239a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 9249a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 9259a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 9269a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 9279a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 9289a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT3 0x100 9299a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT4 0x104 9309a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT5 0x108 9319a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT6 0x10c 9329a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT7 0x110 9339a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT8 0x114 9349a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT9 0x118 9359a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT10 0x11c 9369a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT11 0x120 9379a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT12 0x124 9389a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT13 0x128 9399a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT14 0x12c 9409a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT15 0x130 9419a24b929SJack Pham #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 9429a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 9439a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 9449a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 9459a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 9469a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 9479a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 9489a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 9499a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 9509a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 9519a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 9529a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 9539a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 9549a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 9559a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 9569a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 9579a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 9589a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 9599a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 9609a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 9619a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 9629a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 9639a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 9649a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 9659a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 9669a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 9679a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 9689a24b929SJack Pham #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 9699a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 9709a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 9719a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 9729a24b929SJack Pham #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 9739a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 9749a24b929SJack Pham #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 9759a24b929SJack Pham #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 9769a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 9779a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 9789a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 9799a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 9809a24b929SJack Pham #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 9819a24b929SJack Pham #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 9829a24b929SJack Pham #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 9839a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 9849a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 9859a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 9869a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 9879a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 9889a24b929SJack Pham #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300 9899a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 9909a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 9919a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 9929a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 9939a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 9949a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 9959a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c 9969a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 9979a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 9989a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328 9999a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c 10009a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330 10019a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334 10029a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338 10039a24b929SJack Pham #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c 10049a24b929SJack Pham #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340 10059a24b929SJack Pham #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344 10069a24b929SJack Pham #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348 10079a24b929SJack Pham #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c 10089a24b929SJack Pham #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350 10099a24b929SJack Pham #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 10109a24b929SJack Pham #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 10119a24b929SJack Pham 1012*be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 1013*be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 1014*be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 1015*be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 1016*be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 1017*be0ddb5dSManivannan Sadhasivam 10187b675ba1SJonathan Marek /* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */ 10197b675ba1SJonathan Marek #define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618 10207b675ba1SJonathan Marek #define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638 10217b675ba1SJonathan Marek 10229a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 10239a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 10249a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 10259a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 10269a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 10279a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 10289a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 10299a24b929SJack Pham 10306edf7700SManivannan Sadhasivam /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 10316edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 10326edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 10336edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 10346edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 10356edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 10366edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 10376edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 10386edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 10396edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 10406edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 10416edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 10426edf7700SManivannan Sadhasivam 1043*be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 1044*be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 1045*be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 1046*be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 1047*be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 1048*be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 1049*be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 1050*be0ddb5dSManivannan Sadhasivam 1051920abc10SVinod Koul /* Only for QMP V5 PHY - QSERDES COM registers */ 1052920abc10SVinod Koul #define QSERDES_V5_COM_PLL_IVCO 0x058 1053920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 1054920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 1055920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c 1056920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 1057920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 1058920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 1059920abc10SVinod Koul #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 1060920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 1061920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac 1062920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 1063920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 1064920abc10SVinod Koul #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc 1065920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 1066920abc10SVinod Koul #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 1067920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c 1068920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 1069920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_SEL 0x158 1070920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c 1071920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 1072920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 1073920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 1074920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 1075920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 1076920abc10SVinod Koul 107710c744d4SJack Pham /* Only for QMP V5 PHY - TX registers */ 107810c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 107910c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38 108010c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c 108110c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40 108210c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_1 0x84 108310c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_2 0x88 108410c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_3 0x8c 108510c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_4 0x90 108610c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_5 0x94 108710c744d4SJack Pham #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4 108810c744d4SJack Pham #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0 108910c744d4SJack Pham #define QSERDES_V5_TX_PI_QEC_CTRL 0xe4 1090920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 1091920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 1092920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 1093920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 109410c744d4SJack Pham 109510c744d4SJack Pham /* Only for QMP V5 PHY - RX registers */ 109610c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 109710c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 109810c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 109910c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 110010c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 110110c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 110210c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 110310c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 110410c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c 110510c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 110610c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 110710c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 110810c744d4SJack Pham #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 110910c744d4SJack Pham #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 111010c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 111110c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 111210c744d4SJack Pham #define QSERDES_V5_RX_RX_TERM_BW 0x080 111310c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 111410c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 111510c744d4SJack Pham #define QSERDES_V5_RX_GM_CAL 0x0dc 111610c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 111710c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 111810c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 111910c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 112010c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 112110c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 112210c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 112310c744d4SJack Pham #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 112410c744d4SJack Pham #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 112510c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 112610c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c 112710c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_LVL 0x120 112810c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 112910c744d4SJack Pham #define QSERDES_V5_RX_RX_BAND 0x128 113010c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 113110c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 113210c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 113310c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 113410c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c 113510c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 113610c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 113710c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 113810c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c 113910c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 114010c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 114110c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 114210c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 114310c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 114410c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 114510c744d4SJack Pham #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 114610c744d4SJack Pham #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 114710c744d4SJack Pham #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 114810c744d4SJack Pham #define QSERDES_V5_RX_VTH_CODE 0x1b0 114910c744d4SJack Pham 1150920abc10SVinod Koul /* Only for QMP V5 PHY - UFS PCS registers */ 1151920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 1152920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 1153920abc10SVinod Koul #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 1154920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 1155920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 1156920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 1157920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 1158920abc10SVinod Koul #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 1159920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 1160920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 1161920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 1162920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 1163920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 1164920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 1165920abc10SVinod Koul #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 1166920abc10SVinod Koul 116710c744d4SJack Pham /* Only for QMP V5 PHY - USB3 have different offsets than V4 */ 116810c744d4SJack Pham #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x300 116910c744d4SJack Pham #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 117010c744d4SJack Pham #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 117110c744d4SJack Pham #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 117210c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 117310c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 117410c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 117510c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x31c 117610c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 117710c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 117810c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x328 117910c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x32c 118010c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x330 118110c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x334 118210c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x338 118310c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x33c 118410c744d4SJack Pham #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x340 118510c744d4SJack Pham #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x344 118610c744d4SJack Pham #define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x348 118710c744d4SJack Pham #define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x34c 118810c744d4SJack Pham #define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x350 118910c744d4SJack Pham #define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x354 119010c744d4SJack Pham #define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x358 119110c744d4SJack Pham #define QPHY_V5_PCS_USB3_TEST_CONTROL 0x35c 119210c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x360 119310c744d4SJack Pham 119410c744d4SJack Pham /* Only for QMP V5 PHY - UNI has 0x1000 offset for PCS_USB3 regs */ 119510c744d4SJack Pham #define QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x1018 119610c744d4SJack Pham #define QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x103c 119710c744d4SJack Pham 1198e2248617SManu Gautam #endif 1199