1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 99e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com.h" 109e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx.h" 119e1bae6dSDmitry Baryshkov 12a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v3.h" 13a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v3.h" 14a7fc833eSDmitry Baryshkov 1532d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v4.h" 1632d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v4.h" 1732d2cf53SDmitry Baryshkov 18f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v5.h" 19f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v5.h" 20f1f923adSDmitry Baryshkov 21147924ffSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-pll.h" 22520264dbSSelvam Sathappan Periakaruppan 235ae11aa4SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v2.h" 24e2248617SManu Gautam 2556a1fa09SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v3.h" 2656a1fa09SDmitry Baryshkov #include "phy-qcom-qmp-pcs-misc-v3.h" 2756a1fa09SDmitry Baryshkov 2841ad371fSDmitry Baryshkov #include "phy-qcom-qmp-pcs-v4.h" 2941ad371fSDmitry Baryshkov #include "phy-qcom-qmp-pcs-pcie-v4.h" 3041ad371fSDmitry Baryshkov #include "phy-qcom-qmp-pcs-usb-v4.h" 3141ad371fSDmitry Baryshkov #include "phy-qcom-qmp-pcs-ufs-v4.h" 3241ad371fSDmitry Baryshkov 33*b7a2f882SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v5.h" 34*b7a2f882SDmitry Baryshkov #include "phy-qcom-qmp-pcs-pcie-v5.h" 35*b7a2f882SDmitry Baryshkov #include "phy-qcom-qmp-pcs-usb-v5.h" 36*b7a2f882SDmitry Baryshkov #include "phy-qcom-qmp-pcs-ufs-v5.h" 37*b7a2f882SDmitry Baryshkov 389a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 399c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 409c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 419c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 429c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 439c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 449c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 459c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 469c7761a3SManu Gautam 47a7fc833eSDmitry Baryshkov /* QSERDES V3 COM bits */ 4852e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 4952e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 5052e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 5152e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 5252e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 5352e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 5452e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 559c7761a3SManu Gautam 56a7fc833eSDmitry Baryshkov /* QSERDES V3 TX bits */ 5752e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 5852e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 5952e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 6052e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 6152e013d0SStephen Boyd 625c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 635c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 645c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 655c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 665c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 675c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 685c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 6952e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 7052e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 7152e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 7252e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 7352e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 7452e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 7552e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 765c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 775c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 785c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 795c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 805c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 815c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 825c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 835c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 845c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 855c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 865c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 8752e013d0SStephen Boyd 885c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 8952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 9052e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 9152e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 9252e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 9352e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 9452e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 9552e013d0SStephen Boyd 9652e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 9752e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 9852e013d0SStephen Boyd 9952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 10052e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 10152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 10252e013d0SStephen Boyd 10352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 10452e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 10552e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 10652e013d0SStephen Boyd 10752e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 10852e013d0SStephen Boyd 109a88c85eeSVinod Koul 110be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - TX registers */ 111be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 112be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 113be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 114be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 115be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 116be0ddb5dSManivannan Sadhasivam 117aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 118aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 119aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 120aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 121aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 122aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 123aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 124aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 125aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 126aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 127aff188feSDmitry Baryshkov 128be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - RX registers */ 129be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 130be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 131be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 132be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_3 0x110 133be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 134be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 135be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 136be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 137be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 138be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 139be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 140be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 141be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 142be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 143be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 144be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 145be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 146be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 147be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 148be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 149be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 150be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 151be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 152be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 153be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 154be0ddb5dSManivannan Sadhasivam 155909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 156909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 157909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 158909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 159909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 160909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 161909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 162909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 163909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 164909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 165909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 166909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 167909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 168909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 169909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 170909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 171909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 172909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 173909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 174909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 175909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 176909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 177909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 178909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 179909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 180909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 181909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 182909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 183909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 184909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 185909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 186909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 187909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 188909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 189909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 190909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 191909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 192909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 193909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 194909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 195909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 196909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 197909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 198909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 199909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 200909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 201909a5c78SBjorn Andersson 202909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 203909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 204909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 205909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 206909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 207909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 208909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 209909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 210909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 211909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 212909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 213909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 214909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 215909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 216909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 217909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 218909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 219909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 220909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 221909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 222909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 223909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 224909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 225909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 226909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 227909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 228909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 229909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 230909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 231909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 232909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 233909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 234909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 235909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 236909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 237909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 238909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 239909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 240909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 241909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 242909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 243909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 244909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 245909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 246909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 247909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 248909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 249909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 250909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 251909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 252909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 253909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 254909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 255909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 256909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 257909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 258909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 259909a5c78SBjorn Andersson 260909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 261909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 262909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 263909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 264909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 265909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 266909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 267909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 268909a5c78SBjorn Andersson 269be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 270be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 271be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 272be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 273be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 274be0ddb5dSManivannan Sadhasivam 2759a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 2769a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 2779a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 2789a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 2799a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 2809a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 2819a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 2829a24b929SJack Pham 283be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 284be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 285be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 286be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 287be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 288be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 289be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 290be0ddb5dSManivannan Sadhasivam 2912c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - TX registers */ 2922c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 2932c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 2942c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 2952c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 2962c91bf6bSDmitry Baryshkov 2972c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - RX registers */ 2982c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 2992c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c 3002c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 3012c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c 3022c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 3032c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c 3042c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_3 0x090 3052c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 3062c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 3072c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 3082c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc 3092c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_GM_CAL 0x0ec 3102c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 3112c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 3122c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 3132c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c 3142c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 3152c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 3162c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c 3172c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 3182c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 3192c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 3202c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c 3212c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 3222c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 3232c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 3242c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c 3252c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 3262c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 3272c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 3282c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac 3292c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 3302c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 3312c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 3322c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 3332c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 3342c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc 3352c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 3362c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 3372c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 3382c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 3392c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 3402c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 3412c91bf6bSDmitry Baryshkov 3422c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - PCIe PCS registers */ 3432c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 3442c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 3452c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 3462c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 3472c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 3482c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 3492c91bf6bSDmitry Baryshkov 350e2248617SManu Gautam #endif 351