1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 9e2248617SManu Gautam /* Only for QMP V2 PHY - QSERDES COM registers */ 10e2248617SManu Gautam #define QSERDES_COM_BG_TIMER 0x00c 11e2248617SManu Gautam #define QSERDES_COM_SSC_EN_CENTER 0x010 12e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER1 0x014 13e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER2 0x018 14e2248617SManu Gautam #define QSERDES_COM_SSC_PER1 0x01c 15e2248617SManu Gautam #define QSERDES_COM_SSC_PER2 0x020 16e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE1 0x024 17e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE2 0x028 18e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 19e2248617SManu Gautam #define QSERDES_COM_CLK_ENABLE1 0x038 20e2248617SManu Gautam #define QSERDES_COM_SYS_CLK_CTRL 0x03c 21e2248617SManu Gautam #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 22e2248617SManu Gautam #define QSERDES_COM_PLL_IVCO 0x048 23e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 24e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 25e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 26e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 27e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 28e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 29e2248617SManu Gautam #define QSERDES_COM_BG_TRIM 0x070 30e2248617SManu Gautam #define QSERDES_COM_CLK_EP_DIV 0x074 31e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE0 0x078 32e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE1 0x07c 33e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 34e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 35e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 36e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 37e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 38e2248617SManu Gautam #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 39e2248617SManu Gautam #define QSERDES_COM_RESETSM_CNTRL 0x0b4 40e2248617SManu Gautam #define QSERDES_COM_RESTRIM_CTRL 0x0bc 41e2248617SManu Gautam #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 42e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_EN 0x0c8 43e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 44e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE0 0x0d0 45e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE1 0x0d4 46e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 47e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 48e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 49e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 50e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 51e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 52e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 53e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 54e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 55e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 56e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_CTRL 0x124 57e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_MAP 0x128 58e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 59e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 60e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 61e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 62e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 63e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 64e2248617SManu Gautam #define QSERDES_COM_BG_CTRL 0x170 65e2248617SManu Gautam #define QSERDES_COM_CLK_SELECT 0x174 66e2248617SManu Gautam #define QSERDES_COM_HSCLK_SEL 0x178 67e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV 0x184 68e2248617SManu Gautam #define QSERDES_COM_CORE_CLK_EN 0x18c 69e2248617SManu Gautam #define QSERDES_COM_C_READY_STATUS 0x190 70e2248617SManu Gautam #define QSERDES_COM_CMN_CONFIG 0x194 71e2248617SManu Gautam #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 72e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS0 0x1a0 73e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS1 0x1a4 74e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS2 0x1a8 75e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS3 0x1ac 76e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 77e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 78e2248617SManu Gautam 79e2248617SManu Gautam /* Only for QMP V2 PHY - TX registers */ 80afd55e6dSSivaprakash Murugesan #define QSERDES_TX_EMP_POST1_LVL 0x018 81afd55e6dSSivaprakash Murugesan #define QSERDES_TX_SLEW_CNTL 0x040 82e2248617SManu Gautam #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 83e2248617SManu Gautam #define QSERDES_TX_DEBUG_BUS_SEL 0x064 84e2248617SManu Gautam #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 85e2248617SManu Gautam #define QSERDES_TX_LANE_MODE 0x094 86e2248617SManu Gautam #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 87e2248617SManu Gautam 88e2248617SManu Gautam /* Only for QMP V2 PHY - RX registers */ 89e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 90e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN 0x01c 91e2248617SManu Gautam #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 92e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 93e2248617SManu Gautam #define QSERDES_RX_RX_TERM_BW 0x090 94e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 95e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 96e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 97e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 98e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 99e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 100e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 101e2248617SManu Gautam #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 102e2248617SManu Gautam #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 103e2248617SManu Gautam #define QSERDES_RX_SIGDET_ENABLES 0x110 104e2248617SManu Gautam #define QSERDES_RX_SIGDET_CNTRL 0x114 105e2248617SManu Gautam #define QSERDES_RX_SIGDET_LVL 0x118 106e2248617SManu Gautam #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 107e2248617SManu Gautam #define QSERDES_RX_RX_BAND 0x120 108e2248617SManu Gautam #define QSERDES_RX_RX_INTERFACE_MODE 0x12c 109e2248617SManu Gautam 110e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 111e2248617SManu Gautam #define QPHY_POWER_DOWN_CONTROL 0x04 112e2248617SManu Gautam #define QPHY_TXDEEMPH_M6DB_V0 0x24 113e2248617SManu Gautam #define QPHY_TXDEEMPH_M3P5DB_V0 0x28 114e2248617SManu Gautam #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 115e2248617SManu Gautam #define QPHY_RX_IDLE_DTCT_CNTRL 0x58 116e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG1 0x60 117e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG2 0x64 118e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG4 0x6c 119e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG1 0x80 120e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG2 0x84 121e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG3 0x88 122e2248617SManu Gautam #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 123e2248617SManu Gautam #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 124e2248617SManu Gautam #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 125e2248617SManu Gautam #define QPHY_OSC_DTCT_ACTIONS 0x1AC 126e2248617SManu Gautam #define QPHY_RX_SIGDET_LVL 0x1D8 127e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC 128e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 129e2248617SManu Gautam 1309a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 1319c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 1329c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 1339c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 1349c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 1359c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 1369c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 1379c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 1389c7761a3SManu Gautam 1399c7761a3SManu Gautam /* Only for QMP V3 PHY - QSERDES COM registers */ 14052e013d0SStephen Boyd #define QSERDES_V3_COM_ATB_SEL1 0x000 14152e013d0SStephen Boyd #define QSERDES_V3_COM_ATB_SEL2 0x004 14252e013d0SStephen Boyd #define QSERDES_V3_COM_FREQ_UPDATE 0x008 1439c7761a3SManu Gautam #define QSERDES_V3_COM_BG_TIMER 0x00c 1449c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 1459c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 1469c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 1479c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER1 0x01c 1489c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER2 0x020 1499c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 1509c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 1519c7761a3SManu Gautam #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 15252e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 15352e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 15452e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 15552e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 15652e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 15752e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 15852e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 1599c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_ENABLE1 0x038 1609c7761a3SManu Gautam #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 1619c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 1629c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_IVCO 0x048 1639c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 1649c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 1659c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 1669c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 1679c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 1689c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 1699c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 1709c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 1719c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 1729c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 1739c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 1749c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 1759c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 1769c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 1779c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 1789c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 1799c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 1809c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 1819c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 1829c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 1839c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 1849c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 1859c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 1869c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 1879c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 1889c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 189a51969faSJeffrey Hugo #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 1909c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 1919c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 1929c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 1939c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 1949c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 1959c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 1969c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 1979c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 1989c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 1999c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 200cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 201cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 2029c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 2039c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 2049c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_SELECT 0x138 2059c7761a3SManu Gautam #define QSERDES_V3_COM_HSCLK_SEL 0x13c 2069c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 2079c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 2089c7761a3SManu Gautam #define QSERDES_V3_COM_CORE_CLK_EN 0x154 2099c7761a3SManu Gautam #define QSERDES_V3_COM_C_READY_STATUS 0x158 2109c7761a3SManu Gautam #define QSERDES_V3_COM_CMN_CONFIG 0x15c 2119c7761a3SManu Gautam #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 2129c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS0 0x168 2139c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 2149c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS2 0x170 2159c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS3 0x174 2169c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 217a51969faSJeffrey Hugo #define QSERDES_V3_COM_CMN_MODE 0x184 2189c7761a3SManu Gautam 2199c7761a3SManu Gautam /* Only for QMP V3 PHY - TX registers */ 22052e013d0SStephen Boyd #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 22152e013d0SStephen Boyd #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 22252e013d0SStephen Boyd #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c 22352e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 22452e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 22552e013d0SStephen Boyd 22652e013d0SStephen Boyd #define QSERDES_V3_TX_TX_DRV_LVL 0x01c 22752e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 22852e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 22952e013d0SStephen Boyd 23052e013d0SStephen Boyd #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 23152e013d0SStephen Boyd #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 23252e013d0SStephen Boyd 23352e013d0SStephen Boyd #define QSERDES_V3_TX_TX_BAND 0x02c 23452e013d0SStephen Boyd #define QSERDES_V3_TX_SLEW_CNTL 0x030 23552e013d0SStephen Boyd #define QSERDES_V3_TX_INTERFACE_SELECT 0x034 23652e013d0SStephen Boyd #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c 23752e013d0SStephen Boyd #define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 2389c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 2399c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 2409c7761a3SManu Gautam #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 24152e013d0SStephen Boyd #define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c 2429c7761a3SManu Gautam #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 24352e013d0SStephen Boyd #define QSERDES_V3_TX_TX_POL_INV 0x064 24452e013d0SStephen Boyd #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 2459c7761a3SManu Gautam #define QSERDES_V3_TX_LANE_MODE_1 0x08c 2469c7761a3SManu Gautam #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 24752e013d0SStephen Boyd #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 24852e013d0SStephen Boyd #define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 24952e013d0SStephen Boyd #define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 2509c7761a3SManu Gautam 2519c7761a3SManu Gautam /* Only for QMP V3 PHY - RX registers */ 252a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 2539c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 2549c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 255cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 256cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 257cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 2589c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 2599c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 260cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 261a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 262cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 2639c7761a3SManu Gautam #define QSERDES_V3_RX_RX_TERM_BW 0x07c 264f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 265f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 2669c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 2679c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 2689c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 2699c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 2709c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 2719c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 2729c7761a3SManu Gautam #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 2739c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_ENABLES 0x100 2749c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_CNTRL 0x104 2759c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_LVL 0x108 2769c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 2779c7761a3SManu Gautam #define QSERDES_V3_RX_RX_BAND 0x110 2789c7761a3SManu Gautam #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 279f6721e5cSManu Gautam #define QSERDES_V3_RX_RX_MODE_00 0x164 28073d7ec89SMarc Gonzalez #define QSERDES_V3_RX_RX_MODE_01 0x168 2819c7761a3SManu Gautam 2829c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 2839c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 2849c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 2859c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 2869c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 2879c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 2889c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 2899c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 290cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 291cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 2929c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 2939c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 2949c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 2959c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 2969c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 2979c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 2989c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 2999c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 3009c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 3019c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 3029c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 3039c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 3049c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 3059c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 3069c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 3079c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 3089c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 3099c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 3109c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 3119c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 3129c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 3139c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 3149c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 3159c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 3169c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 3179c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 3189c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 3199c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 32073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 3219c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 3229c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 3239c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 3249c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 3259c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 3269c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 3279c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 3289c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 329cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 330cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 331cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 332cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 33373d7ec89SMarc Gonzalez #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 33473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 33573d7ec89SMarc Gonzalez #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 336cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 337cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 3389c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 33973d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 34073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 341f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 342f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 3439c7761a3SManu Gautam 344ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 345ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 34673d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 34773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 34873d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 34973d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 35073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 351ac0d2399SManu Gautam 3525c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 3535c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 3545c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 3555c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 3565c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 3575c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 3585c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 35952e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 36052e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 36152e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 36252e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 36352e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 36452e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 36552e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 3665c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 3675c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 3685c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 3695c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 3705c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 3715c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 3725c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 3735c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 3745c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 3755c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 3765c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 37752e013d0SStephen Boyd 3785c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 37952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 38052e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 38152e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 38252e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 38352e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 38452e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 38552e013d0SStephen Boyd 38652e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 38752e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 38852e013d0SStephen Boyd 38952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 39052e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 39152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 39252e013d0SStephen Boyd 39352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 39452e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 39552e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 39652e013d0SStephen Boyd 39752e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 39852e013d0SStephen Boyd 399a88c85eeSVinod Koul /* Only for QMP V4 PHY - QSERDES COM registers */ 400*aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BG_TIMER 0x00c 4019a24b929SJack Pham #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 4029a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER1 0x01c 4039a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER2 0x020 4049a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 4059a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 4069a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 4079a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 408*aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 4096edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_ENABLE1 0x048 410*aff188feSDmitry Baryshkov #define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c 4119a24b929SJack Pham #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 412a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_IVCO 0x058 413a88c85eeSVinod Koul #define QSERDES_V4_COM_CMN_IPTRIM 0x060 414a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 415a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 416a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 417a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 418a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 419a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 420a88c85eeSVinod Koul #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 421*aff188feSDmitry Baryshkov #define QSERDES_V4_COM_RESETSM_CNTRL 0x09c 422a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 423a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 424a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 425a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 426a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 427a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 428a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 4299a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 4309a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 4319a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 4329a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 4339a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 4349a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 435*aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec 436*aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 437*aff188feSDmitry Baryshkov #define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 438a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 4399a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 4409a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 4419a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 4429a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 443a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 444*aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_STATUS 0x140 4456edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_SELECT 0x154 446a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_SEL 0x158 447a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 448*aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 4499a24b929SJack Pham #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 450*aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORE_CLK_EN 0x174 451*aff188feSDmitry Baryshkov #define QSERDES_V4_COM_C_READY_STATUS 0x178 452*aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_CONFIG 0x17c 4539a24b929SJack Pham #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 454a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 455a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 456a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 457a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 458a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 459a88c85eeSVinod Koul 460a88c85eeSVinod Koul /* Only for QMP V4 PHY - TX registers */ 461*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_CLKBUF_ENABLE 0x08 462*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c 463*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_DRV_LVL 0x14 464*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c 465*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20 466*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_BAND 0x24 467*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_INTERFACE_SELECT 0x2c 4689a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 4699a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 4707b675ba1SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c 47190b65347SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 472*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54 473*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58 474*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_POL_INV 0x5c 475*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 476a88c85eeSVinod Koul #define QSERDES_V4_TX_LANE_MODE_1 0x84 47790b65347SJonathan Marek #define QSERDES_V4_TX_LANE_MODE_2 0x88 4789a24b929SJack Pham #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 479*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 480*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc 481a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 482a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC 483a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 484a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 485*aff188feSDmitry Baryshkov #define QSERDES_V4_TX_VMODE_CTRL1 0xe8 4869a24b929SJack Pham #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 487a88c85eeSVinod Koul 488a88c85eeSVinod Koul /* Only for QMP V4 PHY - RX registers */ 489a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 490a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 491a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 492a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 493a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 4949a24b929SJack Pham #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 495a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 496a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 4979a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 4989a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 4999a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 5009a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 5019a24b929SJack Pham #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 5026edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 503a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 504a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 505a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_TERM_BW 0x080 5069a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 5079a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 5089a24b929SJack Pham #define QSERDES_V4_RX_GM_CAL 0x0dc 5096edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 510a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 511a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 512a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 513a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 514a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 515a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 5169a24b929SJack Pham #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 517a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 5186edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_SIGDET_ENABLES 0x118 519a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 520a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_LVL 0x120 521a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 522a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_BAND 0x128 523a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 524a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 525a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 526a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 527a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 528a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 529a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 530a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 531a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 532a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 533a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 534a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 535a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 536a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 537a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 5389a24b929SJack Pham #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 5399a24b929SJack Pham #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 540a88c85eeSVinod Koul #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 5419a24b929SJack Pham #define QSERDES_V4_RX_VTH_CODE 0x1c4 542a88c85eeSVinod Koul 543*aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 544*aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 545*aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 546*aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 547*aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 548*aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 549*aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 550*aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 551*aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 552*aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 553*aff188feSDmitry Baryshkov 5549a24b929SJack Pham /* Only for QMP V4 PHY - UFS PCS registers */ 55578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PHY_START 0x000 55678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 55778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_SW_RESET 0x008 55878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 55978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 56078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 56178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 56278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 56378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 56478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 56578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 56678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 56778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 56878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 56978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 57078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 57178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 57278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 57378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 57478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 575a88c85eeSVinod Koul 576909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 577909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 578909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 579909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 580909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 581909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 582909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 583909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 584909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 585909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 586909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 587909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 588909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 589909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 590909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 591909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 592909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 593909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 594909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 595909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 596909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 597909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 598909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 599909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 600909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 601909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 602909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 603909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 604909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 605909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 606909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 607909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 608909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 609909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 610909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 611909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 612909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 613909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 614909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 615909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 616909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 617909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 618909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 619909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 620909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 621909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 622909a5c78SBjorn Andersson 623909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 624909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 625909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 626909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 627909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 628909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 629909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 630909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 631909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 632909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 633909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 634909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 635909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 636909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 637909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 638909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 639909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 640909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 641909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 642909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 643909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 644909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 645909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 646909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 647909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 648909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 649909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 650909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 651909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 652909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 653909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 654909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 655909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 656909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 657909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 658909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 659909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 660909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 661909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 662909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 663909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 664909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 665909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 666909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 667909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 668909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 669909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 670909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 671909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 672909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 673909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 674909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 675909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 676909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 677909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 678909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 679909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 680909a5c78SBjorn Andersson 681909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 682909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 683909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 684909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 685909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 686909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 687909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 688909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 689909a5c78SBjorn Andersson 6909a24b929SJack Pham /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 6919a24b929SJack Pham #define QPHY_V4_PCS_SW_RESET 0x000 6929a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID0 0x004 6939a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID1 0x008 6949a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID2 0x00c 6959a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID3 0x010 6969a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS1 0x014 6979a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS2 0x018 6989a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS3 0x01c 6999a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS4 0x020 7009a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS5 0x024 7019a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS6 0x028 7029a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS7 0x02c 7039a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 7049a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 7059a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 7069a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 7079a24b929SJack Pham #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 7089a24b929SJack Pham #define QPHY_V4_PCS_START_CONTROL 0x044 7099a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 7109a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 7119a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 7129a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 7139a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 7149a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 7159a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 7169a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 7179a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 7189a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 7199a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 7209a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 7219a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 7229a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 7239a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 7249a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 7259a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 7269a24b929SJack Pham #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 7279a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 7289a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 7299a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL1 0x098 7309a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 7319a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 7329a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 7339a24b929SJack Pham #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 7349a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 7359a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 7369a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 7379a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 7389a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 7399a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 7409a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 7419a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 7429a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 7439a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 7449a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 7459a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 7469a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 7479a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 7489a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 7499a24b929SJack Pham #define QPHY_V4_PCS_BIST_CTRL 0x0e8 7509a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 7519a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 7529a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 7539a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 7549a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 7559a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT3 0x100 7569a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT4 0x104 7579a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT5 0x108 7589a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT6 0x10c 7599a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT7 0x110 7609a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT8 0x114 7619a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT9 0x118 7629a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT10 0x11c 7639a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT11 0x120 7649a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT12 0x124 7659a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT13 0x128 7669a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT14 0x12c 7679a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT15 0x130 7689a24b929SJack Pham #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 7699a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 7709a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 7719a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 7729a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 7739a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 7749a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 7759a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 7769a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 7779a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 7789a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 7799a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 7809a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 7819a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 7829a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 7839a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 7849a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 7859a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 7869a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 7879a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 7889a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 7899a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 7909a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 7919a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 7929a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 7939a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 7949a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 7959a24b929SJack Pham #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 7969a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 7979a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 7989a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 7999a24b929SJack Pham #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 8009a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 8019a24b929SJack Pham #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 8029a24b929SJack Pham #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 8039a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 8049a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 8059a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 8069a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 8079a24b929SJack Pham #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 8089a24b929SJack Pham #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 8099a24b929SJack Pham #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 8109a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 8119a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 8129a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 8139a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 8149a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 8159a24b929SJack Pham #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300 8169a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 8179a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 8189a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 8199a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 8209a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 8219a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 8229a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c 8239a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 8249a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 8259a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328 8269a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c 8279a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330 8289a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334 8299a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338 8309a24b929SJack Pham #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c 8319a24b929SJack Pham #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340 8329a24b929SJack Pham #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344 8339a24b929SJack Pham #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348 8349a24b929SJack Pham #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c 8359a24b929SJack Pham #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350 8369a24b929SJack Pham #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 8379a24b929SJack Pham #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 8389a24b929SJack Pham 8397b675ba1SJonathan Marek /* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */ 8407b675ba1SJonathan Marek #define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618 8417b675ba1SJonathan Marek #define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638 8427b675ba1SJonathan Marek 8439a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 8449a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 8459a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 8469a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 8479a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 8489a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 8499a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 8509a24b929SJack Pham 8516edf7700SManivannan Sadhasivam /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 8526edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 8536edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 8546edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 8556edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 8566edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 8576edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 8586edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 8596edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 8606edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 8616edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 8626edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 8636edf7700SManivannan Sadhasivam 864920abc10SVinod Koul /* Only for QMP V5 PHY - QSERDES COM registers */ 865920abc10SVinod Koul #define QSERDES_V5_COM_PLL_IVCO 0x058 866920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 867920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 868920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c 869920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 870920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 871920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 872920abc10SVinod Koul #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 873920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 874920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac 875920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 876920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 877920abc10SVinod Koul #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc 878920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 879920abc10SVinod Koul #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 880920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c 881920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 882920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_SEL 0x158 883920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c 884920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 885920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 886920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 887920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 888920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 889920abc10SVinod Koul 89010c744d4SJack Pham /* Only for QMP V5 PHY - TX registers */ 89110c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 89210c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38 89310c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c 89410c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40 89510c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_1 0x84 89610c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_2 0x88 89710c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_3 0x8c 89810c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_4 0x90 89910c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_5 0x94 90010c744d4SJack Pham #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4 90110c744d4SJack Pham #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0 90210c744d4SJack Pham #define QSERDES_V5_TX_PI_QEC_CTRL 0xe4 903920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 904920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 905920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 906920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 90710c744d4SJack Pham 90810c744d4SJack Pham /* Only for QMP V5 PHY - RX registers */ 90910c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 91010c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 91110c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 91210c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 91310c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 91410c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 91510c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 91610c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 91710c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c 91810c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 91910c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 92010c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 92110c744d4SJack Pham #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 92210c744d4SJack Pham #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 92310c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 92410c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 92510c744d4SJack Pham #define QSERDES_V5_RX_RX_TERM_BW 0x080 92610c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 92710c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 92810c744d4SJack Pham #define QSERDES_V5_RX_GM_CAL 0x0dc 92910c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 93010c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 93110c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 93210c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 93310c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 93410c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 93510c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 93610c744d4SJack Pham #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 93710c744d4SJack Pham #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 93810c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 93910c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c 94010c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_LVL 0x120 94110c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 94210c744d4SJack Pham #define QSERDES_V5_RX_RX_BAND 0x128 94310c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 94410c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 94510c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 94610c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 94710c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c 94810c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 94910c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 95010c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 95110c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c 95210c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 95310c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 95410c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 95510c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 95610c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 95710c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 95810c744d4SJack Pham #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 95910c744d4SJack Pham #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 96010c744d4SJack Pham #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 96110c744d4SJack Pham #define QSERDES_V5_RX_VTH_CODE 0x1b0 96210c744d4SJack Pham 963920abc10SVinod Koul /* Only for QMP V5 PHY - UFS PCS registers */ 964920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 965920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 966920abc10SVinod Koul #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 967920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 968920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 969920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 970920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 971920abc10SVinod Koul #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 972920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 973920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 974920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 975920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 976920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 977920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 978920abc10SVinod Koul #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 979920abc10SVinod Koul 98010c744d4SJack Pham /* Only for QMP V5 PHY - USB3 have different offsets than V4 */ 98110c744d4SJack Pham #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x300 98210c744d4SJack Pham #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 98310c744d4SJack Pham #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 98410c744d4SJack Pham #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 98510c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 98610c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 98710c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 98810c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x31c 98910c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 99010c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 99110c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x328 99210c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x32c 99310c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x330 99410c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x334 99510c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x338 99610c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x33c 99710c744d4SJack Pham #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x340 99810c744d4SJack Pham #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x344 99910c744d4SJack Pham #define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x348 100010c744d4SJack Pham #define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x34c 100110c744d4SJack Pham #define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x350 100210c744d4SJack Pham #define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x354 100310c744d4SJack Pham #define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x358 100410c744d4SJack Pham #define QPHY_V5_PCS_USB3_TEST_CONTROL 0x35c 100510c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x360 100610c744d4SJack Pham 100710c744d4SJack Pham /* Only for QMP V5 PHY - UNI has 0x1000 offset for PCS_USB3 regs */ 100810c744d4SJack Pham #define QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x1018 100910c744d4SJack Pham #define QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x103c 101010c744d4SJack Pham 1011e2248617SManu Gautam #endif 1012