1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 9e2248617SManu Gautam /* Only for QMP V2 PHY - QSERDES COM registers */ 10e2248617SManu Gautam #define QSERDES_COM_BG_TIMER 0x00c 11e2248617SManu Gautam #define QSERDES_COM_SSC_EN_CENTER 0x010 12e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER1 0x014 13e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER2 0x018 14e2248617SManu Gautam #define QSERDES_COM_SSC_PER1 0x01c 15e2248617SManu Gautam #define QSERDES_COM_SSC_PER2 0x020 16e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE1 0x024 17e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE2 0x028 18e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 19e2248617SManu Gautam #define QSERDES_COM_CLK_ENABLE1 0x038 20e2248617SManu Gautam #define QSERDES_COM_SYS_CLK_CTRL 0x03c 21e2248617SManu Gautam #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 22e2248617SManu Gautam #define QSERDES_COM_PLL_IVCO 0x048 23e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 24e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 25e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 26e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 27e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 28e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 29e2248617SManu Gautam #define QSERDES_COM_BG_TRIM 0x070 30e2248617SManu Gautam #define QSERDES_COM_CLK_EP_DIV 0x074 31e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE0 0x078 32e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE1 0x07c 33e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 34e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 35e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 36e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 37e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 38e2248617SManu Gautam #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 39e2248617SManu Gautam #define QSERDES_COM_RESETSM_CNTRL 0x0b4 40e2248617SManu Gautam #define QSERDES_COM_RESTRIM_CTRL 0x0bc 41e2248617SManu Gautam #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 42e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_EN 0x0c8 43e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 44e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE0 0x0d0 45e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE1 0x0d4 46e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 47e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 48e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 49e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 50e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 51e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 52e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 53e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 54e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 55e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 56e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_CTRL 0x124 57e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_MAP 0x128 58e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 59e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 60e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 61e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 62e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 63e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 64e2248617SManu Gautam #define QSERDES_COM_BG_CTRL 0x170 65e2248617SManu Gautam #define QSERDES_COM_CLK_SELECT 0x174 66e2248617SManu Gautam #define QSERDES_COM_HSCLK_SEL 0x178 67e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV 0x184 68e2248617SManu Gautam #define QSERDES_COM_CORE_CLK_EN 0x18c 69e2248617SManu Gautam #define QSERDES_COM_C_READY_STATUS 0x190 70e2248617SManu Gautam #define QSERDES_COM_CMN_CONFIG 0x194 71e2248617SManu Gautam #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 72e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS0 0x1a0 73e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS1 0x1a4 74e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS2 0x1a8 75e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS3 0x1ac 76e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 77e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 78e2248617SManu Gautam 79e2248617SManu Gautam /* Only for QMP V2 PHY - TX registers */ 80afd55e6dSSivaprakash Murugesan #define QSERDES_TX_EMP_POST1_LVL 0x018 81afd55e6dSSivaprakash Murugesan #define QSERDES_TX_SLEW_CNTL 0x040 82e2248617SManu Gautam #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 83e2248617SManu Gautam #define QSERDES_TX_DEBUG_BUS_SEL 0x064 84e2248617SManu Gautam #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 85e2248617SManu Gautam #define QSERDES_TX_LANE_MODE 0x094 86e2248617SManu Gautam #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 87e2248617SManu Gautam 88e2248617SManu Gautam /* Only for QMP V2 PHY - RX registers */ 89e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 90e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN 0x01c 91e2248617SManu Gautam #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 92e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 93e2248617SManu Gautam #define QSERDES_RX_RX_TERM_BW 0x090 94e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 95e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 96e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 97e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 98e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 99e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 100e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 101e2248617SManu Gautam #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 102e2248617SManu Gautam #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 103e2248617SManu Gautam #define QSERDES_RX_SIGDET_ENABLES 0x110 104e2248617SManu Gautam #define QSERDES_RX_SIGDET_CNTRL 0x114 105e2248617SManu Gautam #define QSERDES_RX_SIGDET_LVL 0x118 106e2248617SManu Gautam #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 107e2248617SManu Gautam #define QSERDES_RX_RX_BAND 0x120 108e2248617SManu Gautam #define QSERDES_RX_RX_INTERFACE_MODE 0x12c 109e2248617SManu Gautam 110e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 111e2248617SManu Gautam #define QPHY_POWER_DOWN_CONTROL 0x04 112e2248617SManu Gautam #define QPHY_TXDEEMPH_M6DB_V0 0x24 113e2248617SManu Gautam #define QPHY_TXDEEMPH_M3P5DB_V0 0x28 114e2248617SManu Gautam #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 115e2248617SManu Gautam #define QPHY_RX_IDLE_DTCT_CNTRL 0x58 116e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG1 0x60 117e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG2 0x64 118e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG4 0x6c 119e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG1 0x80 120e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG2 0x84 121e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG3 0x88 122e2248617SManu Gautam #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 123e2248617SManu Gautam #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 124e2248617SManu Gautam #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 125e2248617SManu Gautam #define QPHY_OSC_DTCT_ACTIONS 0x1AC 126e2248617SManu Gautam #define QPHY_RX_SIGDET_LVL 0x1D8 127e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC 128e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 129e2248617SManu Gautam 1309a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 1319c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 1329c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 1339c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 1349c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 1359c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 1369c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 1379c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 1389c7761a3SManu Gautam 1399c7761a3SManu Gautam /* Only for QMP V3 PHY - QSERDES COM registers */ 1409c7761a3SManu Gautam #define QSERDES_V3_COM_BG_TIMER 0x00c 1419c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 1429c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 1439c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 1449c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER1 0x01c 1459c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER2 0x020 1469c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 1479c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 1489c7761a3SManu Gautam #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 1499c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_ENABLE1 0x038 1509c7761a3SManu Gautam #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 1519c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 1529c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_IVCO 0x048 1539c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 1549c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 1559c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 1569c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 1579c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 1589c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 1599c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 1609c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 1619c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 1629c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 1639c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 1649c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 1659c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 1669c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 1679c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 1689c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 1699c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 1709c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 1719c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 1729c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 1739c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 1749c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 1759c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 1769c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 1779c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 1789c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 179a51969faSJeffrey Hugo #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 1809c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 1819c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 1829c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 1839c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 1849c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 1859c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 1869c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 1879c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 1889c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 1899c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 190cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 191cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 1929c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 1939c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 1949c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_SELECT 0x138 1959c7761a3SManu Gautam #define QSERDES_V3_COM_HSCLK_SEL 0x13c 1969c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 1979c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 1989c7761a3SManu Gautam #define QSERDES_V3_COM_CORE_CLK_EN 0x154 1999c7761a3SManu Gautam #define QSERDES_V3_COM_C_READY_STATUS 0x158 2009c7761a3SManu Gautam #define QSERDES_V3_COM_CMN_CONFIG 0x15c 2019c7761a3SManu Gautam #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 2029c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS0 0x168 2039c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 2049c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS2 0x170 2059c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS3 0x174 2069c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 207a51969faSJeffrey Hugo #define QSERDES_V3_COM_CMN_MODE 0x184 2089c7761a3SManu Gautam 2099c7761a3SManu Gautam /* Only for QMP V3 PHY - TX registers */ 2109c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 2119c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 2129c7761a3SManu Gautam #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 2139c7761a3SManu Gautam #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 2149c7761a3SManu Gautam #define QSERDES_V3_TX_LANE_MODE_1 0x08c 2159c7761a3SManu Gautam #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 2169c7761a3SManu Gautam 2179c7761a3SManu Gautam /* Only for QMP V3 PHY - RX registers */ 218a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 2199c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 2209c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 221cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 222cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 223cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 2249c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 2259c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 226cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 227a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 228cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 2299c7761a3SManu Gautam #define QSERDES_V3_RX_RX_TERM_BW 0x07c 230f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 231f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 2329c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 2339c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 2349c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 2359c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 2369c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 2379c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 2389c7761a3SManu Gautam #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 2399c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_ENABLES 0x100 2409c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_CNTRL 0x104 2419c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_LVL 0x108 2429c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 2439c7761a3SManu Gautam #define QSERDES_V3_RX_RX_BAND 0x110 2449c7761a3SManu Gautam #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 245f6721e5cSManu Gautam #define QSERDES_V3_RX_RX_MODE_00 0x164 24673d7ec89SMarc Gonzalez #define QSERDES_V3_RX_RX_MODE_01 0x168 2479c7761a3SManu Gautam 2489c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 2499c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 2509c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 2519c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 2529c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 2539c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 2549c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 2559c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 256cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 257cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 2589c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 2599c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 2609c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 2619c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 2629c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 2639c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 2649c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 2659c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 2669c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 2679c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 2689c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 2699c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 2709c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 2719c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 2729c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 2739c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 2749c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 2759c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 2769c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 2779c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 2789c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 2799c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 2809c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 2819c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 2829c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 2839c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 2849c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 2859c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 28673d7ec89SMarc Gonzalez #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 2879c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 2889c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 2899c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 2909c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 2919c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 2929c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 2939c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 2949c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 295cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 296cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 297cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 298cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 29973d7ec89SMarc Gonzalez #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 30073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 30173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 302cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 303cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 3049c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 30573d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 30673d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 307f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 308f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 3099c7761a3SManu Gautam 310ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 311ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 31273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 31373d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 31473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 31573d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 31673d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 317ac0d2399SManu Gautam 318a88c85eeSVinod Koul /* Only for QMP V4 PHY - QSERDES COM registers */ 3199a24b929SJack Pham #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 3209a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER1 0x01c 3219a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER2 0x020 3229a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 3239a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 3249a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 3259a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 3269a24b929SJack Pham #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 327a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_IVCO 0x058 328a88c85eeSVinod Koul #define QSERDES_V4_COM_CMN_IPTRIM 0x060 329a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 330a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 331a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 332a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 333a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 334a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 335a88c85eeSVinod Koul #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 336a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 337a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 338a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 339a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 340a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 341a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 342a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 3439a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 3449a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 3459a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 3469a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 3479a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 3489a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 349a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 3509a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 3519a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 3529a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 3539a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 354a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 355a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_SEL 0x158 356a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 3579a24b929SJack Pham #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 3589a24b929SJack Pham #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 359a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 360a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 361a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 362a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 363a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 364a88c85eeSVinod Koul 365a88c85eeSVinod Koul /* Only for QMP V4 PHY - TX registers */ 3669a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 3679a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 3687b675ba1SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c 36990b65347SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 370a88c85eeSVinod Koul #define QSERDES_V4_TX_LANE_MODE_1 0x84 37190b65347SJonathan Marek #define QSERDES_V4_TX_LANE_MODE_2 0x88 3729a24b929SJack Pham #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 373a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 374a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC 375a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 376a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 377a88c85eeSVinod Koul #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 3789a24b929SJack Pham #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 379a88c85eeSVinod Koul 380a88c85eeSVinod Koul /* Only for QMP V4 PHY - RX registers */ 381a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 382a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 383a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 384a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 385a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 3869a24b929SJack Pham #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 387a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 388a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 3899a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 3909a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 3919a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 3929a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 3939a24b929SJack Pham #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 394a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 395a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 396a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_TERM_BW 0x080 3979a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 3989a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 3999a24b929SJack Pham #define QSERDES_V4_RX_GM_CAL 0x0dc 400a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 401a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 402a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 403a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 404a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 405a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 4069a24b929SJack Pham #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 407a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 408a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 409a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_LVL 0x120 410a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 411a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_BAND 0x128 412a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 413a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 414a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 415a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 416a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 417a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 418a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 419a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 420a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 421a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 422a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 423a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 424a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 425a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 426a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 4279a24b929SJack Pham #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 4289a24b929SJack Pham #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 429a88c85eeSVinod Koul #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 4309a24b929SJack Pham #define QSERDES_V4_RX_VTH_CODE 0x1c4 431a88c85eeSVinod Koul 4329a24b929SJack Pham /* Only for QMP V4 PHY - UFS PCS registers */ 43378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PHY_START 0x000 43478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 43578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_SW_RESET 0x008 43678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 43778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 43878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 43978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 44078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 44178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 44278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 44378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 44478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 44578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 44678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 44778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 44878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 44978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 45078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 45178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 45278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 453a88c85eeSVinod Koul 454909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 455909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 456909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 457909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 458909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 459909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 460909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 461909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 462909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 463909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 464909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 465909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 466909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 467909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 468909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 469909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 470909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 471909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 472909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 473909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 474909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 475909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 476909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 477909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 478909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 479909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 480909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 481909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 482909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 483909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 484909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 485909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 486909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 487909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 488909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 489909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 490909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 491909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 492909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 493909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 494909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 495909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 496909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 497909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 498909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 499909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 500909a5c78SBjorn Andersson 501909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 502909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 503909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 504909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 505909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 506909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 507909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 508909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 509909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 510909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 511909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 512909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 513909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 514909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 515909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 516909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 517909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 518909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 519909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 520909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 521909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 522909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 523909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 524909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 525909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 526909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 527909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 528909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 529909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 530909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 531909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 532909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 533909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 534909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 535909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 536909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 537909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 538909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 539909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 540909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 541909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 542909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 543909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 544909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 545909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 546909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 547909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 548909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 549909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 550909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 551909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 552909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 553909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 554909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 555909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 556909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 557909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 558909a5c78SBjorn Andersson 559909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 560909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 561909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 562909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 563909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 564909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 565909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 566909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 567909a5c78SBjorn Andersson 5689a24b929SJack Pham /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 5699a24b929SJack Pham #define QPHY_V4_PCS_SW_RESET 0x000 5709a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID0 0x004 5719a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID1 0x008 5729a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID2 0x00c 5739a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID3 0x010 5749a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS1 0x014 5759a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS2 0x018 5769a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS3 0x01c 5779a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS4 0x020 5789a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS5 0x024 5799a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS6 0x028 5809a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS7 0x02c 5819a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 5829a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 5839a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 5849a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 5859a24b929SJack Pham #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 5869a24b929SJack Pham #define QPHY_V4_PCS_START_CONTROL 0x044 5879a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 5889a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 5899a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 5909a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 5919a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 5929a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 5939a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 5949a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 5959a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 5969a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 5979a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 5989a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 5999a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 6009a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 6019a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 6029a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 6039a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 6049a24b929SJack Pham #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 6059a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 6069a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 6079a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL1 0x098 6089a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 6099a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 6109a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 6119a24b929SJack Pham #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 6129a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 6139a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 6149a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 6159a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 6169a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 6179a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 6189a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 6199a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 6209a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 6219a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 6229a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 6239a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 6249a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 6259a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 6269a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 6279a24b929SJack Pham #define QPHY_V4_PCS_BIST_CTRL 0x0e8 6289a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 6299a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 6309a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 6319a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 6329a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 6339a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT3 0x100 6349a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT4 0x104 6359a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT5 0x108 6369a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT6 0x10c 6379a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT7 0x110 6389a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT8 0x114 6399a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT9 0x118 6409a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT10 0x11c 6419a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT11 0x120 6429a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT12 0x124 6439a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT13 0x128 6449a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT14 0x12c 6459a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT15 0x130 6469a24b929SJack Pham #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 6479a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 6489a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 6499a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 6509a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 6519a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 6529a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 6539a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 6549a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 6559a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 6569a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 6579a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 6589a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 6599a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 6609a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 6619a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 6629a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 6639a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 6649a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 6659a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 6669a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 6679a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 6689a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 6699a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 6709a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 6719a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 6729a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 6739a24b929SJack Pham #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 6749a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 6759a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 6769a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 6779a24b929SJack Pham #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 6789a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 6799a24b929SJack Pham #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 6809a24b929SJack Pham #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 6819a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 6829a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 6839a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 6849a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 6859a24b929SJack Pham #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 6869a24b929SJack Pham #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 6879a24b929SJack Pham #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 6889a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 6899a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 6909a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 6919a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 6929a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 6939a24b929SJack Pham #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300 6949a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 6959a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 6969a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 6979a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 6989a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 6999a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 7009a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c 7019a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 7029a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 7039a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328 7049a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c 7059a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330 7069a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334 7079a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338 7089a24b929SJack Pham #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c 7099a24b929SJack Pham #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340 7109a24b929SJack Pham #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344 7119a24b929SJack Pham #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348 7129a24b929SJack Pham #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c 7139a24b929SJack Pham #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350 7149a24b929SJack Pham #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 7159a24b929SJack Pham #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 7169a24b929SJack Pham 7177b675ba1SJonathan Marek /* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */ 7187b675ba1SJonathan Marek #define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618 7197b675ba1SJonathan Marek #define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638 7207b675ba1SJonathan Marek 7219a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 7229a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 7239a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 7249a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 7259a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 7269a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 7279a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 7289a24b929SJack Pham 729e2248617SManu Gautam #endif 730