1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 99e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com.h" 109e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx.h" 119e1bae6dSDmitry Baryshkov 12*a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v3.h" 13*a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v3.h" 14*a7fc833eSDmitry Baryshkov 15520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ 16520264dbSSelvam Sathappan Periakaruppan 17520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TIMER 0x00c 18520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER1 0x01c 19520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER2 0x020 20520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 21520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 22520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 23520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 24520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 25520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_ENABLE1 0x040 26520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYS_CLK_CTRL 0x044 27520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 28520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_IVCO 0x050 29520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 30520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 31520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 32520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 33520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TRIM 0x074 34520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 35520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c 36520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE0 0x080 37520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE1 0x084 38520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 39fe841d5bSJohan Hovold #define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c 40520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 41520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 42520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 43520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 44520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_RESETSM_CNTRL 0x0b0 45520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP_EN 0x0c4 46520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE0 0x0cc 47520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE1 0x0d0 48520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 49520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc 50520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 51520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 52520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 53fe841d5bSJohan Hovold #define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec 54520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 55520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 56520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 57520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c 58520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_MAP 0x120 59520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 60520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 61520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c 62520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 63520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c 64520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 65520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_SELECT 0x16c 66520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_HSCLK_SEL 0x170 67520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV 0x17c 68520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORE_CLK_EN 0x184 69520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CMN_CONFIG 0x18c 70520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 71520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 72520264dbSSelvam Sathappan Periakaruppan 73e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 746cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04 756cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24 766cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x28 776cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x34 786cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x38 796cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x3c 806cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x40 816cad2983SDmitry Baryshkov #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x54 826cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x58 836cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x60 846cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x64 856cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x6c 866cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x80 876cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x84 886cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x88 896cad2983SDmitry Baryshkov #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 906cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 916cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc 926cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c 936cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140 946cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148 956cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154 966cad2983SDmitry Baryshkov #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 976cad2983SDmitry Baryshkov #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac 986cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 996cad2983SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 1006cad2983SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 101e2248617SManu Gautam 1029a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 1039c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 1049c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 1059c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 1069c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 1079c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 1089c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 1099c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 1109c7761a3SManu Gautam 111*a7fc833eSDmitry Baryshkov /* QSERDES V3 COM bits */ 11252e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 11352e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 11452e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 11552e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 11652e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 11752e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 11852e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 1199c7761a3SManu Gautam 120*a7fc833eSDmitry Baryshkov /* QSERDES V3 TX bits */ 12152e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 12252e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 12352e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 12452e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 12552e013d0SStephen Boyd 1269c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 1279c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 1289c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 1299c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 1309c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 1319c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 1329c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 1339c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 134cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 135cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 1369c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 1379c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 1389c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 1399c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 1409c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 1419c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 1429c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 1439c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 1449c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 1459c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 1469c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 1479c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 1489c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 1499c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 1509c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 1519c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 1529c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 1539c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 1549c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 1559c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 1569c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 1579c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 1589c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 1599c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 1609c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 1619c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 1629c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 1639c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 16473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 1659c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 1669c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 1679c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 1689c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 1699c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 1709c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 1719c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 1729c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 173cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 174cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 175cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 176cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 17773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 17873d7ec89SMarc Gonzalez #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 17973d7ec89SMarc Gonzalez #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 180cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 181cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 1829c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 18373d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 18473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 185f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 186f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 1879c7761a3SManu Gautam 188ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 189ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 19073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 19173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 19273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 19373d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 19473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 195ac0d2399SManu Gautam 1965c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 1975c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 1985c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 1995c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 2005c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 2015c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 2025c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 20352e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 20452e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 20552e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 20652e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 20752e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 20852e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 20952e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 2105c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 2115c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 2125c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 2135c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 2145c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 2155c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 2165c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 2175c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 2185c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 2195c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 2205c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 22152e013d0SStephen Boyd 2225c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 22352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 22452e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 22552e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 22652e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 22752e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 22852e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 22952e013d0SStephen Boyd 23052e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 23152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 23252e013d0SStephen Boyd 23352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 23452e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 23552e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 23652e013d0SStephen Boyd 23752e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 23852e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 23952e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 24052e013d0SStephen Boyd 24152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 24252e013d0SStephen Boyd 243a88c85eeSVinod Koul /* Only for QMP V4 PHY - QSERDES COM registers */ 244aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BG_TIMER 0x00c 2459a24b929SJack Pham #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 246f199223cSBjorn Andersson #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014 2479a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER1 0x01c 2489a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER2 0x020 2499a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 2509a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 2519a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 2529a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 253aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 2546edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_ENABLE1 0x048 255aff188feSDmitry Baryshkov #define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c 2569a24b929SJack Pham #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 257a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_IVCO 0x058 258a88c85eeSVinod Koul #define QSERDES_V4_COM_CMN_IPTRIM 0x060 259a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 260a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 261a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 262a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 263a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 264a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 265a88c85eeSVinod Koul #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 266aff188feSDmitry Baryshkov #define QSERDES_V4_COM_RESETSM_CNTRL 0x09c 267a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 268be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8 269a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 270a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 271a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 272a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 27374acf0eeSJohan Hovold #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 274a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 2759a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 2769a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 2779a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 2789a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 2799a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 2809a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 281aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec 282aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 283be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 284be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 285aff188feSDmitry Baryshkov #define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 286a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 2879a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 2889a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 2899a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 2909a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 291a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 292aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_STATUS 0x140 2936edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_SELECT 0x154 294a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_SEL 0x158 295a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 296aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 2979a24b929SJack Pham #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 298aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORE_CLK_EN 0x174 299aff188feSDmitry Baryshkov #define QSERDES_V4_COM_C_READY_STATUS 0x178 300aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_CONFIG 0x17c 3019a24b929SJack Pham #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 302be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_CMN_MISC1 0x19c 303be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0 304be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_CMN_MODE 0x1a4 305be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8 306a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 307a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 308a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 309a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 310be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 311a88c85eeSVinod Koul 312a88c85eeSVinod Koul /* Only for QMP V4 PHY - TX registers */ 313aff188feSDmitry Baryshkov #define QSERDES_V4_TX_CLKBUF_ENABLE 0x08 314aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c 315aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_DRV_LVL 0x14 316aff188feSDmitry Baryshkov #define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c 317aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20 318aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_BAND 0x24 319aff188feSDmitry Baryshkov #define QSERDES_V4_TX_INTERFACE_SELECT 0x2c 3209a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 3219a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 3227b675ba1SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c 32390b65347SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 324aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54 325aff188feSDmitry Baryshkov #define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58 326aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_POL_INV 0x5c 327aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 328a88c85eeSVinod Koul #define QSERDES_V4_TX_LANE_MODE_1 0x84 32990b65347SJonathan Marek #define QSERDES_V4_TX_LANE_MODE_2 0x88 3309a24b929SJack Pham #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 331aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 332aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc 333a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 334fe841d5bSJohan Hovold #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdc 335a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 336a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 337aff188feSDmitry Baryshkov #define QSERDES_V4_TX_VMODE_CTRL1 0xe8 3389a24b929SJack Pham #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 339a88c85eeSVinod Koul 340be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - TX registers */ 341be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 342be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 343be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 344be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 345be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 346be0ddb5dSManivannan Sadhasivam 347a88c85eeSVinod Koul /* Only for QMP V4 PHY - RX registers */ 348a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 349a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 350a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 351a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 352a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 3539a24b929SJack Pham #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 354a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 355a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 3569a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 3579a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 3589a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 3599a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 3609a24b929SJack Pham #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 3616edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 362a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 363a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 364a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_TERM_BW 0x080 3659a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 3669a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 3679a24b929SJack Pham #define QSERDES_V4_RX_GM_CAL 0x0dc 3686edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 369a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 370a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 371a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 372a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 373a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 374a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 3759a24b929SJack Pham #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 376a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 3776edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_SIGDET_ENABLES 0x118 378a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 379a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_LVL 0x120 380a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 381a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_BAND 0x128 382a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 383a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 384a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 385a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 386a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 387a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 388a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 389a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 390a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 391a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 392a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 393a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 394a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 395a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 396a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 3979a24b929SJack Pham #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 3989a24b929SJack Pham #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 399a88c85eeSVinod Koul #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 4009a24b929SJack Pham #define QSERDES_V4_RX_VTH_CODE 0x1c4 401a88c85eeSVinod Koul 402aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 403aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 404aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 405aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 406aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 407aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 408aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 409aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 410aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 411aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 412aff188feSDmitry Baryshkov 413be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - RX registers */ 414be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 415be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 416be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 417be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_3 0x110 418be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 419be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 420be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 421be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 422be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 423be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 424be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 425be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 426be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 427be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 428be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 429be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 430be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 431be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 432be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 433be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 434be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 435be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 436be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 437be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 438be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 439be0ddb5dSManivannan Sadhasivam 4409a24b929SJack Pham /* Only for QMP V4 PHY - UFS PCS registers */ 44178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PHY_START 0x000 44278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 44378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_SW_RESET 0x008 44478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 44578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 44678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 44778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 44878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 44978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 45078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 45178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 45278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 45378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 45478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 45578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 45678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 45778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 45878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 45978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 46078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 461a88c85eeSVinod Koul 462909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 463909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 464909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 465909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 466909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 467909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 468909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 469909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 470909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 471909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 472909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 473909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 474909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 475909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 476909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 477909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 478909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 479909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 480909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 481909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 482909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 483909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 484909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 485909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 486909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 487909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 488909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 489909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 490909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 491909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 492909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 493909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 494909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 495909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 496909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 497909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 498909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 499909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 500909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 501909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 502909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 503909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 504909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 505909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 506909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 507909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 508909a5c78SBjorn Andersson 509909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 510909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 511909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 512909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 513909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 514909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 515909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 516909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 517909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 518909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 519909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 520909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 521909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 522909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 523909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 524909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 525909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 526909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 527909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 528909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 529909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 530909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 531909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 532909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 533909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 534909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 535909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 536909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 537909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 538909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 539909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 540909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 541909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 542909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 543909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 544909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 545909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 546909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 547909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 548909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 549909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 550909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 551909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 552909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 553909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 554909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 555909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 556909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 557909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 558909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 559909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 560909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 561909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 562909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 563909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 564909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 565909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 566909a5c78SBjorn Andersson 567909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 568909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 569909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 570909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 571909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 572909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 573909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 574909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 575909a5c78SBjorn Andersson 5769a24b929SJack Pham /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 5779a24b929SJack Pham #define QPHY_V4_PCS_SW_RESET 0x000 5789a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID0 0x004 5799a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID1 0x008 5809a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID2 0x00c 5819a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID3 0x010 5829a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS1 0x014 5839a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS2 0x018 5849a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS3 0x01c 5859a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS4 0x020 5869a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS5 0x024 5879a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS6 0x028 5889a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS7 0x02c 5899a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 5909a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 5919a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 5929a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 5939a24b929SJack Pham #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 5949a24b929SJack Pham #define QPHY_V4_PCS_START_CONTROL 0x044 5959a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 5969a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 5979a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 5989a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 5999a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 6009a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 6019a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 6029a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 6039a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 6049a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 6059a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 6069a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 6079a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 6089a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 6099a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 6109a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 6119a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 6129a24b929SJack Pham #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 6139a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 6149a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 6159a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL1 0x098 6169a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 6179a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 6189a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 6199a24b929SJack Pham #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 6209a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 6219a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 6229a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 6239a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 6249a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 6259a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 6269a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 6279a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 6289a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 6299a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 6309a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 6319a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 6329a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 6339a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 6349a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 6359a24b929SJack Pham #define QPHY_V4_PCS_BIST_CTRL 0x0e8 6369a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 6379a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 6389a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 6399a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 6409a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 6419a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT3 0x100 6429a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT4 0x104 6439a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT5 0x108 6449a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT6 0x10c 6459a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT7 0x110 6469a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT8 0x114 6479a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT9 0x118 6489a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT10 0x11c 6499a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT11 0x120 6509a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT12 0x124 6519a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT13 0x128 6529a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT14 0x12c 6539a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT15 0x130 6549a24b929SJack Pham #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 6559a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 6569a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 6579a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 6589a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 6599a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 6609a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 6619a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 6629a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 6639a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 6649a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 6659a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 6669a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 6679a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 6689a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 6699a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 6709a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 6719a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 6729a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 6739a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 6749a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 6759a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 6769a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 6779a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 6789a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 6799a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 6809a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 6819a24b929SJack Pham #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 6829a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 6839a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 6849a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 6859a24b929SJack Pham #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 6869a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 6879a24b929SJack Pham #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 6889a24b929SJack Pham #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 6899a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 6909a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 6919a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 6929a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 6939a24b929SJack Pham #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 6949a24b929SJack Pham #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 6959a24b929SJack Pham #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 6969a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 6979a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 6989a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 6999a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 7009a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 701fc646236SDmitry Baryshkov 702fc646236SDmitry Baryshkov /* Only for QMP V4 PHY - USB3 PCS registers */ 703fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000 704fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 705fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 706fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 707fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 708fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 709fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 710fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c 711fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 712fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 713fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028 714fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c 715fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030 716fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034 717fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038 718fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c 719fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040 720fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044 721fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048 722fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c 723fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050 724fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054 725fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058 7269a24b929SJack Pham 727be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 728be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 729be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 730be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 731be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 732be0ddb5dSManivannan Sadhasivam 7339a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 7349a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 7359a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 7369a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 7379a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 7389a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 7399a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 7409a24b929SJack Pham 7416edf7700SManivannan Sadhasivam /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 7426edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 7436edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 7446edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 7456edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 7466edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 7476edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 7486edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 74960f23414SDmitry Baryshkov #define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0 7506edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 7516edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 7526edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 7536edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 7546edf7700SManivannan Sadhasivam 755be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 756be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 757be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 758be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 759be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 760be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 761be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 762be0ddb5dSManivannan Sadhasivam 763920abc10SVinod Koul /* Only for QMP V5 PHY - QSERDES COM registers */ 764107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_EN_CENTER 0x010 765107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_PER1 0x01c 766107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_PER2 0x020 767107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 768107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 769107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 770107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 7712c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 772107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_CLK_ENABLE1 0x048 773107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 774920abc10SVinod Koul #define QSERDES_V5_COM_PLL_IVCO 0x058 775920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 776920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 777920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c 778920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 779920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 780920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 781920abc10SVinod Koul #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 782920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 7832c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 784920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac 785920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 786920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 787920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 78874acf0eeSJohan Hovold #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc 789920abc10SVinod Koul #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 790107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc 791107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 792107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 793107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 794107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc 795107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 796920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c 797107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 798107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 799107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 800107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c 801920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 802107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_CLK_SELECT 0x154 803920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_SEL 0x158 804920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c 8052c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 806107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c 8072c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CORE_CLK_EN 0x174 8082c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CMN_CONFIG 0x17c 8092c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CMN_MISC1 0x19c 810488987b2SDmitry Baryshkov #define QSERDES_V5_COM_CMN_MODE 0x1a0 811488987b2SDmitry Baryshkov #define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4 8122c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8 813920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 814920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 815920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 816920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 81774acf0eeSJohan Hovold #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 818920abc10SVinod Koul 81910c744d4SJack Pham /* Only for QMP V5 PHY - TX registers */ 82010c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 82110c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38 82210c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c 82310c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40 82410c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_1 0x84 82510c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_2 0x88 82610c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_3 0x8c 82710c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_4 0x90 82810c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_5 0x94 82910c744d4SJack Pham #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4 83010c744d4SJack Pham #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0 83110c744d4SJack Pham #define QSERDES_V5_TX_PI_QEC_CTRL 0xe4 832920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 833920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 834920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 835920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 83610c744d4SJack Pham 8372c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - TX registers */ 8382c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 8392c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 8402c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 8412c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 8422c91bf6bSDmitry Baryshkov 84310c744d4SJack Pham /* Only for QMP V5 PHY - RX registers */ 84410c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 84510c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 84610c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 84710c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 84810c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 84910c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 85010c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 85110c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 85210c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c 85310c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 85410c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 85510c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 85610c744d4SJack Pham #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 85710c744d4SJack Pham #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 85810c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 85910c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 86010c744d4SJack Pham #define QSERDES_V5_RX_RX_TERM_BW 0x080 861107ba9bfSDmitry Baryshkov #define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc 86210c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 86310c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 86410c744d4SJack Pham #define QSERDES_V5_RX_GM_CAL 0x0dc 86510c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 86610c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 86710c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 86810c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 86910c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 87010c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 87110c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 87210c744d4SJack Pham #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 87310c744d4SJack Pham #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 87410c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 87510c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c 87610c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_LVL 0x120 87710c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 87810c744d4SJack Pham #define QSERDES_V5_RX_RX_BAND 0x128 87910c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 88010c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 88110c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 88210c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 88310c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c 88410c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 88510c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 88610c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 88710c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c 88810c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 88910c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 89010c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 89110c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 89210c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 89310c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 89410c744d4SJack Pham #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 89510c744d4SJack Pham #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 89610c744d4SJack Pham #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 89710c744d4SJack Pham #define QSERDES_V5_RX_VTH_CODE 0x1b0 89810c744d4SJack Pham 8992c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - RX registers */ 9002c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 9012c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c 9022c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 9032c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c 9042c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 9052c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c 9062c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_3 0x090 9072c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 9082c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 9092c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 9102c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc 9112c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_GM_CAL 0x0ec 9122c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 9132c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 9142c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 9152c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c 9162c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 9172c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 9182c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c 9192c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 9202c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 9212c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 9222c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c 9232c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 9242c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 9252c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 9262c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c 9272c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 9282c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 9292c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 9302c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac 9312c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 9322c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 9332c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 9342c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 9352c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 9362c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc 9372c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 9382c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 9392c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 9402c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 9412c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 9422c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 9432c91bf6bSDmitry Baryshkov 944107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - USB/PCIe PCS registers */ 945107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc 9462c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 947107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 948107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 9492c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 9502c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 951107ba9bfSDmitry Baryshkov 952107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - PCS_PCIE registers */ 953107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 954107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 955107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 956107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 957107ba9bfSDmitry Baryshkov 9582c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - PCIe PCS registers */ 9592c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 9602c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 9612c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 9622c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 9632c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 9642c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 9652c91bf6bSDmitry Baryshkov 966920abc10SVinod Koul /* Only for QMP V5 PHY - UFS PCS registers */ 967920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 968920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 969920abc10SVinod Koul #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 970920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 971920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 972920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 973920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 974920abc10SVinod Koul #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 975920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 976920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 977920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 978920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 979920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 980920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 981920abc10SVinod Koul #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 982920abc10SVinod Koul 98310c744d4SJack Pham /* Only for QMP V5 PHY - USB3 have different offsets than V4 */ 984fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000 985fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 986fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 987fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 988fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 989fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 990fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 991fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c 992fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 993fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 994fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028 995fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c 996fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030 997fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034 998fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038 999fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c 1000fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040 1001fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044 1002fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048 1003fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c 1004fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050 1005fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054 1006fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058 1007fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c 1008fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060 100910c744d4SJack Pham 1010e2248617SManu Gautam #endif 1011