1e2248617SManu Gautam // SPDX-License-Identifier: GPL-2.0 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 9e2248617SManu Gautam /* Only for QMP V2 PHY - QSERDES COM registers */ 10e2248617SManu Gautam #define QSERDES_COM_BG_TIMER 0x00c 11e2248617SManu Gautam #define QSERDES_COM_SSC_EN_CENTER 0x010 12e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER1 0x014 13e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER2 0x018 14e2248617SManu Gautam #define QSERDES_COM_SSC_PER1 0x01c 15e2248617SManu Gautam #define QSERDES_COM_SSC_PER2 0x020 16e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE1 0x024 17e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE2 0x028 18e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 19e2248617SManu Gautam #define QSERDES_COM_CLK_ENABLE1 0x038 20e2248617SManu Gautam #define QSERDES_COM_SYS_CLK_CTRL 0x03c 21e2248617SManu Gautam #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 22e2248617SManu Gautam #define QSERDES_COM_PLL_IVCO 0x048 23e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 24e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 25e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 26e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 27e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 28e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 29e2248617SManu Gautam #define QSERDES_COM_BG_TRIM 0x070 30e2248617SManu Gautam #define QSERDES_COM_CLK_EP_DIV 0x074 31e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE0 0x078 32e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE1 0x07c 33e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 34e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 35e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 36e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 37e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 38e2248617SManu Gautam #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 39e2248617SManu Gautam #define QSERDES_COM_RESETSM_CNTRL 0x0b4 40e2248617SManu Gautam #define QSERDES_COM_RESTRIM_CTRL 0x0bc 41e2248617SManu Gautam #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 42e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_EN 0x0c8 43e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 44e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE0 0x0d0 45e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE1 0x0d4 46e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 47e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 48e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 49e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 50e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 51e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 52e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 53e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 54e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 55e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 56e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_CTRL 0x124 57e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_MAP 0x128 58e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 59e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 60e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 61e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 62e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 63e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 64e2248617SManu Gautam #define QSERDES_COM_BG_CTRL 0x170 65e2248617SManu Gautam #define QSERDES_COM_CLK_SELECT 0x174 66e2248617SManu Gautam #define QSERDES_COM_HSCLK_SEL 0x178 67e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV 0x184 68e2248617SManu Gautam #define QSERDES_COM_CORE_CLK_EN 0x18c 69e2248617SManu Gautam #define QSERDES_COM_C_READY_STATUS 0x190 70e2248617SManu Gautam #define QSERDES_COM_CMN_CONFIG 0x194 71e2248617SManu Gautam #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 72e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS0 0x1a0 73e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS1 0x1a4 74e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS2 0x1a8 75e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS3 0x1ac 76e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 77e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 78e2248617SManu Gautam 79e2248617SManu Gautam /* Only for QMP V2 PHY - TX registers */ 80e2248617SManu Gautam #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 81e2248617SManu Gautam #define QSERDES_TX_DEBUG_BUS_SEL 0x064 82e2248617SManu Gautam #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 83e2248617SManu Gautam #define QSERDES_TX_LANE_MODE 0x094 84e2248617SManu Gautam #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 85e2248617SManu Gautam 86e2248617SManu Gautam /* Only for QMP V2 PHY - RX registers */ 87e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 88e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN 0x01c 89e2248617SManu Gautam #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 90e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 91e2248617SManu Gautam #define QSERDES_RX_RX_TERM_BW 0x090 92e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 93e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 94e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 95e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 96e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 97e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 98e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 99e2248617SManu Gautam #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 100e2248617SManu Gautam #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 101e2248617SManu Gautam #define QSERDES_RX_SIGDET_ENABLES 0x110 102e2248617SManu Gautam #define QSERDES_RX_SIGDET_CNTRL 0x114 103e2248617SManu Gautam #define QSERDES_RX_SIGDET_LVL 0x118 104e2248617SManu Gautam #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 105e2248617SManu Gautam #define QSERDES_RX_RX_BAND 0x120 106e2248617SManu Gautam #define QSERDES_RX_RX_INTERFACE_MODE 0x12c 107e2248617SManu Gautam 108e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 109e2248617SManu Gautam #define QPHY_POWER_DOWN_CONTROL 0x04 110e2248617SManu Gautam #define QPHY_TXDEEMPH_M6DB_V0 0x24 111e2248617SManu Gautam #define QPHY_TXDEEMPH_M3P5DB_V0 0x28 112e2248617SManu Gautam #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 113e2248617SManu Gautam #define QPHY_RX_IDLE_DTCT_CNTRL 0x58 114e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG1 0x60 115e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG2 0x64 116e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG4 0x6c 117e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG1 0x80 118e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG2 0x84 119e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG3 0x88 120e2248617SManu Gautam #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 121e2248617SManu Gautam #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 122e2248617SManu Gautam #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 123e2248617SManu Gautam #define QPHY_OSC_DTCT_ACTIONS 0x1AC 124e2248617SManu Gautam #define QPHY_RX_SIGDET_LVL 0x1D8 125e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC 126e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 127e2248617SManu Gautam 1289c7761a3SManu Gautam /* Only for QMP V3 PHY - DP COM registers */ 1299c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 1309c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 1319c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 1329c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 1339c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 1349c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 1359c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 1369c7761a3SManu Gautam 1379c7761a3SManu Gautam /* Only for QMP V3 PHY - QSERDES COM registers */ 1389c7761a3SManu Gautam #define QSERDES_V3_COM_BG_TIMER 0x00c 1399c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 1409c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 1419c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 1429c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER1 0x01c 1439c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER2 0x020 1449c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 1459c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 1469c7761a3SManu Gautam #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 1479c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_ENABLE1 0x038 1489c7761a3SManu Gautam #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 1499c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 1509c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_IVCO 0x048 1519c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 1529c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 1539c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 1549c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 1559c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 1569c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 1579c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 1589c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 1599c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 1609c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 1619c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 1629c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 1639c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 1649c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 1659c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 1669c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 1679c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 1689c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 1699c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 1709c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 1719c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 1729c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 1739c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 1749c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 1759c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 1769c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 177a51969faSJeffrey Hugo #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 1789c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 1799c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 1809c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 1819c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 1829c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 1839c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 1849c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 1859c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 1869c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 1879c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 188cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 189cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 1909c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 1919c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 1929c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_SELECT 0x138 1939c7761a3SManu Gautam #define QSERDES_V3_COM_HSCLK_SEL 0x13c 1949c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 1959c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 1969c7761a3SManu Gautam #define QSERDES_V3_COM_CORE_CLK_EN 0x154 1979c7761a3SManu Gautam #define QSERDES_V3_COM_C_READY_STATUS 0x158 1989c7761a3SManu Gautam #define QSERDES_V3_COM_CMN_CONFIG 0x15c 1999c7761a3SManu Gautam #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 2009c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS0 0x168 2019c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 2029c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS2 0x170 2039c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS3 0x174 2049c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 205a51969faSJeffrey Hugo #define QSERDES_V3_COM_CMN_MODE 0x184 2069c7761a3SManu Gautam 2079c7761a3SManu Gautam /* Only for QMP V3 PHY - TX registers */ 2089c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 2099c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 2109c7761a3SManu Gautam #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 2119c7761a3SManu Gautam #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 2129c7761a3SManu Gautam #define QSERDES_V3_TX_LANE_MODE_1 0x08c 2139c7761a3SManu Gautam #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 2149c7761a3SManu Gautam 2159c7761a3SManu Gautam /* Only for QMP V3 PHY - RX registers */ 216a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 2179c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 2189c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 219cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 220cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 221cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 2229c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 2239c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 224cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 225a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 226cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 2279c7761a3SManu Gautam #define QSERDES_V3_RX_RX_TERM_BW 0x07c 228f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 229f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 2309c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 2319c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 2329c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 2339c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 2349c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 2359c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 2369c7761a3SManu Gautam #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 2379c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_ENABLES 0x100 2389c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_CNTRL 0x104 2399c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_LVL 0x108 2409c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 2419c7761a3SManu Gautam #define QSERDES_V3_RX_RX_BAND 0x110 2429c7761a3SManu Gautam #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 243f6721e5cSManu Gautam #define QSERDES_V3_RX_RX_MODE_00 0x164 2449c7761a3SManu Gautam 2459c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 2469c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 2479c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 2489c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 2499c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 2509c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 2519c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 2529c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 253cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 254cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 2559c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 2569c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 2579c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 2589c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 2599c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 2609c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 2619c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 2629c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 2639c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 2649c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 2659c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 2669c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 2679c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 2689c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 2699c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 2709c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 2719c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 2729c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 2739c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 2749c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 2759c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 2769c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 2779c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 2789c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 2799c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 2809c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 2819c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 2829c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 2839c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 2849c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 2859c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 2869c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 2879c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 2889c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 2899c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 2909c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 291cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 292cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 293cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 294cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 295cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 296cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 2979c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 298f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 299f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 3009c7761a3SManu Gautam 301ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 302ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 303ac0d2399SManu Gautam 304e2248617SManu Gautam #endif 305