1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 99e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com.h" 109e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx.h" 119e1bae6dSDmitry Baryshkov 12a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v3.h" 13a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v3.h" 14a7fc833eSDmitry Baryshkov 1532d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v4.h" 1632d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v4.h" 175fc21d1bSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v4_20.h" 1832d2cf53SDmitry Baryshkov 19f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v5.h" 20f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v5.h" 215fc21d1bSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v5_20.h" 22*a2e927b0SBjorn Andersson #include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h" 23f1f923adSDmitry Baryshkov 24147924ffSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-pll.h" 25520264dbSSelvam Sathappan Periakaruppan 265ae11aa4SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v2.h" 27e2248617SManu Gautam 2856a1fa09SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v3.h" 2956a1fa09SDmitry Baryshkov #include "phy-qcom-qmp-pcs-misc-v3.h" 30fc270d13SDmitry Baryshkov #include "phy-qcom-qmp-pcs-ufs-v3.h" 3156a1fa09SDmitry Baryshkov 3241ad371fSDmitry Baryshkov #include "phy-qcom-qmp-pcs-v4.h" 3341ad371fSDmitry Baryshkov #include "phy-qcom-qmp-pcs-pcie-v4.h" 3441ad371fSDmitry Baryshkov #include "phy-qcom-qmp-pcs-usb-v4.h" 3541ad371fSDmitry Baryshkov #include "phy-qcom-qmp-pcs-ufs-v4.h" 3641ad371fSDmitry Baryshkov 3725ad4a4cSDmitry Baryshkov #include "phy-qcom-qmp-pcs-v4_20.h" 3825ad4a4cSDmitry Baryshkov #include "phy-qcom-qmp-pcs-pcie-v4_20.h" 3925ad4a4cSDmitry Baryshkov 40b7a2f882SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v5.h" 41b7a2f882SDmitry Baryshkov #include "phy-qcom-qmp-pcs-pcie-v5.h" 42b7a2f882SDmitry Baryshkov #include "phy-qcom-qmp-pcs-usb-v5.h" 43b7a2f882SDmitry Baryshkov #include "phy-qcom-qmp-pcs-ufs-v5.h" 44b7a2f882SDmitry Baryshkov 4525ad4a4cSDmitry Baryshkov #include "phy-qcom-qmp-pcs-pcie-v5_20.h" 4625ad4a4cSDmitry Baryshkov 4787d71378SDmitry Baryshkov #include "phy-qcom-qmp-pcie-qhp.h" 4887d71378SDmitry Baryshkov 499a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 509c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 519c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 529c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 539c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 549c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 559c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 569c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 579c7761a3SManu Gautam 58a7fc833eSDmitry Baryshkov /* QSERDES V3 COM bits */ 5952e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 6052e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 6152e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 6252e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 6352e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 6452e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 6552e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 669c7761a3SManu Gautam 67a7fc833eSDmitry Baryshkov /* QSERDES V3 TX bits */ 6852e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 6952e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 7052e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 7152e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 7252e013d0SStephen Boyd 735c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 745c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 755c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 765c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 775c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 785c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 795c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 8052e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 8152e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 8252e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 8352e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 8452e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 8552e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 8652e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 875c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 885c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 895c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 905c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 915c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 925c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 935c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 945c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 955c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 965c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 975c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 9852e013d0SStephen Boyd 995c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 10052e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 10152e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 10252e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 10352e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 10452e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 10552e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 10652e013d0SStephen Boyd 10752e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 10852e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 10952e013d0SStephen Boyd 11052e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 11152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 11252e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 11352e013d0SStephen Boyd 11452e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 11552e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 11652e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 11752e013d0SStephen Boyd 11852e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 11952e013d0SStephen Boyd 120aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 121aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 122aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 123aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 124aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 125aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 126aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 127aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 128aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 129aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 130aff188feSDmitry Baryshkov 1319a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 1329a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 1339a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 1349a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 1359a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 1369a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 1379a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 1389a24b929SJack Pham 139e2248617SManu Gautam #endif 140