1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 9*9e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com.h" 10*9e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx.h" 11*9e1bae6dSDmitry Baryshkov 12520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ 13520264dbSSelvam Sathappan Periakaruppan 14520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TIMER 0x00c 15520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER1 0x01c 16520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER2 0x020 17520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 18520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 19520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 20520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 21520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 22520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_ENABLE1 0x040 23520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYS_CLK_CTRL 0x044 24520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 25520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_IVCO 0x050 26520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 27520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 28520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 29520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 30520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TRIM 0x074 31520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 32520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c 33520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE0 0x080 34520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE1 0x084 35520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 36fe841d5bSJohan Hovold #define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c 37520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 38520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 39520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 40520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 41520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_RESETSM_CNTRL 0x0b0 42520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP_EN 0x0c4 43520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE0 0x0cc 44520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE1 0x0d0 45520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 46520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc 47520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 48520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 49520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 50fe841d5bSJohan Hovold #define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec 51520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 52520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 53520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 54520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c 55520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_MAP 0x120 56520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 57520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 58520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c 59520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 60520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c 61520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 62520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_SELECT 0x16c 63520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_HSCLK_SEL 0x170 64520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV 0x17c 65520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORE_CLK_EN 0x184 66520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CMN_CONFIG 0x18c 67520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 68520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 69520264dbSSelvam Sathappan Periakaruppan 70e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 716cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04 726cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24 736cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x28 746cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x34 756cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x38 766cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x3c 776cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x40 786cad2983SDmitry Baryshkov #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x54 796cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x58 806cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x60 816cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x64 826cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x6c 836cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x80 846cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x84 856cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x88 866cad2983SDmitry Baryshkov #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 876cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 886cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc 896cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c 906cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140 916cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148 926cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154 936cad2983SDmitry Baryshkov #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 946cad2983SDmitry Baryshkov #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac 956cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 966cad2983SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 976cad2983SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 98e2248617SManu Gautam 999a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 1009c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 1019c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 1029c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 1039c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 1049c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 1059c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 1069c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 1079c7761a3SManu Gautam 1089c7761a3SManu Gautam /* Only for QMP V3 PHY - QSERDES COM registers */ 10952e013d0SStephen Boyd #define QSERDES_V3_COM_ATB_SEL1 0x000 11052e013d0SStephen Boyd #define QSERDES_V3_COM_ATB_SEL2 0x004 11152e013d0SStephen Boyd #define QSERDES_V3_COM_FREQ_UPDATE 0x008 1129c7761a3SManu Gautam #define QSERDES_V3_COM_BG_TIMER 0x00c 1139c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 1149c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 1159c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 1169c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER1 0x01c 1179c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER2 0x020 1189c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 1199c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 120152a810eSIskren Chernev #define QSERDES_V3_COM_POST_DIV 0x02c 121152a810eSIskren Chernev #define QSERDES_V3_COM_POST_DIV_MUX 0x030 1229c7761a3SManu Gautam #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 12352e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 12452e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 12552e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 12652e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 12752e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 12852e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 12952e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 1309c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_ENABLE1 0x038 1319c7761a3SManu Gautam #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 1329c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 133152a810eSIskren Chernev #define QSERDES_V3_COM_PLL_EN 0x044 1349c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_IVCO 0x048 1359c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 1369c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 1379c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 1389c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 1399c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 1409c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 1419c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 1429c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 1439c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 1449c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 1459c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 1469c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 1479c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 1489c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 1499c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 1509c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 1519c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 1529c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 1539c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 1549c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 1559c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 1569c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 1579c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 1589c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 1599c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 1609c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 161a51969faSJeffrey Hugo #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 1629c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 1639c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 1649c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 1659c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 1669c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 1679c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 1689c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 1699c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 1709c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 1719c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 172cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 173cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 1749c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 1759c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 1769c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_SELECT 0x138 1779c7761a3SManu Gautam #define QSERDES_V3_COM_HSCLK_SEL 0x13c 1789c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 1799c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 1809c7761a3SManu Gautam #define QSERDES_V3_COM_CORE_CLK_EN 0x154 1819c7761a3SManu Gautam #define QSERDES_V3_COM_C_READY_STATUS 0x158 1829c7761a3SManu Gautam #define QSERDES_V3_COM_CMN_CONFIG 0x15c 1839c7761a3SManu Gautam #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 1849c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS0 0x168 1859c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 1869c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS2 0x170 1879c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS3 0x174 1889c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 189a51969faSJeffrey Hugo #define QSERDES_V3_COM_CMN_MODE 0x184 1909c7761a3SManu Gautam 1919c7761a3SManu Gautam /* Only for QMP V3 PHY - TX registers */ 19252e013d0SStephen Boyd #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 19352e013d0SStephen Boyd #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 19452e013d0SStephen Boyd #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c 19552e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 19652e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 19752e013d0SStephen Boyd 19852e013d0SStephen Boyd #define QSERDES_V3_TX_TX_DRV_LVL 0x01c 19952e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 20052e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 20152e013d0SStephen Boyd 20252e013d0SStephen Boyd #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 20352e013d0SStephen Boyd #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 20452e013d0SStephen Boyd 20552e013d0SStephen Boyd #define QSERDES_V3_TX_TX_BAND 0x02c 20652e013d0SStephen Boyd #define QSERDES_V3_TX_SLEW_CNTL 0x030 20752e013d0SStephen Boyd #define QSERDES_V3_TX_INTERFACE_SELECT 0x034 20852e013d0SStephen Boyd #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c 20952e013d0SStephen Boyd #define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 2109c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 2119c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 2129c7761a3SManu Gautam #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 21352e013d0SStephen Boyd #define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c 2149c7761a3SManu Gautam #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 21552e013d0SStephen Boyd #define QSERDES_V3_TX_TX_POL_INV 0x064 21652e013d0SStephen Boyd #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 2179c7761a3SManu Gautam #define QSERDES_V3_TX_LANE_MODE_1 0x08c 2189c7761a3SManu Gautam #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 21952e013d0SStephen Boyd #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 22052e013d0SStephen Boyd #define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 22152e013d0SStephen Boyd #define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 2229c7761a3SManu Gautam 2239c7761a3SManu Gautam /* Only for QMP V3 PHY - RX registers */ 224a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 2259c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 2269c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 227cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 228cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 229cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 2309c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 2319c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 232cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 233a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 234cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 2359c7761a3SManu Gautam #define QSERDES_V3_RX_RX_TERM_BW 0x07c 236f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 237f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 2389c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 2399c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 2409c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 2419c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 2429c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 2439c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 2449c7761a3SManu Gautam #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 2459c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_ENABLES 0x100 2469c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_CNTRL 0x104 2479c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_LVL 0x108 2489c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 2499c7761a3SManu Gautam #define QSERDES_V3_RX_RX_BAND 0x110 2509c7761a3SManu Gautam #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 251f6721e5cSManu Gautam #define QSERDES_V3_RX_RX_MODE_00 0x164 25273d7ec89SMarc Gonzalez #define QSERDES_V3_RX_RX_MODE_01 0x168 2539c7761a3SManu Gautam 2549c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 2559c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 2569c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 2579c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 2589c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 2599c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 2609c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 2619c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 262cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 263cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 2649c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 2659c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 2669c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 2679c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 2689c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 2699c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 2709c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 2719c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 2729c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 2739c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 2749c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 2759c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 2769c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 2779c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 2789c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 2799c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 2809c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 2819c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 2829c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 2839c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 2849c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 2859c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 2869c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 2879c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 2889c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 2899c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 2909c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 2919c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 29273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 2939c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 2949c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 2959c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 2969c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 2979c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 2989c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 2999c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 3009c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 301cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 302cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 303cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 304cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 30573d7ec89SMarc Gonzalez #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 30673d7ec89SMarc Gonzalez #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 30773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 308cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 309cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 3109c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 31173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 31273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 313f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 314f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 3159c7761a3SManu Gautam 316ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 317ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 31873d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 31973d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 32073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 32173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 32273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 323ac0d2399SManu Gautam 3245c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 3255c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 3265c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 3275c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 3285c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 3295c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 3305c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 33152e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 33252e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 33352e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 33452e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 33552e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 33652e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 33752e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 3385c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 3395c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 3405c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 3415c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 3425c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 3435c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 3445c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 3455c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 3465c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 3475c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 3485c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 34952e013d0SStephen Boyd 3505c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 35152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 35252e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 35352e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 35452e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 35552e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 35652e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 35752e013d0SStephen Boyd 35852e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 35952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 36052e013d0SStephen Boyd 36152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 36252e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 36352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 36452e013d0SStephen Boyd 36552e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 36652e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 36752e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 36852e013d0SStephen Boyd 36952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 37052e013d0SStephen Boyd 371a88c85eeSVinod Koul /* Only for QMP V4 PHY - QSERDES COM registers */ 372aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BG_TIMER 0x00c 3739a24b929SJack Pham #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 374f199223cSBjorn Andersson #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014 3759a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER1 0x01c 3769a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER2 0x020 3779a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 3789a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 3799a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 3809a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 381aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 3826edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_ENABLE1 0x048 383aff188feSDmitry Baryshkov #define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c 3849a24b929SJack Pham #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 385a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_IVCO 0x058 386a88c85eeSVinod Koul #define QSERDES_V4_COM_CMN_IPTRIM 0x060 387a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 388a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 389a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 390a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 391a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 392a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 393a88c85eeSVinod Koul #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 394aff188feSDmitry Baryshkov #define QSERDES_V4_COM_RESETSM_CNTRL 0x09c 395a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 396be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8 397a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 398a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 399a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 400a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 40174acf0eeSJohan Hovold #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 402a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 4039a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 4049a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 4059a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 4069a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 4079a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 4089a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 409aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec 410aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 411be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 412be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 413aff188feSDmitry Baryshkov #define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 414a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 4159a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 4169a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 4179a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 4189a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 419a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 420aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_STATUS 0x140 4216edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_SELECT 0x154 422a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_SEL 0x158 423a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 424aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 4259a24b929SJack Pham #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 426aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORE_CLK_EN 0x174 427aff188feSDmitry Baryshkov #define QSERDES_V4_COM_C_READY_STATUS 0x178 428aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_CONFIG 0x17c 4299a24b929SJack Pham #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 430be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_CMN_MISC1 0x19c 431be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0 432be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_CMN_MODE 0x1a4 433be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8 434a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 435a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 436a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 437a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 438be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 439a88c85eeSVinod Koul 440a88c85eeSVinod Koul /* Only for QMP V4 PHY - TX registers */ 441aff188feSDmitry Baryshkov #define QSERDES_V4_TX_CLKBUF_ENABLE 0x08 442aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c 443aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_DRV_LVL 0x14 444aff188feSDmitry Baryshkov #define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c 445aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20 446aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_BAND 0x24 447aff188feSDmitry Baryshkov #define QSERDES_V4_TX_INTERFACE_SELECT 0x2c 4489a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 4499a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 4507b675ba1SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c 45190b65347SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 452aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54 453aff188feSDmitry Baryshkov #define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58 454aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_POL_INV 0x5c 455aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 456a88c85eeSVinod Koul #define QSERDES_V4_TX_LANE_MODE_1 0x84 45790b65347SJonathan Marek #define QSERDES_V4_TX_LANE_MODE_2 0x88 4589a24b929SJack Pham #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 459aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 460aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc 461a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 462fe841d5bSJohan Hovold #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdc 463a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 464a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 465aff188feSDmitry Baryshkov #define QSERDES_V4_TX_VMODE_CTRL1 0xe8 4669a24b929SJack Pham #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 467a88c85eeSVinod Koul 468be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - TX registers */ 469be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 470be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 471be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 472be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 473be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 474be0ddb5dSManivannan Sadhasivam 475a88c85eeSVinod Koul /* Only for QMP V4 PHY - RX registers */ 476a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 477a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 478a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 479a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 480a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 4819a24b929SJack Pham #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 482a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 483a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 4849a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 4859a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 4869a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 4879a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 4889a24b929SJack Pham #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 4896edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 490a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 491a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 492a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_TERM_BW 0x080 4939a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 4949a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 4959a24b929SJack Pham #define QSERDES_V4_RX_GM_CAL 0x0dc 4966edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 497a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 498a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 499a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 500a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 501a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 502a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 5039a24b929SJack Pham #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 504a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 5056edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_SIGDET_ENABLES 0x118 506a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 507a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_LVL 0x120 508a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 509a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_BAND 0x128 510a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 511a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 512a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 513a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 514a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 515a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 516a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 517a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 518a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 519a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 520a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 521a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 522a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 523a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 524a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 5259a24b929SJack Pham #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 5269a24b929SJack Pham #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 527a88c85eeSVinod Koul #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 5289a24b929SJack Pham #define QSERDES_V4_RX_VTH_CODE 0x1c4 529a88c85eeSVinod Koul 530aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 531aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 532aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 533aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 534aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 535aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 536aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 537aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 538aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 539aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 540aff188feSDmitry Baryshkov 541be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - RX registers */ 542be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 543be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 544be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 545be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_3 0x110 546be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 547be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 548be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 549be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 550be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 551be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 552be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 553be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 554be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 555be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 556be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 557be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 558be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 559be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 560be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 561be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 562be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 563be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 564be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 565be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 566be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 567be0ddb5dSManivannan Sadhasivam 5689a24b929SJack Pham /* Only for QMP V4 PHY - UFS PCS registers */ 56978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PHY_START 0x000 57078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 57178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_SW_RESET 0x008 57278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 57378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 57478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 57578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 57678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 57778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 57878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 57978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 58078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 58178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 58278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 58378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 58478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 58578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 58678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 58778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 58878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 589a88c85eeSVinod Koul 590909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 591909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 592909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 593909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 594909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 595909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 596909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 597909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 598909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 599909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 600909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 601909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 602909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 603909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 604909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 605909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 606909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 607909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 608909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 609909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 610909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 611909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 612909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 613909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 614909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 615909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 616909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 617909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 618909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 619909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 620909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 621909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 622909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 623909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 624909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 625909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 626909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 627909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 628909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 629909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 630909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 631909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 632909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 633909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 634909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 635909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 636909a5c78SBjorn Andersson 637909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 638909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 639909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 640909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 641909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 642909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 643909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 644909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 645909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 646909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 647909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 648909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 649909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 650909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 651909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 652909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 653909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 654909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 655909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 656909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 657909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 658909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 659909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 660909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 661909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 662909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 663909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 664909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 665909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 666909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 667909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 668909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 669909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 670909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 671909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 672909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 673909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 674909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 675909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 676909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 677909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 678909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 679909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 680909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 681909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 682909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 683909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 684909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 685909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 686909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 687909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 688909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 689909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 690909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 691909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 692909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 693909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 694909a5c78SBjorn Andersson 695909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 696909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 697909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 698909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 699909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 700909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 701909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 702909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 703909a5c78SBjorn Andersson 7049a24b929SJack Pham /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 7059a24b929SJack Pham #define QPHY_V4_PCS_SW_RESET 0x000 7069a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID0 0x004 7079a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID1 0x008 7089a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID2 0x00c 7099a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID3 0x010 7109a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS1 0x014 7119a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS2 0x018 7129a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS3 0x01c 7139a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS4 0x020 7149a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS5 0x024 7159a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS6 0x028 7169a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS7 0x02c 7179a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 7189a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 7199a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 7209a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 7219a24b929SJack Pham #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 7229a24b929SJack Pham #define QPHY_V4_PCS_START_CONTROL 0x044 7239a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 7249a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 7259a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 7269a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 7279a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 7289a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 7299a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 7309a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 7319a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 7329a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 7339a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 7349a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 7359a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 7369a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 7379a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 7389a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 7399a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 7409a24b929SJack Pham #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 7419a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 7429a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 7439a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL1 0x098 7449a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 7459a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 7469a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 7479a24b929SJack Pham #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 7489a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 7499a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 7509a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 7519a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 7529a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 7539a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 7549a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 7559a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 7569a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 7579a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 7589a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 7599a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 7609a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 7619a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 7629a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 7639a24b929SJack Pham #define QPHY_V4_PCS_BIST_CTRL 0x0e8 7649a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 7659a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 7669a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 7679a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 7689a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 7699a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT3 0x100 7709a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT4 0x104 7719a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT5 0x108 7729a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT6 0x10c 7739a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT7 0x110 7749a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT8 0x114 7759a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT9 0x118 7769a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT10 0x11c 7779a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT11 0x120 7789a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT12 0x124 7799a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT13 0x128 7809a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT14 0x12c 7819a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT15 0x130 7829a24b929SJack Pham #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 7839a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 7849a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 7859a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 7869a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 7879a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 7889a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 7899a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 7909a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 7919a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 7929a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 7939a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 7949a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 7959a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 7969a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 7979a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 7989a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 7999a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 8009a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 8019a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 8029a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 8039a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 8049a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 8059a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 8069a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 8079a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 8089a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 8099a24b929SJack Pham #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 8109a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 8119a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 8129a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 8139a24b929SJack Pham #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 8149a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 8159a24b929SJack Pham #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 8169a24b929SJack Pham #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 8179a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 8189a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 8199a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 8209a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 8219a24b929SJack Pham #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 8229a24b929SJack Pham #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 8239a24b929SJack Pham #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 8249a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 8259a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 8269a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 8279a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 8289a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 829fc646236SDmitry Baryshkov 830fc646236SDmitry Baryshkov /* Only for QMP V4 PHY - USB3 PCS registers */ 831fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000 832fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 833fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 834fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 835fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 836fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 837fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 838fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c 839fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 840fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 841fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028 842fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c 843fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030 844fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034 845fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038 846fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c 847fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040 848fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044 849fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048 850fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c 851fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050 852fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054 853fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058 8549a24b929SJack Pham 855be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 856be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 857be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 858be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 859be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 860be0ddb5dSManivannan Sadhasivam 8619a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 8629a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 8639a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 8649a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 8659a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 8669a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 8679a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 8689a24b929SJack Pham 8696edf7700SManivannan Sadhasivam /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 8706edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 8716edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 8726edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 8736edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 8746edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 8756edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 8766edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 87760f23414SDmitry Baryshkov #define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0 8786edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 8796edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 8806edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 8816edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 8826edf7700SManivannan Sadhasivam 883be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 884be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 885be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 886be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 887be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 888be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 889be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 890be0ddb5dSManivannan Sadhasivam 891920abc10SVinod Koul /* Only for QMP V5 PHY - QSERDES COM registers */ 892107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_EN_CENTER 0x010 893107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_PER1 0x01c 894107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_PER2 0x020 895107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 896107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 897107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 898107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 8992c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 900107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_CLK_ENABLE1 0x048 901107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 902920abc10SVinod Koul #define QSERDES_V5_COM_PLL_IVCO 0x058 903920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 904920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 905920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c 906920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 907920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 908920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 909920abc10SVinod Koul #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 910920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 9112c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 912920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac 913920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 914920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 915920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 91674acf0eeSJohan Hovold #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc 917920abc10SVinod Koul #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 918107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc 919107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 920107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 921107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 922107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc 923107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 924920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c 925107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 926107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 927107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 928107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c 929920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 930107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_CLK_SELECT 0x154 931920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_SEL 0x158 932920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c 9332c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 934107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c 9352c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CORE_CLK_EN 0x174 9362c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CMN_CONFIG 0x17c 9372c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CMN_MISC1 0x19c 938488987b2SDmitry Baryshkov #define QSERDES_V5_COM_CMN_MODE 0x1a0 939488987b2SDmitry Baryshkov #define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4 9402c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8 941920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 942920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 943920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 944920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 94574acf0eeSJohan Hovold #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 946920abc10SVinod Koul 94710c744d4SJack Pham /* Only for QMP V5 PHY - TX registers */ 94810c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 94910c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38 95010c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c 95110c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40 95210c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_1 0x84 95310c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_2 0x88 95410c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_3 0x8c 95510c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_4 0x90 95610c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_5 0x94 95710c744d4SJack Pham #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4 95810c744d4SJack Pham #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0 95910c744d4SJack Pham #define QSERDES_V5_TX_PI_QEC_CTRL 0xe4 960920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 961920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 962920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 963920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 96410c744d4SJack Pham 9652c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - TX registers */ 9662c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 9672c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 9682c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 9692c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 9702c91bf6bSDmitry Baryshkov 97110c744d4SJack Pham /* Only for QMP V5 PHY - RX registers */ 97210c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 97310c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 97410c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 97510c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 97610c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 97710c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 97810c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 97910c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 98010c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c 98110c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 98210c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 98310c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 98410c744d4SJack Pham #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 98510c744d4SJack Pham #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 98610c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 98710c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 98810c744d4SJack Pham #define QSERDES_V5_RX_RX_TERM_BW 0x080 989107ba9bfSDmitry Baryshkov #define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc 99010c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 99110c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 99210c744d4SJack Pham #define QSERDES_V5_RX_GM_CAL 0x0dc 99310c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 99410c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 99510c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 99610c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 99710c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 99810c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 99910c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 100010c744d4SJack Pham #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 100110c744d4SJack Pham #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 100210c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 100310c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c 100410c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_LVL 0x120 100510c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 100610c744d4SJack Pham #define QSERDES_V5_RX_RX_BAND 0x128 100710c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 100810c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 100910c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 101010c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 101110c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c 101210c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 101310c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 101410c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 101510c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c 101610c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 101710c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 101810c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 101910c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 102010c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 102110c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 102210c744d4SJack Pham #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 102310c744d4SJack Pham #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 102410c744d4SJack Pham #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 102510c744d4SJack Pham #define QSERDES_V5_RX_VTH_CODE 0x1b0 102610c744d4SJack Pham 10272c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - RX registers */ 10282c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 10292c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c 10302c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 10312c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c 10322c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 10332c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c 10342c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_3 0x090 10352c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 10362c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 10372c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 10382c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc 10392c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_GM_CAL 0x0ec 10402c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 10412c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 10422c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 10432c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c 10442c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 10452c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 10462c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c 10472c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 10482c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 10492c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 10502c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c 10512c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 10522c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 10532c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 10542c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c 10552c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 10562c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 10572c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 10582c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac 10592c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 10602c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 10612c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 10622c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 10632c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 10642c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc 10652c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 10662c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 10672c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 10682c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 10692c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 10702c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 10712c91bf6bSDmitry Baryshkov 1072107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - USB/PCIe PCS registers */ 1073107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc 10742c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 1075107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 1076107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 10772c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 10782c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 1079107ba9bfSDmitry Baryshkov 1080107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - PCS_PCIE registers */ 1081107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 1082107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 1083107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 1084107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 1085107ba9bfSDmitry Baryshkov 10862c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - PCIe PCS registers */ 10872c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 10882c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 10892c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 10902c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 10912c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 10922c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 10932c91bf6bSDmitry Baryshkov 1094920abc10SVinod Koul /* Only for QMP V5 PHY - UFS PCS registers */ 1095920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 1096920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 1097920abc10SVinod Koul #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 1098920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 1099920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 1100920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 1101920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 1102920abc10SVinod Koul #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 1103920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 1104920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 1105920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 1106920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 1107920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 1108920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 1109920abc10SVinod Koul #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 1110920abc10SVinod Koul 111110c744d4SJack Pham /* Only for QMP V5 PHY - USB3 have different offsets than V4 */ 1112fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000 1113fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 1114fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 1115fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 1116fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 1117fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 1118fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 1119fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c 1120fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 1121fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 1122fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028 1123fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c 1124fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030 1125fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034 1126fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038 1127fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c 1128fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040 1129fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044 1130fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048 1131fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c 1132fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050 1133fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054 1134fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058 1135fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c 1136fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060 113710c744d4SJack Pham 1138e2248617SManu Gautam #endif 1139