1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 9e2248617SManu Gautam /* Only for QMP V2 PHY - QSERDES COM registers */ 10e2248617SManu Gautam #define QSERDES_COM_BG_TIMER 0x00c 11e2248617SManu Gautam #define QSERDES_COM_SSC_EN_CENTER 0x010 12e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER1 0x014 13e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER2 0x018 14e2248617SManu Gautam #define QSERDES_COM_SSC_PER1 0x01c 15e2248617SManu Gautam #define QSERDES_COM_SSC_PER2 0x020 16e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE1 0x024 17e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE2 0x028 18e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 19e2248617SManu Gautam #define QSERDES_COM_CLK_ENABLE1 0x038 20e2248617SManu Gautam #define QSERDES_COM_SYS_CLK_CTRL 0x03c 21e2248617SManu Gautam #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 22e2248617SManu Gautam #define QSERDES_COM_PLL_IVCO 0x048 23e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 24e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 25e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 26e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 27e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 28e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 29e2248617SManu Gautam #define QSERDES_COM_BG_TRIM 0x070 30e2248617SManu Gautam #define QSERDES_COM_CLK_EP_DIV 0x074 31e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE0 0x078 32e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE1 0x07c 33e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 34e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 35e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 36e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 37e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 38e2248617SManu Gautam #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 39e2248617SManu Gautam #define QSERDES_COM_RESETSM_CNTRL 0x0b4 40e2248617SManu Gautam #define QSERDES_COM_RESTRIM_CTRL 0x0bc 41e2248617SManu Gautam #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 42e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_EN 0x0c8 43e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 44e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE0 0x0d0 45e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE1 0x0d4 46e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 47e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 48e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 49e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 50e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 51e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 52e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 53e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 54e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 55e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 56e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_CTRL 0x124 57e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_MAP 0x128 58e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 59e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 60e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 61e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 62e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 63e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 64e2248617SManu Gautam #define QSERDES_COM_BG_CTRL 0x170 65e2248617SManu Gautam #define QSERDES_COM_CLK_SELECT 0x174 66e2248617SManu Gautam #define QSERDES_COM_HSCLK_SEL 0x178 67e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV 0x184 68e2248617SManu Gautam #define QSERDES_COM_CORE_CLK_EN 0x18c 69e2248617SManu Gautam #define QSERDES_COM_C_READY_STATUS 0x190 70e2248617SManu Gautam #define QSERDES_COM_CMN_CONFIG 0x194 71e2248617SManu Gautam #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 72e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS0 0x1a0 73e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS1 0x1a4 74e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS2 0x1a8 75e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS3 0x1ac 76e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 77e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 78e2248617SManu Gautam 79e2248617SManu Gautam /* Only for QMP V2 PHY - TX registers */ 80e2248617SManu Gautam #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 81e2248617SManu Gautam #define QSERDES_TX_DEBUG_BUS_SEL 0x064 82e2248617SManu Gautam #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 83e2248617SManu Gautam #define QSERDES_TX_LANE_MODE 0x094 84e2248617SManu Gautam #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 85e2248617SManu Gautam 86e2248617SManu Gautam /* Only for QMP V2 PHY - RX registers */ 87e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 88e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN 0x01c 89e2248617SManu Gautam #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 90e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 91e2248617SManu Gautam #define QSERDES_RX_RX_TERM_BW 0x090 92e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 93e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 94e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 95e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 96e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 97e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 98e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 99e2248617SManu Gautam #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 100e2248617SManu Gautam #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 101e2248617SManu Gautam #define QSERDES_RX_SIGDET_ENABLES 0x110 102e2248617SManu Gautam #define QSERDES_RX_SIGDET_CNTRL 0x114 103e2248617SManu Gautam #define QSERDES_RX_SIGDET_LVL 0x118 104e2248617SManu Gautam #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 105e2248617SManu Gautam #define QSERDES_RX_RX_BAND 0x120 106e2248617SManu Gautam #define QSERDES_RX_RX_INTERFACE_MODE 0x12c 107e2248617SManu Gautam 108e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 109e2248617SManu Gautam #define QPHY_POWER_DOWN_CONTROL 0x04 110e2248617SManu Gautam #define QPHY_TXDEEMPH_M6DB_V0 0x24 111e2248617SManu Gautam #define QPHY_TXDEEMPH_M3P5DB_V0 0x28 112e2248617SManu Gautam #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 113e2248617SManu Gautam #define QPHY_RX_IDLE_DTCT_CNTRL 0x58 114e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG1 0x60 115e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG2 0x64 116e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG4 0x6c 117e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG1 0x80 118e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG2 0x84 119e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG3 0x88 120e2248617SManu Gautam #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 121e2248617SManu Gautam #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 122e2248617SManu Gautam #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 123e2248617SManu Gautam #define QPHY_OSC_DTCT_ACTIONS 0x1AC 124e2248617SManu Gautam #define QPHY_RX_SIGDET_LVL 0x1D8 125e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC 126e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 127e2248617SManu Gautam 1289c7761a3SManu Gautam /* Only for QMP V3 PHY - DP COM registers */ 1299c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 1309c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 1319c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 1329c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 1339c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 1349c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 1359c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 1369c7761a3SManu Gautam 1379c7761a3SManu Gautam /* Only for QMP V3 PHY - QSERDES COM registers */ 1389c7761a3SManu Gautam #define QSERDES_V3_COM_BG_TIMER 0x00c 1399c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 1409c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 1419c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 1429c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER1 0x01c 1439c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER2 0x020 1449c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 1459c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 1469c7761a3SManu Gautam #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 1479c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_ENABLE1 0x038 1489c7761a3SManu Gautam #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 1499c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 1509c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_IVCO 0x048 1519c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 1529c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 1539c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 1549c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 1559c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 1569c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 1579c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 1589c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 1599c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 1609c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 1619c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 1629c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 1639c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 1649c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 1659c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 1669c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 1679c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 1689c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 1699c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 1709c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 1719c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 1729c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 1739c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 1749c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 1759c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 1769c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 177a51969faSJeffrey Hugo #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 1789c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 1799c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 1809c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 1819c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 1829c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 1839c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 1849c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 1859c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 1869c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 1879c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 188cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 189cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 1909c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 1919c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 1929c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_SELECT 0x138 1939c7761a3SManu Gautam #define QSERDES_V3_COM_HSCLK_SEL 0x13c 1949c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 1959c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 1969c7761a3SManu Gautam #define QSERDES_V3_COM_CORE_CLK_EN 0x154 1979c7761a3SManu Gautam #define QSERDES_V3_COM_C_READY_STATUS 0x158 1989c7761a3SManu Gautam #define QSERDES_V3_COM_CMN_CONFIG 0x15c 1999c7761a3SManu Gautam #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 2009c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS0 0x168 2019c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 2029c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS2 0x170 2039c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS3 0x174 2049c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 205a51969faSJeffrey Hugo #define QSERDES_V3_COM_CMN_MODE 0x184 2069c7761a3SManu Gautam 2079c7761a3SManu Gautam /* Only for QMP V3 PHY - TX registers */ 2089c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 2099c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 2109c7761a3SManu Gautam #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 2119c7761a3SManu Gautam #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 2129c7761a3SManu Gautam #define QSERDES_V3_TX_LANE_MODE_1 0x08c 2139c7761a3SManu Gautam #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 2149c7761a3SManu Gautam 2159c7761a3SManu Gautam /* Only for QMP V3 PHY - RX registers */ 216a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 2179c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 2189c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 219cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 220cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 221cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 2229c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 2239c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 224cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 225a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 226cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 2279c7761a3SManu Gautam #define QSERDES_V3_RX_RX_TERM_BW 0x07c 228f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 229f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 2309c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 2319c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 2329c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 2339c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 2349c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 2359c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 2369c7761a3SManu Gautam #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 2379c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_ENABLES 0x100 2389c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_CNTRL 0x104 2399c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_LVL 0x108 2409c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 2419c7761a3SManu Gautam #define QSERDES_V3_RX_RX_BAND 0x110 2429c7761a3SManu Gautam #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 243f6721e5cSManu Gautam #define QSERDES_V3_RX_RX_MODE_00 0x164 24473d7ec89SMarc Gonzalez #define QSERDES_V3_RX_RX_MODE_01 0x168 2459c7761a3SManu Gautam 2469c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 2479c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 2489c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 2499c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 2509c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 2519c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 2529c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 2539c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 254cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 255cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 2569c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 2579c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 2589c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 2599c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 2609c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 2619c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 2629c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 2639c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 2649c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 2659c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 2669c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 2679c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 2689c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 2699c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 2709c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 2719c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 2729c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 2739c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 2749c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 2759c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 2769c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 2779c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 2789c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 2799c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 2809c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 2819c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 2829c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 2839c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 28473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 2859c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 2869c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 2879c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 2889c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 2899c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 2909c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 2919c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 2929c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 293cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 294cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 295cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 296cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 29773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 29873d7ec89SMarc Gonzalez #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 29973d7ec89SMarc Gonzalez #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 300cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 301cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 3029c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 30373d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 30473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 305f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 306f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 3079c7761a3SManu Gautam 308ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 309ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 31073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 31173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 31273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 31373d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 31473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 315ac0d2399SManu Gautam 316a88c85eeSVinod Koul /* Only for QMP V4 PHY - QSERDES COM registers */ 317a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_IVCO 0x058 318a88c85eeSVinod Koul #define QSERDES_V4_COM_CMN_IPTRIM 0x060 319a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 320a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 321a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 322a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 323a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 324a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 325a88c85eeSVinod Koul #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 326a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 327a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 328a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 329a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 330a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 331a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 332a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 333a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 334a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 335a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_SEL 0x158 336a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 337a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 338a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 339a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 340a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 341a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 342a88c85eeSVinod Koul 343a88c85eeSVinod Koul /* Only for QMP V4 PHY - TX registers */ 344a88c85eeSVinod Koul #define QSERDES_V4_TX_LANE_MODE_1 0x84 345a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 346a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC 347a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 348a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 349a88c85eeSVinod Koul #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 350a88c85eeSVinod Koul 351a88c85eeSVinod Koul /* Only for QMP V4 PHY - RX registers */ 352a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 353a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 354a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 355a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 356a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 357a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 358a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 359a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 360a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 361a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_TERM_BW 0x080 362a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 363a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 364a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 365a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 366a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 367a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 368a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 369a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 370a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_LVL 0x120 371a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 372a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_BAND 0x128 373a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 374a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 375a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 376a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 377a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 378a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 379a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 380a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 381a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 382a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 383a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 384a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 385a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 386a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 387a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 388a88c85eeSVinod Koul #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 389a88c85eeSVinod Koul 390a88c85eeSVinod Koul /* Only for QMP V4 PHY - PCS registers */ 391a88c85eeSVinod Koul #define QPHY_V4_PHY_START 0x000 392a88c85eeSVinod Koul #define QPHY_V4_POWER_DOWN_CONTROL 0x004 393a88c85eeSVinod Koul #define QPHY_V4_SW_RESET 0x008 394a88c85eeSVinod Koul #define QPHY_V4_TIMER_20US_CORECLK_STEPS_MSB 0x00c 395a88c85eeSVinod Koul #define QPHY_V4_TIMER_20US_CORECLK_STEPS_LSB 0x010 396a88c85eeSVinod Koul #define QPHY_V4_PLL_CNTL 0x02c 397a88c85eeSVinod Koul #define QPHY_V4_TX_LARGE_AMP_DRV_LVL 0x030 398a88c85eeSVinod Koul #define QPHY_V4_TX_SMALL_AMP_DRV_LVL 0x038 399a88c85eeSVinod Koul #define QPHY_V4_BIST_FIXED_PAT_CTRL 0x060 400a88c85eeSVinod Koul #define QPHY_V4_TX_HSGEAR_CAPABILITY 0x074 401a88c85eeSVinod Koul #define QPHY_V4_RX_HSGEAR_CAPABILITY 0x0b4 402a88c85eeSVinod Koul #define QPHY_V4_DEBUG_BUS_CLKSEL 0x124 403a88c85eeSVinod Koul #define QPHY_V4_LINECFG_DISABLE 0x148 404a88c85eeSVinod Koul #define QPHY_V4_RX_MIN_HIBERN8_TIME 0x150 405a88c85eeSVinod Koul #define QPHY_V4_RX_SIGDET_CTRL2 0x158 406a88c85eeSVinod Koul #define QPHY_V4_TX_PWM_GEAR_BAND 0x160 407a88c85eeSVinod Koul #define QPHY_V4_TX_HS_GEAR_BAND 0x168 408a88c85eeSVinod Koul #define QPHY_V4_PCS_READY_STATUS 0x180 409a88c85eeSVinod Koul #define QPHY_V4_TX_MID_TERM_CTRL1 0x1d8 410a88c85eeSVinod Koul #define QPHY_V4_MULTI_LANE_CTRL1 0x1e0 411a88c85eeSVinod Koul 412909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 413909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 414909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 415909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 416909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 417909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 418909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 419909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 420909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 421909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 422909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 423909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 424909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 425909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 426909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 427909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 428909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 429909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 430909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 431909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 432909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 433909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 434909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 435909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 436909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 437909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 438909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 439909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 440909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 441909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 442909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 443909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 444909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 445909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 446909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 447909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 448909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 449909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 450909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 451909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 452909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 453909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 454909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 455909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 456909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 457909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 458909a5c78SBjorn Andersson 459909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 460909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 461909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 462909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 463909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 464909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 465909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 466909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 467909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 468909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 469909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 470909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 471909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 472909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 473909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 474909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 475909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 476909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 477909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 478909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 479909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 480909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 481909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 482909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 483909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 484909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 485909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 486909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 487909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 488909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 489909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 490909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 491909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 492909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 493909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 494909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 495909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 496909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 497909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 498909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 499909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 500909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 501909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 502909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 503909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 504909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 505909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 506909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 507909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 508909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 509909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 510909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 511909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 512909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 513909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 514909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 515909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 516909a5c78SBjorn Andersson 517909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 518909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 519909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 520909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 521909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 522909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 523909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 524909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 525909a5c78SBjorn Andersson 526e2248617SManu Gautam #endif 527