1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 99e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com.h" 109e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx.h" 119e1bae6dSDmitry Baryshkov 12a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v3.h" 13a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v3.h" 14a7fc833eSDmitry Baryshkov 1532d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v4.h" 1632d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v4.h" 1732d2cf53SDmitry Baryshkov 18f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v5.h" 19f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v5.h" 20f1f923adSDmitry Baryshkov 21147924ffSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-pll.h" 22520264dbSSelvam Sathappan Periakaruppan 235ae11aa4SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v2.h" 24e2248617SManu Gautam 2556a1fa09SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v3.h" 2656a1fa09SDmitry Baryshkov #include "phy-qcom-qmp-pcs-misc-v3.h" 2756a1fa09SDmitry Baryshkov 2841ad371fSDmitry Baryshkov #include "phy-qcom-qmp-pcs-v4.h" 2941ad371fSDmitry Baryshkov #include "phy-qcom-qmp-pcs-pcie-v4.h" 3041ad371fSDmitry Baryshkov #include "phy-qcom-qmp-pcs-usb-v4.h" 3141ad371fSDmitry Baryshkov #include "phy-qcom-qmp-pcs-ufs-v4.h" 3241ad371fSDmitry Baryshkov 33b7a2f882SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v5.h" 34b7a2f882SDmitry Baryshkov #include "phy-qcom-qmp-pcs-pcie-v5.h" 35b7a2f882SDmitry Baryshkov #include "phy-qcom-qmp-pcs-usb-v5.h" 36b7a2f882SDmitry Baryshkov #include "phy-qcom-qmp-pcs-ufs-v5.h" 37b7a2f882SDmitry Baryshkov 38*87d71378SDmitry Baryshkov #include "phy-qcom-qmp-pcie-qhp.h" 39*87d71378SDmitry Baryshkov 409a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 419c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 429c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 439c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 449c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 459c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 469c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 479c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 489c7761a3SManu Gautam 49a7fc833eSDmitry Baryshkov /* QSERDES V3 COM bits */ 5052e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 5152e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 5252e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 5352e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 5452e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 5552e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 5652e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 579c7761a3SManu Gautam 58a7fc833eSDmitry Baryshkov /* QSERDES V3 TX bits */ 5952e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 6052e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 6152e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 6252e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 6352e013d0SStephen Boyd 645c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 655c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 665c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 675c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 685c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 695c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 705c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 7152e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 7252e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 7352e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 7452e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 7552e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 7652e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 7752e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 785c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 795c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 805c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 815c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 825c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 835c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 845c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 855c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 865c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 875c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 885c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 8952e013d0SStephen Boyd 905c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 9152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 9252e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 9352e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 9452e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 9552e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 9652e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 9752e013d0SStephen Boyd 9852e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 9952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 10052e013d0SStephen Boyd 10152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 10252e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 10352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 10452e013d0SStephen Boyd 10552e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 10652e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 10752e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 10852e013d0SStephen Boyd 10952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 11052e013d0SStephen Boyd 111a88c85eeSVinod Koul 112be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - TX registers */ 113be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 114be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 115be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 116be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 117be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 118be0ddb5dSManivannan Sadhasivam 119aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 120aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 121aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 122aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 123aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 124aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 125aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 126aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 127aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 128aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 129aff188feSDmitry Baryshkov 130be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - RX registers */ 131be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 132be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 133be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 134be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_3 0x110 135be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 136be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 137be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 138be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 139be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 140be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 141be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 142be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 143be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 144be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 145be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 146be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 147be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 148be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 149be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 150be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 151be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 152be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 153be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 154be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 155be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 156be0ddb5dSManivannan Sadhasivam 157be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 158be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 159be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 160be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 161be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 162be0ddb5dSManivannan Sadhasivam 1639a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 1649a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 1659a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 1669a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 1679a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 1689a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 1699a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 1709a24b929SJack Pham 171be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 172be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 173be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 174be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 175be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 176be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 177be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 178be0ddb5dSManivannan Sadhasivam 1792c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - TX registers */ 1802c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 1812c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 1822c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 1832c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 1842c91bf6bSDmitry Baryshkov 1852c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - RX registers */ 1862c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 1872c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c 1882c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 1892c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c 1902c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 1912c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c 1922c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_3 0x090 1932c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 1942c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 1952c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 1962c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc 1972c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_GM_CAL 0x0ec 1982c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 1992c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 2002c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 2012c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c 2022c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 2032c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 2042c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c 2052c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 2062c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 2072c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 2082c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c 2092c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 2102c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 2112c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 2122c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c 2132c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 2142c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 2152c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 2162c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac 2172c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 2182c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 2192c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 2202c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 2212c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 2222c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc 2232c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 2242c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 2252c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 2262c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 2272c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 2282c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 2292c91bf6bSDmitry Baryshkov 2302c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - PCIe PCS registers */ 2312c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 2322c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 2332c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 2342c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 2352c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 2362c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 2372c91bf6bSDmitry Baryshkov 238e2248617SManu Gautam #endif 239