1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 9e2248617SManu Gautam /* Only for QMP V2 PHY - QSERDES COM registers */ 10e2248617SManu Gautam #define QSERDES_COM_BG_TIMER 0x00c 11e2248617SManu Gautam #define QSERDES_COM_SSC_EN_CENTER 0x010 12e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER1 0x014 13e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER2 0x018 14e2248617SManu Gautam #define QSERDES_COM_SSC_PER1 0x01c 15e2248617SManu Gautam #define QSERDES_COM_SSC_PER2 0x020 16e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE1 0x024 17e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE2 0x028 18e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 19e2248617SManu Gautam #define QSERDES_COM_CLK_ENABLE1 0x038 20e2248617SManu Gautam #define QSERDES_COM_SYS_CLK_CTRL 0x03c 21e2248617SManu Gautam #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 22e2248617SManu Gautam #define QSERDES_COM_PLL_IVCO 0x048 23e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 24e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 25e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 26e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 27e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 28e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 29e2248617SManu Gautam #define QSERDES_COM_BG_TRIM 0x070 30e2248617SManu Gautam #define QSERDES_COM_CLK_EP_DIV 0x074 31e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE0 0x078 32e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE1 0x07c 33e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 34e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 35e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 36e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 37e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 38e2248617SManu Gautam #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 39e2248617SManu Gautam #define QSERDES_COM_RESETSM_CNTRL 0x0b4 40e2248617SManu Gautam #define QSERDES_COM_RESTRIM_CTRL 0x0bc 41e2248617SManu Gautam #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 42e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_EN 0x0c8 43e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 44e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE0 0x0d0 45e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE1 0x0d4 46e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 47e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 48e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 49e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 50e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 51e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 52e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 53e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 54e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 55e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 56e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_CTRL 0x124 57e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_MAP 0x128 58e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 59e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 60e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 61e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 62e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 63e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 64e2248617SManu Gautam #define QSERDES_COM_BG_CTRL 0x170 65e2248617SManu Gautam #define QSERDES_COM_CLK_SELECT 0x174 66e2248617SManu Gautam #define QSERDES_COM_HSCLK_SEL 0x178 67e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV 0x184 68e2248617SManu Gautam #define QSERDES_COM_CORE_CLK_EN 0x18c 69e2248617SManu Gautam #define QSERDES_COM_C_READY_STATUS 0x190 70e2248617SManu Gautam #define QSERDES_COM_CMN_CONFIG 0x194 71e2248617SManu Gautam #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 72e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS0 0x1a0 73e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS1 0x1a4 74e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS2 0x1a8 75e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS3 0x1ac 76e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 77e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 78e2248617SManu Gautam 79e2248617SManu Gautam /* Only for QMP V2 PHY - TX registers */ 80e2248617SManu Gautam #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 81e2248617SManu Gautam #define QSERDES_TX_DEBUG_BUS_SEL 0x064 82e2248617SManu Gautam #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 83e2248617SManu Gautam #define QSERDES_TX_LANE_MODE 0x094 84e2248617SManu Gautam #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 85e2248617SManu Gautam 86e2248617SManu Gautam /* Only for QMP V2 PHY - RX registers */ 87e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 88e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN 0x01c 89e2248617SManu Gautam #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 90e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 91e2248617SManu Gautam #define QSERDES_RX_RX_TERM_BW 0x090 92e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 93e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 94e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 95e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 96e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 97e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 98e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 99e2248617SManu Gautam #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 100e2248617SManu Gautam #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 101e2248617SManu Gautam #define QSERDES_RX_SIGDET_ENABLES 0x110 102e2248617SManu Gautam #define QSERDES_RX_SIGDET_CNTRL 0x114 103e2248617SManu Gautam #define QSERDES_RX_SIGDET_LVL 0x118 104e2248617SManu Gautam #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 105e2248617SManu Gautam #define QSERDES_RX_RX_BAND 0x120 106e2248617SManu Gautam #define QSERDES_RX_RX_INTERFACE_MODE 0x12c 107e2248617SManu Gautam 108e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 109e2248617SManu Gautam #define QPHY_POWER_DOWN_CONTROL 0x04 110e2248617SManu Gautam #define QPHY_TXDEEMPH_M6DB_V0 0x24 111e2248617SManu Gautam #define QPHY_TXDEEMPH_M3P5DB_V0 0x28 112e2248617SManu Gautam #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 113e2248617SManu Gautam #define QPHY_RX_IDLE_DTCT_CNTRL 0x58 114e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG1 0x60 115e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG2 0x64 116e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG4 0x6c 117e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG1 0x80 118e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG2 0x84 119e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG3 0x88 120e2248617SManu Gautam #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 121e2248617SManu Gautam #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 122e2248617SManu Gautam #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 123e2248617SManu Gautam #define QPHY_OSC_DTCT_ACTIONS 0x1AC 124e2248617SManu Gautam #define QPHY_RX_SIGDET_LVL 0x1D8 125e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC 126e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 127e2248617SManu Gautam 1289a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 1299c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 1309c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 1319c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 1329c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 1339c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 1349c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 1359c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 1369c7761a3SManu Gautam 1379c7761a3SManu Gautam /* Only for QMP V3 PHY - QSERDES COM registers */ 1389c7761a3SManu Gautam #define QSERDES_V3_COM_BG_TIMER 0x00c 1399c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 1409c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 1419c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 1429c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER1 0x01c 1439c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER2 0x020 1449c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 1459c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 1469c7761a3SManu Gautam #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 1479c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_ENABLE1 0x038 1489c7761a3SManu Gautam #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 1499c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 1509c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_IVCO 0x048 1519c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 1529c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 1539c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 1549c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 1559c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 1569c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 1579c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 1589c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 1599c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 1609c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 1619c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 1629c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 1639c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 1649c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 1659c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 1669c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 1679c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 1689c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 1699c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 1709c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 1719c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 1729c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 1739c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 1749c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 1759c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 1769c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 177a51969faSJeffrey Hugo #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 1789c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 1799c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 1809c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 1819c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 1829c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 1839c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 1849c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 1859c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 1869c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 1879c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 188cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 189cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 1909c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 1919c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 1929c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_SELECT 0x138 1939c7761a3SManu Gautam #define QSERDES_V3_COM_HSCLK_SEL 0x13c 1949c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 1959c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 1969c7761a3SManu Gautam #define QSERDES_V3_COM_CORE_CLK_EN 0x154 1979c7761a3SManu Gautam #define QSERDES_V3_COM_C_READY_STATUS 0x158 1989c7761a3SManu Gautam #define QSERDES_V3_COM_CMN_CONFIG 0x15c 1999c7761a3SManu Gautam #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 2009c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS0 0x168 2019c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 2029c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS2 0x170 2039c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS3 0x174 2049c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 205a51969faSJeffrey Hugo #define QSERDES_V3_COM_CMN_MODE 0x184 2069c7761a3SManu Gautam 2079c7761a3SManu Gautam /* Only for QMP V3 PHY - TX registers */ 2089c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 2099c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 2109c7761a3SManu Gautam #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 2119c7761a3SManu Gautam #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 2129c7761a3SManu Gautam #define QSERDES_V3_TX_LANE_MODE_1 0x08c 2139c7761a3SManu Gautam #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 2149c7761a3SManu Gautam 2159c7761a3SManu Gautam /* Only for QMP V3 PHY - RX registers */ 216a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 2179c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 2189c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 219cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 220cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 221cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 2229c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 2239c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 224cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 225a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 226cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 2279c7761a3SManu Gautam #define QSERDES_V3_RX_RX_TERM_BW 0x07c 228f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 229f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 2309c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 2319c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 2329c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 2339c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 2349c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 2359c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 2369c7761a3SManu Gautam #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 2379c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_ENABLES 0x100 2389c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_CNTRL 0x104 2399c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_LVL 0x108 2409c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 2419c7761a3SManu Gautam #define QSERDES_V3_RX_RX_BAND 0x110 2429c7761a3SManu Gautam #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 243f6721e5cSManu Gautam #define QSERDES_V3_RX_RX_MODE_00 0x164 24473d7ec89SMarc Gonzalez #define QSERDES_V3_RX_RX_MODE_01 0x168 2459c7761a3SManu Gautam 2469c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 2479c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 2489c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 2499c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 2509c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 2519c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 2529c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 2539c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 254cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 255cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 2569c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 2579c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 2589c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 2599c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 2609c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 2619c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 2629c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 2639c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 2649c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 2659c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 2669c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 2679c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 2689c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 2699c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 2709c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 2719c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 2729c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 2739c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 2749c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 2759c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 2769c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 2779c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 2789c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 2799c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 2809c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 2819c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 2829c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 2839c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 28473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 2859c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 2869c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 2879c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 2889c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 2899c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 2909c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 2919c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 2929c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 293cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 294cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 295cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 296cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 29773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 29873d7ec89SMarc Gonzalez #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 29973d7ec89SMarc Gonzalez #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 300cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 301cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 3029c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 30373d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 30473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 305f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 306f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 3079c7761a3SManu Gautam 308ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 309ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 31073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 31173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 31273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 31373d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 31473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 315ac0d2399SManu Gautam 316a88c85eeSVinod Koul /* Only for QMP V4 PHY - QSERDES COM registers */ 3179a24b929SJack Pham #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 3189a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER1 0x01c 3199a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER2 0x020 3209a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 3219a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 3229a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 3239a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 3249a24b929SJack Pham #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 325a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_IVCO 0x058 326a88c85eeSVinod Koul #define QSERDES_V4_COM_CMN_IPTRIM 0x060 327a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 328a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 329a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 330a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 331a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 332a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 333a88c85eeSVinod Koul #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 334a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 335a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 336a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 337a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 338a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 339a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 340a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 3419a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 3429a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 3439a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 3449a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 3459a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 3469a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 347a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 3489a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 3499a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 3509a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 3519a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 352a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 353a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_SEL 0x158 354a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 3559a24b929SJack Pham #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 3569a24b929SJack Pham #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 357a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 358a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 359a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 360a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 361a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 362a88c85eeSVinod Koul 363a88c85eeSVinod Koul /* Only for QMP V4 PHY - TX registers */ 3649a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 3659a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 366a88c85eeSVinod Koul #define QSERDES_V4_TX_LANE_MODE_1 0x84 3679a24b929SJack Pham #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 368a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 369a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC 370a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 371a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 372a88c85eeSVinod Koul #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 3739a24b929SJack Pham #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 374a88c85eeSVinod Koul 375a88c85eeSVinod Koul /* Only for QMP V4 PHY - RX registers */ 376a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 377a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 378a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 379a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 380a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 3819a24b929SJack Pham #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 382a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 383a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 3849a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 3859a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 3869a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 3879a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 3889a24b929SJack Pham #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 389a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 390a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 391a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_TERM_BW 0x080 3929a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 3939a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 3949a24b929SJack Pham #define QSERDES_V4_RX_GM_CAL 0x0dc 395a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 396a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 397a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 398a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 399a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 400a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 4019a24b929SJack Pham #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 402a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 403a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 404a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_LVL 0x120 405a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 406a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_BAND 0x128 407a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 408a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 409a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 410a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 411a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 412a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 413a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 414a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 415a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 416a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 417a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 418a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 419a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 420a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 421a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 4229a24b929SJack Pham #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 4239a24b929SJack Pham #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 424a88c85eeSVinod Koul #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 4259a24b929SJack Pham #define QSERDES_V4_RX_VTH_CODE 0x1c4 426a88c85eeSVinod Koul 4279a24b929SJack Pham /* Only for QMP V4 PHY - UFS PCS registers */ 42878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PHY_START 0x000 42978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 43078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_SW_RESET 0x008 43178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 43278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 43378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 43478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 43578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 43678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 43778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 43878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 43978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 44078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 44178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 44278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 44378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 44478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 44578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 44678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 44778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 448a88c85eeSVinod Koul 449909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 450909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 451909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 452909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 453909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 454909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 455909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 456909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 457909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 458909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 459909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 460909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 461909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 462909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 463909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 464909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 465909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 466909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 467909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 468909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 469909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 470909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 471909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 472909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 473909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 474909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 475909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 476909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 477909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 478909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 479909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 480909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 481909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 482909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 483909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 484909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 485909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 486909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 487909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 488909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 489909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 490909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 491909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 492909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 493909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 494909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 495909a5c78SBjorn Andersson 496909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 497909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 498909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 499909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 500909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 501909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 502909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 503909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 504909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 505909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 506909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 507909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 508909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 509909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 510909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 511909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 512909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 513909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 514909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 515909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 516909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 517909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 518909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 519909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 520909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 521909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 522909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 523909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 524909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 525909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 526909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 527909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 528909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 529909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 530909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 531909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 532909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 533909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 534909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 535909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 536909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 537909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 538909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 539909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 540909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 541909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 542909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 543909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 544909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 545909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 546909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 547909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 548909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 549909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 550909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 551909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 552909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 553909a5c78SBjorn Andersson 554909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 555909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 556909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 557909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 558909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 559909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 560909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 561909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 562909a5c78SBjorn Andersson 5639a24b929SJack Pham /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 5649a24b929SJack Pham #define QPHY_V4_PCS_SW_RESET 0x000 5659a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID0 0x004 5669a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID1 0x008 5679a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID2 0x00c 5689a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID3 0x010 5699a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS1 0x014 5709a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS2 0x018 5719a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS3 0x01c 5729a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS4 0x020 5739a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS5 0x024 5749a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS6 0x028 5759a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS7 0x02c 5769a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 5779a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 5789a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 5799a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 5809a24b929SJack Pham #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 5819a24b929SJack Pham #define QPHY_V4_PCS_START_CONTROL 0x044 5829a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 5839a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 5849a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 5859a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 5869a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 5879a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 5889a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 5899a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 5909a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 5919a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 5929a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 5939a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 5949a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 5959a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 5969a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 5979a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 5989a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 5999a24b929SJack Pham #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 6009a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 6019a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 6029a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL1 0x098 6039a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 6049a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 6059a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 6069a24b929SJack Pham #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 6079a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 6089a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 6099a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 6109a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 6119a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 6129a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 6139a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 6149a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 6159a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 6169a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 6179a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 6189a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 6199a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 6209a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 6219a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 6229a24b929SJack Pham #define QPHY_V4_PCS_BIST_CTRL 0x0e8 6239a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 6249a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 6259a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 6269a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 6279a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 6289a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT3 0x100 6299a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT4 0x104 6309a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT5 0x108 6319a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT6 0x10c 6329a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT7 0x110 6339a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT8 0x114 6349a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT9 0x118 6359a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT10 0x11c 6369a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT11 0x120 6379a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT12 0x124 6389a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT13 0x128 6399a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT14 0x12c 6409a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT15 0x130 6419a24b929SJack Pham #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 6429a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 6439a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 6449a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 6459a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 6469a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 6479a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 6489a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 6499a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 6509a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 6519a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 6529a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 6539a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 6549a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 6559a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 6569a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 6579a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 6589a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 6599a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 6609a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 6619a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 6629a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 6639a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 6649a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 6659a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 6669a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 6679a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 6689a24b929SJack Pham #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 6699a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 6709a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 6719a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 6729a24b929SJack Pham #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 6739a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 6749a24b929SJack Pham #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 6759a24b929SJack Pham #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 6769a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 6779a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 6789a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 6799a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 6809a24b929SJack Pham #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 6819a24b929SJack Pham #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 6829a24b929SJack Pham #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 6839a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 6849a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 6859a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 6869a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 6879a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 6889a24b929SJack Pham #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300 6899a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 6909a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 6919a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 6929a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 6939a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 6949a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 6959a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c 6969a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 6979a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 6989a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328 6999a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c 7009a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330 7019a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334 7029a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338 7039a24b929SJack Pham #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c 7049a24b929SJack Pham #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340 7059a24b929SJack Pham #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344 7069a24b929SJack Pham #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348 7079a24b929SJack Pham #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c 7089a24b929SJack Pham #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350 7099a24b929SJack Pham #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 7109a24b929SJack Pham #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 7119a24b929SJack Pham 7129a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 7139a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 7149a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 7159a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 7169a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 7179a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 7189a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 7199a24b929SJack Pham 720e2248617SManu Gautam #endif 721