1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 9520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ 10520264dbSSelvam Sathappan Periakaruppan 11520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TIMER 0x00c 12520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER1 0x01c 13520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER2 0x020 14520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 15520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 16520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 17520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 18520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 19520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_ENABLE1 0x040 20520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYS_CLK_CTRL 0x044 21520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 22520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_IVCO 0x050 23520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 24520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 25520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 26520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 27520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TRIM 0x074 28520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 29520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c 30520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE0 0x080 31520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE1 0x084 32520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 33fe841d5bSJohan Hovold #define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c 34520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 35520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 36520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 37520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 38520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_RESETSM_CNTRL 0x0b0 39520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP_EN 0x0c4 40520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE0 0x0cc 41520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE1 0x0d0 42520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 43520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc 44520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 45520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 46520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 47fe841d5bSJohan Hovold #define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec 48520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 49520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 50520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 51520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c 52520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_MAP 0x120 53520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 54520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 55520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c 56520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 57520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c 58520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 59520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_SELECT 0x16c 60520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_HSCLK_SEL 0x170 61520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV 0x17c 62520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORE_CLK_EN 0x184 63520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CMN_CONFIG 0x18c 64520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 65520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 66520264dbSSelvam Sathappan Periakaruppan 67520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - PCS registers */ 68520264dbSSelvam Sathappan Periakaruppan 69520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNTRL1 0x098 70520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNTRL2 0x09c 71520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNT_VAL_L 0x0a0 72520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNT_VAL_H_TOL 0x0a4 73520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_MAN_CODE 0x0a8 74520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_REFGEN_REQ_CONFIG1 0x0dc 75520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_G12S1_TXDEEMPH_M3P5DB 0x16c 76520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_RX_SIGDET_LVL 0x188 77520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 78520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 79520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_RX_DCC_CAL_CONFIG 0x1d8 80520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_EQ_CONFIG5 0x1ec 81520264dbSSelvam Sathappan Periakaruppan 82520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */ 83520264dbSSelvam Sathappan Periakaruppan 84af664324SDmitry Baryshkov #define PCS_PCIE_POWER_STATE_CONFIG2 0x00c 85af664324SDmitry Baryshkov #define PCS_PCIE_POWER_STATE_CONFIG4 0x014 86af664324SDmitry Baryshkov #define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 87af664324SDmitry Baryshkov #define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x040 88af664324SDmitry Baryshkov #define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x044 89af664324SDmitry Baryshkov #define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x048 90af664324SDmitry Baryshkov #define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x04c 91af664324SDmitry Baryshkov #define PCS_PCIE_OSC_DTCT_CONFIG2 0x05c 92af664324SDmitry Baryshkov #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x078 93af664324SDmitry Baryshkov #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x080 94af664324SDmitry Baryshkov #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x084 95af664324SDmitry Baryshkov #define PCS_PCIE_OSC_DTCT_ACTIONS 0x090 96af664324SDmitry Baryshkov #define PCS_PCIE_EQ_CONFIG1 0x0a0 97af664324SDmitry Baryshkov #define PCS_PCIE_EQ_CONFIG2 0x0a4 98af664324SDmitry Baryshkov #define PCS_PCIE_PRESET_P10_PRE 0x0bc 99af664324SDmitry Baryshkov #define PCS_PCIE_PRESET_P10_POST 0x0e0 100520264dbSSelvam Sathappan Periakaruppan 101e2248617SManu Gautam /* Only for QMP V2 PHY - QSERDES COM registers */ 102e2248617SManu Gautam #define QSERDES_COM_BG_TIMER 0x00c 103e2248617SManu Gautam #define QSERDES_COM_SSC_EN_CENTER 0x010 104e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER1 0x014 105e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER2 0x018 106e2248617SManu Gautam #define QSERDES_COM_SSC_PER1 0x01c 107e2248617SManu Gautam #define QSERDES_COM_SSC_PER2 0x020 108e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE1 0x024 109e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE2 0x028 110e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 111e2248617SManu Gautam #define QSERDES_COM_CLK_ENABLE1 0x038 112e2248617SManu Gautam #define QSERDES_COM_SYS_CLK_CTRL 0x03c 113e2248617SManu Gautam #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 114e2248617SManu Gautam #define QSERDES_COM_PLL_IVCO 0x048 115e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 116e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 117e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 118e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 119e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 120e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 121e2248617SManu Gautam #define QSERDES_COM_BG_TRIM 0x070 122e2248617SManu Gautam #define QSERDES_COM_CLK_EP_DIV 0x074 123e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE0 0x078 124e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE1 0x07c 125e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 126e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 127e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 128e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 129e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 130e2248617SManu Gautam #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 131e2248617SManu Gautam #define QSERDES_COM_RESETSM_CNTRL 0x0b4 1328abe5e77SShawn Guo #define QSERDES_COM_RESETSM_CNTRL2 0x0b8 133e2248617SManu Gautam #define QSERDES_COM_RESTRIM_CTRL 0x0bc 134e2248617SManu Gautam #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 135e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_EN 0x0c8 136e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 137e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE0 0x0d0 138e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE1 0x0d4 139e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 140e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 141e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 142e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 143e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 144e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 1458abe5e77SShawn Guo #define QSERDES_COM_INTEGLOOP_INITVAL 0x100 146e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 147e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 148e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 149e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 150e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_CTRL 0x124 151e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_MAP 0x128 152e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 153e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 154e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 155e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 156152a810eSIskren Chernev #define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c 157152a810eSIskren Chernev #define QSERDES_COM_VCO_TUNE_INITVAL2 0x140 158e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 159e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 160e2248617SManu Gautam #define QSERDES_COM_BG_CTRL 0x170 161e2248617SManu Gautam #define QSERDES_COM_CLK_SELECT 0x174 162e2248617SManu Gautam #define QSERDES_COM_HSCLK_SEL 0x178 163e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV 0x184 164e2248617SManu Gautam #define QSERDES_COM_CORE_CLK_EN 0x18c 165e2248617SManu Gautam #define QSERDES_COM_C_READY_STATUS 0x190 166e2248617SManu Gautam #define QSERDES_COM_CMN_CONFIG 0x194 167e2248617SManu Gautam #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 168e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS0 0x1a0 169e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS1 0x1a4 170e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS2 0x1a8 171e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS3 0x1ac 172e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 173e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 174e2248617SManu Gautam 175e2248617SManu Gautam /* Only for QMP V2 PHY - TX registers */ 176afd55e6dSSivaprakash Murugesan #define QSERDES_TX_EMP_POST1_LVL 0x018 177afd55e6dSSivaprakash Murugesan #define QSERDES_TX_SLEW_CNTL 0x040 178e2248617SManu Gautam #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 179e2248617SManu Gautam #define QSERDES_TX_DEBUG_BUS_SEL 0x064 180e2248617SManu Gautam #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 181e2248617SManu Gautam #define QSERDES_TX_LANE_MODE 0x094 182e2248617SManu Gautam #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 183e2248617SManu Gautam 184e2248617SManu Gautam /* Only for QMP V2 PHY - RX registers */ 185e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 186e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN 0x01c 187152a810eSIskren Chernev #define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030 188152a810eSIskren Chernev #define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034 189152a810eSIskren Chernev #define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038 190152a810eSIskren Chernev #define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c 191e2248617SManu Gautam #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 192e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 193e2248617SManu Gautam #define QSERDES_RX_RX_TERM_BW 0x090 194e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 195e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 196e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 197e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 198e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 199e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 200e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 201e2248617SManu Gautam #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 202e2248617SManu Gautam #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 203e2248617SManu Gautam #define QSERDES_RX_SIGDET_ENABLES 0x110 204e2248617SManu Gautam #define QSERDES_RX_SIGDET_CNTRL 0x114 205e2248617SManu Gautam #define QSERDES_RX_SIGDET_LVL 0x118 206e2248617SManu Gautam #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 207e2248617SManu Gautam #define QSERDES_RX_RX_BAND 0x120 208e2248617SManu Gautam #define QSERDES_RX_RX_INTERFACE_MODE 0x12c 209e2248617SManu Gautam 210e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 211*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04 212*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24 213*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x28 214*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x34 215*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x38 216*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x3c 217*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x40 218*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x54 219*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x58 220*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x60 221*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x64 222*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x6c 223*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x80 224*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x84 225*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x88 226*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 227*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 228*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc 229*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c 230*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140 231*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148 232*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154 233*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 234*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac 235*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 236*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 237*6cad2983SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 238e2248617SManu Gautam 2399a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 2409c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 2419c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 2429c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 2439c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 2449c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 2459c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 2469c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 2479c7761a3SManu Gautam 2489c7761a3SManu Gautam /* Only for QMP V3 PHY - QSERDES COM registers */ 24952e013d0SStephen Boyd #define QSERDES_V3_COM_ATB_SEL1 0x000 25052e013d0SStephen Boyd #define QSERDES_V3_COM_ATB_SEL2 0x004 25152e013d0SStephen Boyd #define QSERDES_V3_COM_FREQ_UPDATE 0x008 2529c7761a3SManu Gautam #define QSERDES_V3_COM_BG_TIMER 0x00c 2539c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 2549c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 2559c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 2569c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER1 0x01c 2579c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER2 0x020 2589c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 2599c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 260152a810eSIskren Chernev #define QSERDES_V3_COM_POST_DIV 0x02c 261152a810eSIskren Chernev #define QSERDES_V3_COM_POST_DIV_MUX 0x030 2629c7761a3SManu Gautam #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 26352e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 26452e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 26552e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 26652e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 26752e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 26852e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 26952e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 2709c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_ENABLE1 0x038 2719c7761a3SManu Gautam #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 2729c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 273152a810eSIskren Chernev #define QSERDES_V3_COM_PLL_EN 0x044 2749c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_IVCO 0x048 2759c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 2769c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 2779c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 2789c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 2799c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 2809c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 2819c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 2829c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 2839c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 2849c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 2859c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 2869c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 2879c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 2889c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 2899c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 2909c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 2919c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 2929c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 2939c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 2949c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 2959c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 2969c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 2979c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 2989c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 2999c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 3009c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 301a51969faSJeffrey Hugo #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 3029c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 3039c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 3049c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 3059c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 3069c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 3079c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 3089c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 3099c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 3109c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 3119c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 312cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 313cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 3149c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 3159c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 3169c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_SELECT 0x138 3179c7761a3SManu Gautam #define QSERDES_V3_COM_HSCLK_SEL 0x13c 3189c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 3199c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 3209c7761a3SManu Gautam #define QSERDES_V3_COM_CORE_CLK_EN 0x154 3219c7761a3SManu Gautam #define QSERDES_V3_COM_C_READY_STATUS 0x158 3229c7761a3SManu Gautam #define QSERDES_V3_COM_CMN_CONFIG 0x15c 3239c7761a3SManu Gautam #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 3249c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS0 0x168 3259c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 3269c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS2 0x170 3279c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS3 0x174 3289c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 329a51969faSJeffrey Hugo #define QSERDES_V3_COM_CMN_MODE 0x184 3309c7761a3SManu Gautam 3319c7761a3SManu Gautam /* Only for QMP V3 PHY - TX registers */ 33252e013d0SStephen Boyd #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 33352e013d0SStephen Boyd #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 33452e013d0SStephen Boyd #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c 33552e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 33652e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 33752e013d0SStephen Boyd 33852e013d0SStephen Boyd #define QSERDES_V3_TX_TX_DRV_LVL 0x01c 33952e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 34052e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 34152e013d0SStephen Boyd 34252e013d0SStephen Boyd #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 34352e013d0SStephen Boyd #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 34452e013d0SStephen Boyd 34552e013d0SStephen Boyd #define QSERDES_V3_TX_TX_BAND 0x02c 34652e013d0SStephen Boyd #define QSERDES_V3_TX_SLEW_CNTL 0x030 34752e013d0SStephen Boyd #define QSERDES_V3_TX_INTERFACE_SELECT 0x034 34852e013d0SStephen Boyd #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c 34952e013d0SStephen Boyd #define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 3509c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 3519c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 3529c7761a3SManu Gautam #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 35352e013d0SStephen Boyd #define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c 3549c7761a3SManu Gautam #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 35552e013d0SStephen Boyd #define QSERDES_V3_TX_TX_POL_INV 0x064 35652e013d0SStephen Boyd #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 3579c7761a3SManu Gautam #define QSERDES_V3_TX_LANE_MODE_1 0x08c 3589c7761a3SManu Gautam #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 35952e013d0SStephen Boyd #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 36052e013d0SStephen Boyd #define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 36152e013d0SStephen Boyd #define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 3629c7761a3SManu Gautam 3639c7761a3SManu Gautam /* Only for QMP V3 PHY - RX registers */ 364a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 3659c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 3669c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 367cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 368cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 369cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 3709c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 3719c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 372cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 373a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 374cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 3759c7761a3SManu Gautam #define QSERDES_V3_RX_RX_TERM_BW 0x07c 376f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 377f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 3789c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 3799c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 3809c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 3819c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 3829c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 3839c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 3849c7761a3SManu Gautam #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 3859c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_ENABLES 0x100 3869c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_CNTRL 0x104 3879c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_LVL 0x108 3889c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 3899c7761a3SManu Gautam #define QSERDES_V3_RX_RX_BAND 0x110 3909c7761a3SManu Gautam #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 391f6721e5cSManu Gautam #define QSERDES_V3_RX_RX_MODE_00 0x164 39273d7ec89SMarc Gonzalez #define QSERDES_V3_RX_RX_MODE_01 0x168 3939c7761a3SManu Gautam 3949c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 3959c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 3969c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 3979c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 3989c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 3999c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 4009c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 4019c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 402cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 403cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 4049c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 4059c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 4069c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 4079c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 4089c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 4099c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 4109c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 4119c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 4129c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 4139c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 4149c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 4159c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 4169c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 4179c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 4189c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 4199c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 4209c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 4219c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 4229c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 4239c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 4249c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 4259c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 4269c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 4279c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 4289c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 4299c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 4309c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 4319c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 43273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 4339c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 4349c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 4359c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 4369c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 4379c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 4389c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 4399c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 4409c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 441cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 442cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 443cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 444cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 44573d7ec89SMarc Gonzalez #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 44673d7ec89SMarc Gonzalez #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 44773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 448cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 449cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 4509c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 45173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 45273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 453f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 454f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 4559c7761a3SManu Gautam 456ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 457ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 45873d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 45973d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 46073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 46173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 46273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 463ac0d2399SManu Gautam 4645c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 4655c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 4665c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 4675c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 4685c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 4695c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 4705c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 47152e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 47252e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 47352e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 47452e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 47552e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 47652e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 47752e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 4785c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 4795c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 4805c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 4815c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 4825c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 4835c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 4845c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 4855c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 4865c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 4875c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 4885c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 48952e013d0SStephen Boyd 4905c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 49152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 49252e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 49352e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 49452e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 49552e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 49652e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 49752e013d0SStephen Boyd 49852e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 49952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 50052e013d0SStephen Boyd 50152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 50252e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 50352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 50452e013d0SStephen Boyd 50552e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 50652e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 50752e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 50852e013d0SStephen Boyd 50952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 51052e013d0SStephen Boyd 511a88c85eeSVinod Koul /* Only for QMP V4 PHY - QSERDES COM registers */ 512aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BG_TIMER 0x00c 5139a24b929SJack Pham #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 514f199223cSBjorn Andersson #define QSERDES_V4_COM_SSC_ADJ_PER1 0x014 5159a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER1 0x01c 5169a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER2 0x020 5179a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 5189a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 5199a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 5209a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 521aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 5226edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_ENABLE1 0x048 523aff188feSDmitry Baryshkov #define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c 5249a24b929SJack Pham #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 525a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_IVCO 0x058 526a88c85eeSVinod Koul #define QSERDES_V4_COM_CMN_IPTRIM 0x060 527a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 528a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 529a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 530a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 531a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 532a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 533a88c85eeSVinod Koul #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 534aff188feSDmitry Baryshkov #define QSERDES_V4_COM_RESETSM_CNTRL 0x09c 535a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 536be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8 537a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 538a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 539a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 540a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 54174acf0eeSJohan Hovold #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 542a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 5439a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 5449a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 5459a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 5469a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 5479a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 5489a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 549aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec 550aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 551be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 552be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 553aff188feSDmitry Baryshkov #define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 554a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 5559a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 5569a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 5579a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 5589a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 559a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 560aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_STATUS 0x140 5616edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_SELECT 0x154 562a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_SEL 0x158 563a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 564aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 5659a24b929SJack Pham #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 566aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORE_CLK_EN 0x174 567aff188feSDmitry Baryshkov #define QSERDES_V4_COM_C_READY_STATUS 0x178 568aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_CONFIG 0x17c 5699a24b929SJack Pham #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 570be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_CMN_MISC1 0x19c 571be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0 572be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_CMN_MODE 0x1a4 573be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8 574a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 575a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 576a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 577a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 578be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 579a88c85eeSVinod Koul 580a88c85eeSVinod Koul /* Only for QMP V4 PHY - TX registers */ 581aff188feSDmitry Baryshkov #define QSERDES_V4_TX_CLKBUF_ENABLE 0x08 582aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c 583aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_DRV_LVL 0x14 584aff188feSDmitry Baryshkov #define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c 585aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20 586aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_BAND 0x24 587aff188feSDmitry Baryshkov #define QSERDES_V4_TX_INTERFACE_SELECT 0x2c 5889a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 5899a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 5907b675ba1SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c 59190b65347SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 592aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54 593aff188feSDmitry Baryshkov #define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58 594aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_POL_INV 0x5c 595aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 596a88c85eeSVinod Koul #define QSERDES_V4_TX_LANE_MODE_1 0x84 59790b65347SJonathan Marek #define QSERDES_V4_TX_LANE_MODE_2 0x88 5989a24b929SJack Pham #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 599aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 600aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc 601a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 602fe841d5bSJohan Hovold #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdc 603a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 604a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 605aff188feSDmitry Baryshkov #define QSERDES_V4_TX_VMODE_CTRL1 0xe8 6069a24b929SJack Pham #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 607a88c85eeSVinod Koul 608be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - TX registers */ 609be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 610be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 611be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 612be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 613be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 614be0ddb5dSManivannan Sadhasivam 615a88c85eeSVinod Koul /* Only for QMP V4 PHY - RX registers */ 616a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 617a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 618a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 619a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 620a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 6219a24b929SJack Pham #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 622a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 623a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 6249a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 6259a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 6269a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 6279a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 6289a24b929SJack Pham #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 6296edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 630a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 631a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 632a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_TERM_BW 0x080 6339a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 6349a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 6359a24b929SJack Pham #define QSERDES_V4_RX_GM_CAL 0x0dc 6366edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 637a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 638a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 639a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 640a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 641a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 642a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 6439a24b929SJack Pham #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 644a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 6456edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_SIGDET_ENABLES 0x118 646a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 647a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_LVL 0x120 648a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 649a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_BAND 0x128 650a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 651a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 652a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 653a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 654a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 655a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 656a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 657a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 658a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 659a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 660a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 661a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 662a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 663a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 664a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 6659a24b929SJack Pham #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 6669a24b929SJack Pham #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 667a88c85eeSVinod Koul #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 6689a24b929SJack Pham #define QSERDES_V4_RX_VTH_CODE 0x1c4 669a88c85eeSVinod Koul 670aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 671aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 672aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 673aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 674aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 675aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 676aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 677aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 678aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 679aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 680aff188feSDmitry Baryshkov 681be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - RX registers */ 682be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 683be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 684be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 685be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_3 0x110 686be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 687be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 688be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 689be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 690be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 691be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 692be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 693be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 694be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 695be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 696be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 697be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 698be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 699be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 700be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 701be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 702be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 703be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 704be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 705be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 706be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 707be0ddb5dSManivannan Sadhasivam 7089a24b929SJack Pham /* Only for QMP V4 PHY - UFS PCS registers */ 70978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PHY_START 0x000 71078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 71178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_SW_RESET 0x008 71278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 71378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 71478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 71578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 71678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 71778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 71878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 71978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 72078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 72178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 72278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 72378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 72478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 72578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 72678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 72778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 72878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 729a88c85eeSVinod Koul 730909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 731909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 732909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 733909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 734909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 735909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 736909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 737909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 738909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 739909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 740909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 741909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 742909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 743909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 744909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 745909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 746909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 747909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 748909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 749909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 750909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 751909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 752909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 753909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 754909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 755909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 756909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 757909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 758909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 759909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 760909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 761909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 762909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 763909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 764909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 765909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 766909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 767909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 768909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 769909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 770909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 771909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 772909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 773909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 774909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 775909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 776909a5c78SBjorn Andersson 777909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 778909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 779909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 780909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 781909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 782909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 783909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 784909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 785909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 786909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 787909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 788909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 789909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 790909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 791909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 792909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 793909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 794909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 795909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 796909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 797909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 798909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 799909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 800909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 801909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 802909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 803909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 804909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 805909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 806909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 807909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 808909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 809909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 810909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 811909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 812909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 813909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 814909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 815909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 816909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 817909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 818909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 819909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 820909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 821909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 822909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 823909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 824909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 825909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 826909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 827909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 828909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 829909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 830909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 831909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 832909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 833909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 834909a5c78SBjorn Andersson 835909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 836909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 837909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 838909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 839909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 840909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 841909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 842909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 843909a5c78SBjorn Andersson 8449a24b929SJack Pham /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 8459a24b929SJack Pham #define QPHY_V4_PCS_SW_RESET 0x000 8469a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID0 0x004 8479a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID1 0x008 8489a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID2 0x00c 8499a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID3 0x010 8509a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS1 0x014 8519a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS2 0x018 8529a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS3 0x01c 8539a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS4 0x020 8549a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS5 0x024 8559a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS6 0x028 8569a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS7 0x02c 8579a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 8589a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 8599a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 8609a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 8619a24b929SJack Pham #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 8629a24b929SJack Pham #define QPHY_V4_PCS_START_CONTROL 0x044 8639a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 8649a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 8659a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 8669a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 8679a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 8689a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 8699a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 8709a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 8719a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 8729a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 8739a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 8749a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 8759a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 8769a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 8779a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 8789a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 8799a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 8809a24b929SJack Pham #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 8819a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 8829a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 8839a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL1 0x098 8849a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 8859a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 8869a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 8879a24b929SJack Pham #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 8889a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 8899a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 8909a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 8919a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 8929a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 8939a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 8949a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 8959a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 8969a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 8979a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 8989a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 8999a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 9009a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 9019a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 9029a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 9039a24b929SJack Pham #define QPHY_V4_PCS_BIST_CTRL 0x0e8 9049a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 9059a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 9069a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 9079a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 9089a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 9099a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT3 0x100 9109a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT4 0x104 9119a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT5 0x108 9129a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT6 0x10c 9139a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT7 0x110 9149a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT8 0x114 9159a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT9 0x118 9169a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT10 0x11c 9179a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT11 0x120 9189a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT12 0x124 9199a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT13 0x128 9209a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT14 0x12c 9219a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT15 0x130 9229a24b929SJack Pham #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 9239a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 9249a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 9259a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 9269a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 9279a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 9289a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 9299a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 9309a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 9319a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 9329a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 9339a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 9349a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 9359a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 9369a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 9379a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 9389a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 9399a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 9409a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 9419a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 9429a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 9439a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 9449a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 9459a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 9469a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 9479a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 9489a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 9499a24b929SJack Pham #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 9509a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 9519a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 9529a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 9539a24b929SJack Pham #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 9549a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 9559a24b929SJack Pham #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 9569a24b929SJack Pham #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 9579a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 9589a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 9599a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 9609a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 9619a24b929SJack Pham #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 9629a24b929SJack Pham #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 9639a24b929SJack Pham #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 9649a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 9659a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 9669a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 9679a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 9689a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 969fc646236SDmitry Baryshkov 970fc646236SDmitry Baryshkov /* Only for QMP V4 PHY - USB3 PCS registers */ 971fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000 972fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 973fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 974fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 975fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 976fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 977fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 978fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c 979fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 980fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 981fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028 982fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c 983fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030 984fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034 985fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038 986fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c 987fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040 988fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044 989fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048 990fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c 991fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050 992fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054 993fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058 9949a24b929SJack Pham 995be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 996be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 997be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 998be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 999be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 1000be0ddb5dSManivannan Sadhasivam 10019a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 10029a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 10039a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 10049a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 10059a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 10069a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 10079a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 10089a24b929SJack Pham 10096edf7700SManivannan Sadhasivam /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 10106edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 10116edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 10126edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 10136edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 10146edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 10156edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 10166edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 10176edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 10186edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 10196edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 10206edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 10216edf7700SManivannan Sadhasivam 1022be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 1023be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 1024be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 1025be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 1026be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 1027be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 1028be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 1029be0ddb5dSManivannan Sadhasivam 1030920abc10SVinod Koul /* Only for QMP V5 PHY - QSERDES COM registers */ 1031107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_EN_CENTER 0x010 1032107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_PER1 0x01c 1033107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_PER2 0x020 1034107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 1035107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 1036107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 1037107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 10382c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 1039107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_CLK_ENABLE1 0x048 1040107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 1041920abc10SVinod Koul #define QSERDES_V5_COM_PLL_IVCO 0x058 1042920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 1043920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 1044920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c 1045920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 1046920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 1047920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 1048920abc10SVinod Koul #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 1049920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 10502c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 1051920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac 1052920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 1053920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 1054920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 105574acf0eeSJohan Hovold #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc 1056920abc10SVinod Koul #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 1057107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc 1058107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 1059107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 1060107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 1061107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc 1062107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 1063920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c 1064107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 1065107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 1066107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 1067107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c 1068920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 1069107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_CLK_SELECT 0x154 1070920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_SEL 0x158 1071920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c 10722c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 1073107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c 10742c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CORE_CLK_EN 0x174 10752c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CMN_CONFIG 0x17c 10762c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CMN_MISC1 0x19c 1077488987b2SDmitry Baryshkov #define QSERDES_V5_COM_CMN_MODE 0x1a0 1078488987b2SDmitry Baryshkov #define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4 10792c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8 1080920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 1081920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 1082920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 1083920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 108474acf0eeSJohan Hovold #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 1085920abc10SVinod Koul 108610c744d4SJack Pham /* Only for QMP V5 PHY - TX registers */ 108710c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 108810c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38 108910c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c 109010c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40 109110c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_1 0x84 109210c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_2 0x88 109310c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_3 0x8c 109410c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_4 0x90 109510c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_5 0x94 109610c744d4SJack Pham #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4 109710c744d4SJack Pham #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0 109810c744d4SJack Pham #define QSERDES_V5_TX_PI_QEC_CTRL 0xe4 1099920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 1100920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 1101920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 1102920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 110310c744d4SJack Pham 11042c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - TX registers */ 11052c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 11062c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 11072c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 11082c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 11092c91bf6bSDmitry Baryshkov 111010c744d4SJack Pham /* Only for QMP V5 PHY - RX registers */ 111110c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 111210c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 111310c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 111410c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 111510c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 111610c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 111710c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 111810c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 111910c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c 112010c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 112110c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 112210c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 112310c744d4SJack Pham #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 112410c744d4SJack Pham #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 112510c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 112610c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 112710c744d4SJack Pham #define QSERDES_V5_RX_RX_TERM_BW 0x080 1128107ba9bfSDmitry Baryshkov #define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc 112910c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 113010c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 113110c744d4SJack Pham #define QSERDES_V5_RX_GM_CAL 0x0dc 113210c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 113310c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 113410c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 113510c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 113610c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 113710c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 113810c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 113910c744d4SJack Pham #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 114010c744d4SJack Pham #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 114110c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 114210c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c 114310c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_LVL 0x120 114410c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 114510c744d4SJack Pham #define QSERDES_V5_RX_RX_BAND 0x128 114610c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 114710c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 114810c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 114910c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 115010c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c 115110c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 115210c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 115310c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 115410c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c 115510c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 115610c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 115710c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 115810c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 115910c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 116010c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 116110c744d4SJack Pham #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 116210c744d4SJack Pham #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 116310c744d4SJack Pham #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 116410c744d4SJack Pham #define QSERDES_V5_RX_VTH_CODE 0x1b0 116510c744d4SJack Pham 11662c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - RX registers */ 11672c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 11682c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c 11692c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 11702c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c 11712c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 11722c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c 11732c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_3 0x090 11742c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 11752c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 11762c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 11772c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc 11782c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_GM_CAL 0x0ec 11792c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 11802c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 11812c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 11822c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c 11832c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 11842c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 11852c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c 11862c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 11872c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 11882c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 11892c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c 11902c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 11912c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 11922c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 11932c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c 11942c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 11952c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 11962c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 11972c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac 11982c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 11992c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 12002c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 12012c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 12022c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 12032c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc 12042c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 12052c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 12062c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 12072c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 12082c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 12092c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 12102c91bf6bSDmitry Baryshkov 1211107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - USB/PCIe PCS registers */ 1212107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc 12132c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 1214107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 1215107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 12162c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 12172c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 1218107ba9bfSDmitry Baryshkov 1219107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - PCS_PCIE registers */ 1220107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 1221107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 1222107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 1223107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 1224107ba9bfSDmitry Baryshkov 12252c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - PCIe PCS registers */ 12262c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 12272c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 12282c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 12292c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 12302c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 12312c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 12322c91bf6bSDmitry Baryshkov 1233920abc10SVinod Koul /* Only for QMP V5 PHY - UFS PCS registers */ 1234920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 1235920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 1236920abc10SVinod Koul #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 1237920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 1238920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 1239920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 1240920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 1241920abc10SVinod Koul #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 1242920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 1243920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 1244920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 1245920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 1246920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 1247920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 1248920abc10SVinod Koul #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 1249920abc10SVinod Koul 125010c744d4SJack Pham /* Only for QMP V5 PHY - USB3 have different offsets than V4 */ 1251fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000 1252fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 1253fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 1254fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 1255fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 1256fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 1257fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 1258fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c 1259fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 1260fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 1261fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028 1262fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c 1263fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030 1264fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034 1265fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038 1266fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c 1267fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040 1268fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044 1269fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048 1270fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c 1271fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050 1272fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054 1273fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058 1274fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c 1275fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060 127610c744d4SJack Pham 1277e2248617SManu Gautam #endif 1278