1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 99e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com.h" 109e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx.h" 119e1bae6dSDmitry Baryshkov 12a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v3.h" 13a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v3.h" 14a7fc833eSDmitry Baryshkov 1532d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v4.h" 1632d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v4.h" 1732d2cf53SDmitry Baryshkov 18f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v5.h" 19f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v5.h" 20f1f923adSDmitry Baryshkov 21147924ffSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-pll.h" 22520264dbSSelvam Sathappan Periakaruppan 23*5ae11aa4SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v2.h" 24e2248617SManu Gautam 259a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 269c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 279c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 289c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 299c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 309c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 319c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 329c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 339c7761a3SManu Gautam 34a7fc833eSDmitry Baryshkov /* QSERDES V3 COM bits */ 3552e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 3652e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 3752e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 3852e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 3952e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 4052e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 4152e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 429c7761a3SManu Gautam 43a7fc833eSDmitry Baryshkov /* QSERDES V3 TX bits */ 4452e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 4552e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 4652e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 4752e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 4852e013d0SStephen Boyd 499c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 509c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 519c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 529c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 539c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 549c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 559c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 569c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 57cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 58cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 599c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 609c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 619c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 629c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 639c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 649c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 659c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 669c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 679c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 689c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 699c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 709c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 719c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 729c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 739c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 749c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 759c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 769c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 779c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 789c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 799c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 809c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 819c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 829c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 839c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 849c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 859c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 869c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 8773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 889c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 899c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 909c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 919c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 929c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 939c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 949c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 959c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 96cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 97cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 98cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 99cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 10073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 10173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 10273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 103cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 104cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 1059c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 10673d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 10773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 108f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 109f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 1109c7761a3SManu Gautam 111ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 112ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 11373d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 11473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 11573d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 11673d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 11773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 118ac0d2399SManu Gautam 1195c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 1205c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 1215c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 1225c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 1235c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 1245c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 1255c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 12652e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 12752e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 12852e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 12952e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 13052e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 13152e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 13252e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 1335c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 1345c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 1355c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 1365c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 1375c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 1385c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 1395c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 1405c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 1415c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 1425c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 1435c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 14452e013d0SStephen Boyd 1455c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 14652e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 14752e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 14852e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 14952e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 15052e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 15152e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 15252e013d0SStephen Boyd 15352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 15452e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 15552e013d0SStephen Boyd 15652e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 15752e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 15852e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 15952e013d0SStephen Boyd 16052e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 16152e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 16252e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 16352e013d0SStephen Boyd 16452e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 16552e013d0SStephen Boyd 166a88c85eeSVinod Koul 167be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - TX registers */ 168be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 169be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 170be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 171be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 172be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 173be0ddb5dSManivannan Sadhasivam 174aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 175aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 176aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 177aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 178aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 179aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 180aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 181aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 182aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 183aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 184aff188feSDmitry Baryshkov 185be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - RX registers */ 186be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 187be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 188be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 189be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_3 0x110 190be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 191be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 192be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 193be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 194be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 195be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 196be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 197be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 198be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 199be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 200be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 201be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 202be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 203be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 204be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 205be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 206be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 207be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 208be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 209be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 210be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 211be0ddb5dSManivannan Sadhasivam 2129a24b929SJack Pham /* Only for QMP V4 PHY - UFS PCS registers */ 21378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PHY_START 0x000 21478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 21578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_SW_RESET 0x008 21678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 21778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 21878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 21978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 22078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 22178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 22278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 22378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 22478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 22578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 22678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 22778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 22878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 22978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 23078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 23178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 23278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 233a88c85eeSVinod Koul 234909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 235909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 236909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 237909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 238909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 239909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 240909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 241909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 242909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 243909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 244909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 245909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 246909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 247909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 248909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 249909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 250909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 251909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 252909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 253909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 254909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 255909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 256909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 257909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 258909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 259909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 260909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 261909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 262909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 263909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 264909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 265909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 266909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 267909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 268909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 269909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 270909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 271909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 272909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 273909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 274909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 275909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 276909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 277909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 278909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 279909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 280909a5c78SBjorn Andersson 281909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 282909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 283909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 284909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 285909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 286909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 287909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 288909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 289909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 290909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 291909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 292909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 293909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 294909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 295909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 296909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 297909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 298909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 299909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 300909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 301909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 302909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 303909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 304909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 305909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 306909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 307909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 308909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 309909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 310909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 311909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 312909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 313909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 314909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 315909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 316909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 317909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 318909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 319909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 320909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 321909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 322909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 323909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 324909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 325909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 326909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 327909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 328909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 329909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 330909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 331909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 332909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 333909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 334909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 335909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 336909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 337909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 338909a5c78SBjorn Andersson 339909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 340909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 341909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 342909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 343909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 344909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 345909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 346909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 347909a5c78SBjorn Andersson 3489a24b929SJack Pham /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 3499a24b929SJack Pham #define QPHY_V4_PCS_SW_RESET 0x000 3509a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID0 0x004 3519a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID1 0x008 3529a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID2 0x00c 3539a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID3 0x010 3549a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS1 0x014 3559a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS2 0x018 3569a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS3 0x01c 3579a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS4 0x020 3589a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS5 0x024 3599a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS6 0x028 3609a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS7 0x02c 3619a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 3629a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 3639a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 3649a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 3659a24b929SJack Pham #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 3669a24b929SJack Pham #define QPHY_V4_PCS_START_CONTROL 0x044 3679a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 3689a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 3699a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 3709a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 3719a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 3729a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 3739a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 3749a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 3759a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 3769a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 3779a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 3789a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 3799a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 3809a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 3819a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 3829a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 3839a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 3849a24b929SJack Pham #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 3859a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 3869a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 3879a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL1 0x098 3889a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 3899a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 3909a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 3919a24b929SJack Pham #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 3929a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 3939a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 3949a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 3959a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 3969a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 3979a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 3989a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 3999a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 4009a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 4019a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 4029a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 4039a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 4049a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 4059a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 4069a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 4079a24b929SJack Pham #define QPHY_V4_PCS_BIST_CTRL 0x0e8 4089a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 4099a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 4109a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 4119a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 4129a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 4139a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT3 0x100 4149a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT4 0x104 4159a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT5 0x108 4169a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT6 0x10c 4179a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT7 0x110 4189a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT8 0x114 4199a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT9 0x118 4209a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT10 0x11c 4219a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT11 0x120 4229a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT12 0x124 4239a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT13 0x128 4249a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT14 0x12c 4259a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT15 0x130 4269a24b929SJack Pham #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 4279a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 4289a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 4299a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 4309a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 4319a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 4329a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 4339a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 4349a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 4359a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 4369a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 4379a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 4389a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 4399a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 4409a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 4419a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 4429a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 4439a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 4449a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 4459a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 4469a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 4479a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 4489a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 4499a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 4509a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 4519a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 4529a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 4539a24b929SJack Pham #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 4549a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 4559a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 4569a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 4579a24b929SJack Pham #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 4589a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 4599a24b929SJack Pham #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 4609a24b929SJack Pham #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 4619a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 4629a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 4639a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 4649a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 4659a24b929SJack Pham #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 4669a24b929SJack Pham #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 4679a24b929SJack Pham #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 4689a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 4699a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 4709a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 4719a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 4729a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 473fc646236SDmitry Baryshkov 474fc646236SDmitry Baryshkov /* Only for QMP V4 PHY - USB3 PCS registers */ 475fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000 476fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 477fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 478fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 479fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 480fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 481fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 482fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c 483fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 484fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 485fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028 486fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c 487fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030 488fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034 489fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038 490fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c 491fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040 492fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044 493fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048 494fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c 495fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050 496fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054 497fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058 4989a24b929SJack Pham 499be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 500be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 501be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 502be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 503be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 504be0ddb5dSManivannan Sadhasivam 5059a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 5069a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 5079a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 5089a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 5099a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 5109a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 5119a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 5129a24b929SJack Pham 5136edf7700SManivannan Sadhasivam /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 5146edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 5156edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 5166edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 5176edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 5186edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 5196edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 5206edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 52160f23414SDmitry Baryshkov #define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0 5226edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 5236edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 5246edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 5256edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 5266edf7700SManivannan Sadhasivam 527be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 528be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 529be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 530be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 531be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 532be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 533be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 534be0ddb5dSManivannan Sadhasivam 5352c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - TX registers */ 5362c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 5372c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 5382c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 5392c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 5402c91bf6bSDmitry Baryshkov 5412c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - RX registers */ 5422c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 5432c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c 5442c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 5452c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c 5462c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 5472c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c 5482c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_3 0x090 5492c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 5502c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 5512c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 5522c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc 5532c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_GM_CAL 0x0ec 5542c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 5552c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 5562c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 5572c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c 5582c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 5592c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 5602c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c 5612c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 5622c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 5632c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 5642c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c 5652c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 5662c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 5672c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 5682c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c 5692c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 5702c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 5712c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 5722c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac 5732c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 5742c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 5752c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 5762c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 5772c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 5782c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc 5792c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 5802c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 5812c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 5822c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 5832c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 5842c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 5852c91bf6bSDmitry Baryshkov 586107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - USB/PCIe PCS registers */ 587107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc 5882c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 589107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 590107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 5912c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 5922c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 593107ba9bfSDmitry Baryshkov 594107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - PCS_PCIE registers */ 595107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 596107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 597107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 598107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 599107ba9bfSDmitry Baryshkov 6002c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - PCIe PCS registers */ 6012c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 6022c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 6032c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 6042c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 6052c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 6062c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 6072c91bf6bSDmitry Baryshkov 608920abc10SVinod Koul /* Only for QMP V5 PHY - UFS PCS registers */ 609920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 610920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 611920abc10SVinod Koul #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 612920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 613920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 614920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 615920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 616920abc10SVinod Koul #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 617920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 618920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 619920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 620920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 621920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 622920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 623920abc10SVinod Koul #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 624920abc10SVinod Koul 62510c744d4SJack Pham /* Only for QMP V5 PHY - USB3 have different offsets than V4 */ 626fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000 627fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 628fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 629fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 630fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 631fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 632fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 633fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c 634fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 635fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 636fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028 637fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c 638fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030 639fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034 640fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038 641fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c 642fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040 643fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044 644fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048 645fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c 646fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050 647fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054 648fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058 649fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c 650fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060 65110c744d4SJack Pham 652e2248617SManu Gautam #endif 653