1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 99e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com.h" 109e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx.h" 119e1bae6dSDmitry Baryshkov 12a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v3.h" 13a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v3.h" 14a7fc833eSDmitry Baryshkov 1532d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v4.h" 1632d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v4.h" 1732d2cf53SDmitry Baryshkov 18f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v5.h" 19f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v5.h" 20f1f923adSDmitry Baryshkov 21147924ffSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-pll.h" 22520264dbSSelvam Sathappan Periakaruppan 235ae11aa4SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v2.h" 24e2248617SManu Gautam 25*56a1fa09SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v3.h" 26*56a1fa09SDmitry Baryshkov #include "phy-qcom-qmp-pcs-misc-v3.h" 27*56a1fa09SDmitry Baryshkov 289a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 299c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 309c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 319c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 329c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 339c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 349c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 359c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 369c7761a3SManu Gautam 37a7fc833eSDmitry Baryshkov /* QSERDES V3 COM bits */ 3852e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 3952e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 4052e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 4152e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 4252e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 4352e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 4452e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 459c7761a3SManu Gautam 46a7fc833eSDmitry Baryshkov /* QSERDES V3 TX bits */ 4752e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 4852e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 4952e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 5052e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 5152e013d0SStephen Boyd 525c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 535c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 545c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 555c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 565c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 575c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 585c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 5952e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 6052e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 6152e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 6252e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 6352e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 6452e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 6552e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 665c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 675c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 685c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 695c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 705c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 715c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 725c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 735c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 745c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 755c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 765c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 7752e013d0SStephen Boyd 785c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 7952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 8052e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 8152e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 8252e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 8352e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 8452e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 8552e013d0SStephen Boyd 8652e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 8752e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 8852e013d0SStephen Boyd 8952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 9052e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 9152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 9252e013d0SStephen Boyd 9352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 9452e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 9552e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 9652e013d0SStephen Boyd 9752e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 9852e013d0SStephen Boyd 99a88c85eeSVinod Koul 100be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - TX registers */ 101be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 102be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 103be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 104be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 105be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 106be0ddb5dSManivannan Sadhasivam 107aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 108aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 109aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 110aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 111aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 112aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 113aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 114aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 115aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 116aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 117aff188feSDmitry Baryshkov 118be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - RX registers */ 119be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 120be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 121be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 122be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_3 0x110 123be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 124be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 125be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 126be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 127be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 128be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 129be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 130be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 131be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 132be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 133be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 134be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 135be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 136be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 137be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 138be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 139be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 140be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 141be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 142be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 143be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 144be0ddb5dSManivannan Sadhasivam 1459a24b929SJack Pham /* Only for QMP V4 PHY - UFS PCS registers */ 14678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PHY_START 0x000 14778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 14878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_SW_RESET 0x008 14978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 15078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 15178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 15278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 15378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 15478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 15578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 15678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 15778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 15878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 15978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 16078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 16178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 16278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 16378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 16478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 16578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 166a88c85eeSVinod Koul 167909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 168909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 169909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 170909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 171909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 172909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 173909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 174909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 175909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 176909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 177909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 178909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 179909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 180909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 181909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 182909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 183909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 184909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 185909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 186909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 187909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 188909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 189909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 190909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 191909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 192909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 193909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 194909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 195909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 196909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 197909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 198909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 199909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 200909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 201909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 202909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 203909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 204909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 205909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 206909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 207909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 208909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 209909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 210909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 211909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 212909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 213909a5c78SBjorn Andersson 214909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 215909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 216909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 217909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 218909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 219909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 220909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 221909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 222909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 223909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 224909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 225909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 226909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 227909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 228909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 229909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 230909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 231909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 232909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 233909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 234909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 235909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 236909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 237909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 238909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 239909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 240909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 241909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 242909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 243909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 244909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 245909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 246909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 247909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 248909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 249909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 250909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 251909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 252909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 253909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 254909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 255909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 256909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 257909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 258909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 259909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 260909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 261909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 262909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 263909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 264909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 265909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 266909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 267909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 268909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 269909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 270909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 271909a5c78SBjorn Andersson 272909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 273909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 274909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 275909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 276909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 277909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 278909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 279909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 280909a5c78SBjorn Andersson 2819a24b929SJack Pham /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 2829a24b929SJack Pham #define QPHY_V4_PCS_SW_RESET 0x000 2839a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID0 0x004 2849a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID1 0x008 2859a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID2 0x00c 2869a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID3 0x010 2879a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS1 0x014 2889a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS2 0x018 2899a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS3 0x01c 2909a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS4 0x020 2919a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS5 0x024 2929a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS6 0x028 2939a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS7 0x02c 2949a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 2959a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 2969a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 2979a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 2989a24b929SJack Pham #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 2999a24b929SJack Pham #define QPHY_V4_PCS_START_CONTROL 0x044 3009a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 3019a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 3029a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 3039a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 3049a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 3059a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 3069a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 3079a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 3089a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 3099a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 3109a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 3119a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 3129a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 3139a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 3149a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 3159a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 3169a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 3179a24b929SJack Pham #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 3189a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 3199a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 3209a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL1 0x098 3219a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 3229a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 3239a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 3249a24b929SJack Pham #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 3259a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 3269a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 3279a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 3289a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 3299a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 3309a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 3319a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 3329a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 3339a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 3349a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 3359a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 3369a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 3379a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 3389a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 3399a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 3409a24b929SJack Pham #define QPHY_V4_PCS_BIST_CTRL 0x0e8 3419a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 3429a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 3439a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 3449a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 3459a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 3469a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT3 0x100 3479a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT4 0x104 3489a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT5 0x108 3499a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT6 0x10c 3509a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT7 0x110 3519a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT8 0x114 3529a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT9 0x118 3539a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT10 0x11c 3549a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT11 0x120 3559a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT12 0x124 3569a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT13 0x128 3579a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT14 0x12c 3589a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT15 0x130 3599a24b929SJack Pham #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 3609a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 3619a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 3629a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 3639a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 3649a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 3659a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 3669a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 3679a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 3689a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 3699a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 3709a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 3719a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 3729a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 3739a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 3749a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 3759a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 3769a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 3779a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 3789a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 3799a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 3809a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 3819a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 3829a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 3839a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 3849a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 3859a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 3869a24b929SJack Pham #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 3879a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 3889a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 3899a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 3909a24b929SJack Pham #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 3919a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 3929a24b929SJack Pham #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 3939a24b929SJack Pham #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 3949a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 3959a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 3969a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 3979a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 3989a24b929SJack Pham #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 3999a24b929SJack Pham #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 4009a24b929SJack Pham #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 4019a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 4029a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 4039a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 4049a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 4059a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 406fc646236SDmitry Baryshkov 407fc646236SDmitry Baryshkov /* Only for QMP V4 PHY - USB3 PCS registers */ 408fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000 409fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 410fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 411fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 412fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 413fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 414fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 415fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c 416fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 417fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 418fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028 419fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c 420fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030 421fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034 422fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038 423fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c 424fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040 425fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044 426fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048 427fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c 428fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050 429fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054 430fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058 4319a24b929SJack Pham 432be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 433be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 434be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 435be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 436be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 437be0ddb5dSManivannan Sadhasivam 4389a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 4399a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 4409a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 4419a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 4429a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 4439a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 4449a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 4459a24b929SJack Pham 4466edf7700SManivannan Sadhasivam /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 4476edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 4486edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 4496edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 4506edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 4516edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 4526edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 4536edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 45460f23414SDmitry Baryshkov #define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0 4556edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 4566edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 4576edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 4586edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 4596edf7700SManivannan Sadhasivam 460be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 461be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 462be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 463be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 464be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 465be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 466be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 467be0ddb5dSManivannan Sadhasivam 4682c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - TX registers */ 4692c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 4702c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 4712c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 4722c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 4732c91bf6bSDmitry Baryshkov 4742c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - RX registers */ 4752c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 4762c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c 4772c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 4782c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c 4792c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 4802c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c 4812c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_3 0x090 4822c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 4832c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 4842c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 4852c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc 4862c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_GM_CAL 0x0ec 4872c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 4882c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 4892c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 4902c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c 4912c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 4922c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 4932c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c 4942c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 4952c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 4962c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 4972c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c 4982c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 4992c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 5002c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 5012c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c 5022c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 5032c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 5042c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 5052c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac 5062c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 5072c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 5082c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 5092c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 5102c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 5112c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc 5122c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 5132c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 5142c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 5152c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 5162c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 5172c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 5182c91bf6bSDmitry Baryshkov 519107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - USB/PCIe PCS registers */ 520107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc 5212c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 522107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 523107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 5242c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 5252c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 526107ba9bfSDmitry Baryshkov 527107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - PCS_PCIE registers */ 528107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 529107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 530107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 531107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 532107ba9bfSDmitry Baryshkov 5332c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - PCIe PCS registers */ 5342c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 5352c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 5362c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 5372c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 5382c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 5392c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 5402c91bf6bSDmitry Baryshkov 541920abc10SVinod Koul /* Only for QMP V5 PHY - UFS PCS registers */ 542920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 543920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 544920abc10SVinod Koul #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 545920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 546920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 547920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 548920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 549920abc10SVinod Koul #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 550920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 551920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 552920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 553920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 554920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 555920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 556920abc10SVinod Koul #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 557920abc10SVinod Koul 55810c744d4SJack Pham /* Only for QMP V5 PHY - USB3 have different offsets than V4 */ 559fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000 560fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 561fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 562fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 563fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 564fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 565fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 566fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c 567fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 568fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 569fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028 570fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c 571fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030 572fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034 573fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038 574fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c 575fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040 576fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044 577fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048 578fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c 579fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050 580fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054 581fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058 582fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c 583fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060 58410c744d4SJack Pham 585e2248617SManu Gautam #endif 586