1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 9*520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ 10*520264dbSSelvam Sathappan Periakaruppan 11*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TIMER 0x00c 12*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER1 0x01c 13*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER2 0x020 14*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 15*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 16*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 17*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 18*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 19*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_ENABLE1 0x040 20*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYS_CLK_CTRL 0x044 21*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 22*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_IVCO 0x050 23*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 24*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 25*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 26*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 27*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TRIM 0x074 28*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 29*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c 30*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE0 0x080 31*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE1 0x084 32*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 33*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_RCTRL_MODE1 0x08C 34*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 35*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 36*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 37*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 38*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_RESETSM_CNTRL 0x0b0 39*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP_EN 0x0c4 40*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE0 0x0cc 41*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE1 0x0d0 42*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 43*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc 44*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 45*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 46*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 47*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0eC 48*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 49*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 50*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 51*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c 52*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_MAP 0x120 53*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 54*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 55*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c 56*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 57*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c 58*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 59*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_SELECT 0x16c 60*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_HSCLK_SEL 0x170 61*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV 0x17c 62*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORE_CLK_EN 0x184 63*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CMN_CONFIG 0x18c 64*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 65*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 66*520264dbSSelvam Sathappan Periakaruppan 67*520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - QSERDES TX registers */ 68*520264dbSSelvam Sathappan Periakaruppan 69*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX 0x03c 70*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_TX0_HIGHZ_DRVR_EN 0x058 71*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_TX0_LANE_MODE_1 0x084 72*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c 73*520264dbSSelvam Sathappan Periakaruppan 74*520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - QSERDES RX registers */ 75*520264dbSSelvam Sathappan Periakaruppan 76*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_UCDR_FO_GAIN 0x008 77*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_UCDR_SO_GAIN 0x014 78*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE 0x034 79*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_UCDR_PI_CONTROLS 0x044 80*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 0x0ec 81*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 0x0f0 82*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 0x0f4 83*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_IDAC_TSETTLE_LOW 0x0f8 84*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH 0x0fc 85*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 86*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 0x114 87*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_SIGDET_ENABLES 0x118 88*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_SIGDET_CNTRL 0x11c 89*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL 0x124 90*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_LOW 0x170 91*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_HIGH 0x174 92*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_HIGH2 0x178 93*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_HIGH3 0x17c 94*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_HIGH4 0x180 95*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_LOW 0x184 96*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_HIGH 0x188 97*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_HIGH2 0x18c 98*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_HIGH3 0x190 99*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_HIGH4 0x194 100*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_LOW 0x198 101*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_HIGH 0x19c 102*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_HIGH2 0x1a0 103*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_HIGH3 0x1a4 104*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_HIGH4 0x1a8 105*520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_DFE_EN_TIMER 0x1b4 106*520264dbSSelvam Sathappan Periakaruppan 107*520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - PCS registers */ 108*520264dbSSelvam Sathappan Periakaruppan 109*520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNTRL1 0x098 110*520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNTRL2 0x09c 111*520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNT_VAL_L 0x0a0 112*520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNT_VAL_H_TOL 0x0a4 113*520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_MAN_CODE 0x0a8 114*520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_REFGEN_REQ_CONFIG1 0x0dc 115*520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_G12S1_TXDEEMPH_M3P5DB 0x16c 116*520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_RX_SIGDET_LVL 0x188 117*520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 118*520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 119*520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_RX_DCC_CAL_CONFIG 0x1d8 120*520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_EQ_CONFIG5 0x1ec 121*520264dbSSelvam Sathappan Periakaruppan 122*520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */ 123*520264dbSSelvam Sathappan Periakaruppan 124*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_POWER_STATE_CONFIG2 0x40c 125*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_POWER_STATE_CONFIG4 0x414 126*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c 127*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440 128*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444 129*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448 130*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c 131*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c 132*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478 133*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480 134*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484 135*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_ACTIONS 0x490 136*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_EQ_CONFIG1 0x4a0 137*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_EQ_CONFIG2 0x4a4 138*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_PRESET_P10_PRE 0x4bc 139*520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_PRESET_P10_POST 0x4e0 140*520264dbSSelvam Sathappan Periakaruppan 141e2248617SManu Gautam /* Only for QMP V2 PHY - QSERDES COM registers */ 142e2248617SManu Gautam #define QSERDES_COM_BG_TIMER 0x00c 143e2248617SManu Gautam #define QSERDES_COM_SSC_EN_CENTER 0x010 144e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER1 0x014 145e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER2 0x018 146e2248617SManu Gautam #define QSERDES_COM_SSC_PER1 0x01c 147e2248617SManu Gautam #define QSERDES_COM_SSC_PER2 0x020 148e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE1 0x024 149e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE2 0x028 150e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 151e2248617SManu Gautam #define QSERDES_COM_CLK_ENABLE1 0x038 152e2248617SManu Gautam #define QSERDES_COM_SYS_CLK_CTRL 0x03c 153e2248617SManu Gautam #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 154e2248617SManu Gautam #define QSERDES_COM_PLL_IVCO 0x048 155e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 156e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 157e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 158e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 159e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 160e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 161e2248617SManu Gautam #define QSERDES_COM_BG_TRIM 0x070 162e2248617SManu Gautam #define QSERDES_COM_CLK_EP_DIV 0x074 163e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE0 0x078 164e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE1 0x07c 165e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 166e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 167e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 168e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 169e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 170e2248617SManu Gautam #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 171e2248617SManu Gautam #define QSERDES_COM_RESETSM_CNTRL 0x0b4 172e2248617SManu Gautam #define QSERDES_COM_RESTRIM_CTRL 0x0bc 173e2248617SManu Gautam #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 174e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_EN 0x0c8 175e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 176e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE0 0x0d0 177e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE1 0x0d4 178e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 179e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 180e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 181e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 182e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 183e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 184e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 185e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 186e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 187e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 188e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_CTRL 0x124 189e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_MAP 0x128 190e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 191e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 192e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 193e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 194e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 195e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 196e2248617SManu Gautam #define QSERDES_COM_BG_CTRL 0x170 197e2248617SManu Gautam #define QSERDES_COM_CLK_SELECT 0x174 198e2248617SManu Gautam #define QSERDES_COM_HSCLK_SEL 0x178 199e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV 0x184 200e2248617SManu Gautam #define QSERDES_COM_CORE_CLK_EN 0x18c 201e2248617SManu Gautam #define QSERDES_COM_C_READY_STATUS 0x190 202e2248617SManu Gautam #define QSERDES_COM_CMN_CONFIG 0x194 203e2248617SManu Gautam #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 204e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS0 0x1a0 205e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS1 0x1a4 206e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS2 0x1a8 207e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS3 0x1ac 208e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 209e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 210e2248617SManu Gautam 211e2248617SManu Gautam /* Only for QMP V2 PHY - TX registers */ 212afd55e6dSSivaprakash Murugesan #define QSERDES_TX_EMP_POST1_LVL 0x018 213afd55e6dSSivaprakash Murugesan #define QSERDES_TX_SLEW_CNTL 0x040 214e2248617SManu Gautam #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 215e2248617SManu Gautam #define QSERDES_TX_DEBUG_BUS_SEL 0x064 216e2248617SManu Gautam #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 217e2248617SManu Gautam #define QSERDES_TX_LANE_MODE 0x094 218e2248617SManu Gautam #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 219e2248617SManu Gautam 220e2248617SManu Gautam /* Only for QMP V2 PHY - RX registers */ 221e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 222e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN 0x01c 223e2248617SManu Gautam #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 224e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 225e2248617SManu Gautam #define QSERDES_RX_RX_TERM_BW 0x090 226e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 227e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 228e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 229e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 230e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 231e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 232e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 233e2248617SManu Gautam #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 234e2248617SManu Gautam #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 235e2248617SManu Gautam #define QSERDES_RX_SIGDET_ENABLES 0x110 236e2248617SManu Gautam #define QSERDES_RX_SIGDET_CNTRL 0x114 237e2248617SManu Gautam #define QSERDES_RX_SIGDET_LVL 0x118 238e2248617SManu Gautam #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 239e2248617SManu Gautam #define QSERDES_RX_RX_BAND 0x120 240e2248617SManu Gautam #define QSERDES_RX_RX_INTERFACE_MODE 0x12c 241e2248617SManu Gautam 242e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 243e2248617SManu Gautam #define QPHY_POWER_DOWN_CONTROL 0x04 244e2248617SManu Gautam #define QPHY_TXDEEMPH_M6DB_V0 0x24 245e2248617SManu Gautam #define QPHY_TXDEEMPH_M3P5DB_V0 0x28 246e2248617SManu Gautam #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 247e2248617SManu Gautam #define QPHY_RX_IDLE_DTCT_CNTRL 0x58 248e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG1 0x60 249e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG2 0x64 250e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG4 0x6c 251e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG1 0x80 252e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG2 0x84 253e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG3 0x88 254e2248617SManu Gautam #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 255e2248617SManu Gautam #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 256e2248617SManu Gautam #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 257e2248617SManu Gautam #define QPHY_OSC_DTCT_ACTIONS 0x1AC 258e2248617SManu Gautam #define QPHY_RX_SIGDET_LVL 0x1D8 259e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC 260e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 261e2248617SManu Gautam 2629a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 2639c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 2649c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 2659c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 2669c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 2679c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 2689c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 2699c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 2709c7761a3SManu Gautam 2719c7761a3SManu Gautam /* Only for QMP V3 PHY - QSERDES COM registers */ 27252e013d0SStephen Boyd #define QSERDES_V3_COM_ATB_SEL1 0x000 27352e013d0SStephen Boyd #define QSERDES_V3_COM_ATB_SEL2 0x004 27452e013d0SStephen Boyd #define QSERDES_V3_COM_FREQ_UPDATE 0x008 2759c7761a3SManu Gautam #define QSERDES_V3_COM_BG_TIMER 0x00c 2769c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 2779c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 2789c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 2799c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER1 0x01c 2809c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER2 0x020 2819c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 2829c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 2839c7761a3SManu Gautam #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 28452e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 28552e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 28652e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 28752e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 28852e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 28952e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 29052e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 2919c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_ENABLE1 0x038 2929c7761a3SManu Gautam #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 2939c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 2949c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_IVCO 0x048 2959c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 2969c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 2979c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 2989c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 2999c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 3009c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 3019c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 3029c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 3039c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 3049c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 3059c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 3069c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 3079c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 3089c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 3099c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 3109c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 3119c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 3129c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 3139c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 3149c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 3159c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 3169c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 3179c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 3189c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 3199c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 3209c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 321a51969faSJeffrey Hugo #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 3229c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 3239c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 3249c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 3259c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 3269c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 3279c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 3289c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 3299c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 3309c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 3319c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 332cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 333cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 3349c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 3359c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 3369c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_SELECT 0x138 3379c7761a3SManu Gautam #define QSERDES_V3_COM_HSCLK_SEL 0x13c 3389c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 3399c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 3409c7761a3SManu Gautam #define QSERDES_V3_COM_CORE_CLK_EN 0x154 3419c7761a3SManu Gautam #define QSERDES_V3_COM_C_READY_STATUS 0x158 3429c7761a3SManu Gautam #define QSERDES_V3_COM_CMN_CONFIG 0x15c 3439c7761a3SManu Gautam #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 3449c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS0 0x168 3459c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 3469c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS2 0x170 3479c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS3 0x174 3489c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 349a51969faSJeffrey Hugo #define QSERDES_V3_COM_CMN_MODE 0x184 3509c7761a3SManu Gautam 3519c7761a3SManu Gautam /* Only for QMP V3 PHY - TX registers */ 35252e013d0SStephen Boyd #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 35352e013d0SStephen Boyd #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 35452e013d0SStephen Boyd #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c 35552e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 35652e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 35752e013d0SStephen Boyd 35852e013d0SStephen Boyd #define QSERDES_V3_TX_TX_DRV_LVL 0x01c 35952e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 36052e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 36152e013d0SStephen Boyd 36252e013d0SStephen Boyd #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 36352e013d0SStephen Boyd #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 36452e013d0SStephen Boyd 36552e013d0SStephen Boyd #define QSERDES_V3_TX_TX_BAND 0x02c 36652e013d0SStephen Boyd #define QSERDES_V3_TX_SLEW_CNTL 0x030 36752e013d0SStephen Boyd #define QSERDES_V3_TX_INTERFACE_SELECT 0x034 36852e013d0SStephen Boyd #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c 36952e013d0SStephen Boyd #define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 3709c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 3719c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 3729c7761a3SManu Gautam #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 37352e013d0SStephen Boyd #define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c 3749c7761a3SManu Gautam #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 37552e013d0SStephen Boyd #define QSERDES_V3_TX_TX_POL_INV 0x064 37652e013d0SStephen Boyd #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 3779c7761a3SManu Gautam #define QSERDES_V3_TX_LANE_MODE_1 0x08c 3789c7761a3SManu Gautam #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 37952e013d0SStephen Boyd #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 38052e013d0SStephen Boyd #define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 38152e013d0SStephen Boyd #define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 3829c7761a3SManu Gautam 3839c7761a3SManu Gautam /* Only for QMP V3 PHY - RX registers */ 384a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 3859c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 3869c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 387cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 388cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 389cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 3909c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 3919c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 392cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 393a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 394cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 3959c7761a3SManu Gautam #define QSERDES_V3_RX_RX_TERM_BW 0x07c 396f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 397f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 3989c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 3999c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 4009c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 4019c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 4029c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 4039c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 4049c7761a3SManu Gautam #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 4059c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_ENABLES 0x100 4069c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_CNTRL 0x104 4079c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_LVL 0x108 4089c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 4099c7761a3SManu Gautam #define QSERDES_V3_RX_RX_BAND 0x110 4109c7761a3SManu Gautam #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 411f6721e5cSManu Gautam #define QSERDES_V3_RX_RX_MODE_00 0x164 41273d7ec89SMarc Gonzalez #define QSERDES_V3_RX_RX_MODE_01 0x168 4139c7761a3SManu Gautam 4149c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 4159c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 4169c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 4179c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 4189c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 4199c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 4209c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 4219c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 422cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 423cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 4249c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 4259c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 4269c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 4279c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 4289c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 4299c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 4309c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 4319c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 4329c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 4339c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 4349c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 4359c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 4369c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 4379c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 4389c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 4399c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 4409c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 4419c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 4429c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 4439c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 4449c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 4459c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 4469c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 4479c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 4489c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 4499c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 4509c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 4519c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 45273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 4539c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 4549c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 4559c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 4569c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 4579c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 4589c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 4599c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 4609c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 461cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 462cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 463cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 464cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 46573d7ec89SMarc Gonzalez #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 46673d7ec89SMarc Gonzalez #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 46773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 468cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 469cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 4709c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 47173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 47273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 473f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 474f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 4759c7761a3SManu Gautam 476ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 477ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 47873d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 47973d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 48073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 48173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 48273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 483ac0d2399SManu Gautam 4845c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 4855c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 4865c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 4875c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 4885c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 4895c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 4905c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 49152e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 49252e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 49352e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 49452e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 49552e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 49652e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 49752e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 4985c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 4995c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 5005c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 5015c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 5025c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 5035c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 5045c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 5055c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 5065c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 5075c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 5085c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 50952e013d0SStephen Boyd 5105c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 51152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 51252e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 51352e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 51452e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 51552e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 51652e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 51752e013d0SStephen Boyd 51852e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 51952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 52052e013d0SStephen Boyd 52152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 52252e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 52352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 52452e013d0SStephen Boyd 52552e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 52652e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 52752e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 52852e013d0SStephen Boyd 52952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 53052e013d0SStephen Boyd 531a88c85eeSVinod Koul /* Only for QMP V4 PHY - QSERDES COM registers */ 532aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BG_TIMER 0x00c 5339a24b929SJack Pham #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 5349a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER1 0x01c 5359a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER2 0x020 5369a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 5379a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 5389a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 5399a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 540aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 5416edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_ENABLE1 0x048 542aff188feSDmitry Baryshkov #define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c 5439a24b929SJack Pham #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 544a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_IVCO 0x058 545a88c85eeSVinod Koul #define QSERDES_V4_COM_CMN_IPTRIM 0x060 546a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 547a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 548a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 549a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 550a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 551a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 552a88c85eeSVinod Koul #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 553aff188feSDmitry Baryshkov #define QSERDES_V4_COM_RESETSM_CNTRL 0x09c 554a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 555a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 556a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 557a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 558a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 559a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 560a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 5619a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 5629a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 5639a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 5649a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 5659a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 5669a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 567aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec 568aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 569aff188feSDmitry Baryshkov #define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 570a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 5719a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 5729a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 5739a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 5749a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 575a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 576aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_STATUS 0x140 5776edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_SELECT 0x154 578a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_SEL 0x158 579a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 580aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 5819a24b929SJack Pham #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 582aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORE_CLK_EN 0x174 583aff188feSDmitry Baryshkov #define QSERDES_V4_COM_C_READY_STATUS 0x178 584aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_CONFIG 0x17c 5859a24b929SJack Pham #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 586a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 587a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 588a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 589a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 590a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 591a88c85eeSVinod Koul 592a88c85eeSVinod Koul /* Only for QMP V4 PHY - TX registers */ 593aff188feSDmitry Baryshkov #define QSERDES_V4_TX_CLKBUF_ENABLE 0x08 594aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c 595aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_DRV_LVL 0x14 596aff188feSDmitry Baryshkov #define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c 597aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20 598aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_BAND 0x24 599aff188feSDmitry Baryshkov #define QSERDES_V4_TX_INTERFACE_SELECT 0x2c 6009a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 6019a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 6027b675ba1SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c 60390b65347SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 604aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54 605aff188feSDmitry Baryshkov #define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58 606aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_POL_INV 0x5c 607aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 608a88c85eeSVinod Koul #define QSERDES_V4_TX_LANE_MODE_1 0x84 60990b65347SJonathan Marek #define QSERDES_V4_TX_LANE_MODE_2 0x88 6109a24b929SJack Pham #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 611aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 612aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc 613a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 614a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC 615a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 616a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 617aff188feSDmitry Baryshkov #define QSERDES_V4_TX_VMODE_CTRL1 0xe8 6189a24b929SJack Pham #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 619a88c85eeSVinod Koul 620a88c85eeSVinod Koul /* Only for QMP V4 PHY - RX registers */ 621a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 622a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 623a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 624a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 625a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 6269a24b929SJack Pham #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 627a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 628a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 6299a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 6309a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 6319a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 6329a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 6339a24b929SJack Pham #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 6346edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 635a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 636a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 637a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_TERM_BW 0x080 6389a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 6399a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 6409a24b929SJack Pham #define QSERDES_V4_RX_GM_CAL 0x0dc 6416edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 642a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 643a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 644a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 645a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 646a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 647a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 6489a24b929SJack Pham #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 649a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 6506edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_SIGDET_ENABLES 0x118 651a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 652a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_LVL 0x120 653a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 654a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_BAND 0x128 655a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 656a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 657a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 658a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 659a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 660a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 661a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 662a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 663a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 664a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 665a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 666a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 667a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 668a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 669a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 6709a24b929SJack Pham #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 6719a24b929SJack Pham #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 672a88c85eeSVinod Koul #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 6739a24b929SJack Pham #define QSERDES_V4_RX_VTH_CODE 0x1c4 674a88c85eeSVinod Koul 675aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 676aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 677aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 678aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 679aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 680aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 681aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 682aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 683aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 684aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 685aff188feSDmitry Baryshkov 6869a24b929SJack Pham /* Only for QMP V4 PHY - UFS PCS registers */ 68778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PHY_START 0x000 68878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 68978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_SW_RESET 0x008 69078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 69178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 69278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 69378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 69478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 69578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 69678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 69778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 69878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 69978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 70078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 70178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 70278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 70378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 70478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 70578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 70678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 707a88c85eeSVinod Koul 708909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 709909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 710909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 711909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 712909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 713909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 714909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 715909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 716909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 717909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 718909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 719909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 720909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 721909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 722909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 723909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 724909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 725909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 726909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 727909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 728909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 729909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 730909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 731909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 732909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 733909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 734909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 735909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 736909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 737909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 738909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 739909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 740909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 741909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 742909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 743909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 744909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 745909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 746909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 747909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 748909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 749909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 750909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 751909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 752909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 753909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 754909a5c78SBjorn Andersson 755909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 756909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 757909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 758909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 759909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 760909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 761909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 762909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 763909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 764909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 765909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 766909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 767909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 768909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 769909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 770909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 771909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 772909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 773909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 774909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 775909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 776909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 777909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 778909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 779909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 780909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 781909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 782909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 783909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 784909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 785909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 786909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 787909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 788909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 789909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 790909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 791909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 792909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 793909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 794909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 795909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 796909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 797909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 798909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 799909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 800909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 801909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 802909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 803909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 804909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 805909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 806909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 807909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 808909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 809909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 810909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 811909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 812909a5c78SBjorn Andersson 813909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 814909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 815909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 816909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 817909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 818909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 819909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 820909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 821909a5c78SBjorn Andersson 8229a24b929SJack Pham /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 8239a24b929SJack Pham #define QPHY_V4_PCS_SW_RESET 0x000 8249a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID0 0x004 8259a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID1 0x008 8269a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID2 0x00c 8279a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID3 0x010 8289a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS1 0x014 8299a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS2 0x018 8309a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS3 0x01c 8319a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS4 0x020 8329a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS5 0x024 8339a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS6 0x028 8349a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS7 0x02c 8359a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 8369a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 8379a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 8389a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 8399a24b929SJack Pham #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 8409a24b929SJack Pham #define QPHY_V4_PCS_START_CONTROL 0x044 8419a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 8429a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 8439a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 8449a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 8459a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 8469a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 8479a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 8489a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 8499a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 8509a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 8519a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 8529a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 8539a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 8549a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 8559a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 8569a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 8579a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 8589a24b929SJack Pham #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 8599a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 8609a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 8619a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL1 0x098 8629a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 8639a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 8649a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 8659a24b929SJack Pham #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 8669a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 8679a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 8689a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 8699a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 8709a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 8719a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 8729a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 8739a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 8749a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 8759a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 8769a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 8779a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 8789a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 8799a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 8809a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 8819a24b929SJack Pham #define QPHY_V4_PCS_BIST_CTRL 0x0e8 8829a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 8839a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 8849a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 8859a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 8869a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 8879a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT3 0x100 8889a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT4 0x104 8899a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT5 0x108 8909a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT6 0x10c 8919a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT7 0x110 8929a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT8 0x114 8939a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT9 0x118 8949a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT10 0x11c 8959a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT11 0x120 8969a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT12 0x124 8979a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT13 0x128 8989a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT14 0x12c 8999a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT15 0x130 9009a24b929SJack Pham #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 9019a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 9029a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 9039a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 9049a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 9059a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 9069a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 9079a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 9089a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 9099a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 9109a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 9119a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 9129a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 9139a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 9149a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 9159a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 9169a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 9179a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 9189a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 9199a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 9209a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 9219a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 9229a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 9239a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 9249a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 9259a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 9269a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 9279a24b929SJack Pham #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 9289a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 9299a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 9309a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 9319a24b929SJack Pham #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 9329a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 9339a24b929SJack Pham #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 9349a24b929SJack Pham #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 9359a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 9369a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 9379a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 9389a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 9399a24b929SJack Pham #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 9409a24b929SJack Pham #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 9419a24b929SJack Pham #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 9429a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 9439a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 9449a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 9459a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 9469a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 9479a24b929SJack Pham #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300 9489a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 9499a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 9509a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 9519a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 9529a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 9539a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 9549a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c 9559a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 9569a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 9579a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328 9589a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c 9599a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330 9609a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334 9619a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338 9629a24b929SJack Pham #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c 9639a24b929SJack Pham #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340 9649a24b929SJack Pham #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344 9659a24b929SJack Pham #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348 9669a24b929SJack Pham #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c 9679a24b929SJack Pham #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350 9689a24b929SJack Pham #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 9699a24b929SJack Pham #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 9709a24b929SJack Pham 9717b675ba1SJonathan Marek /* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */ 9727b675ba1SJonathan Marek #define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618 9737b675ba1SJonathan Marek #define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638 9747b675ba1SJonathan Marek 9759a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 9769a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 9779a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 9789a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 9799a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 9809a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 9819a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 9829a24b929SJack Pham 9836edf7700SManivannan Sadhasivam /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 9846edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 9856edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 9866edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 9876edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 9886edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 9896edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 9906edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 9916edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 9926edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 9936edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 9946edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 9956edf7700SManivannan Sadhasivam 996920abc10SVinod Koul /* Only for QMP V5 PHY - QSERDES COM registers */ 997920abc10SVinod Koul #define QSERDES_V5_COM_PLL_IVCO 0x058 998920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 999920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 1000920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c 1001920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 1002920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 1003920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 1004920abc10SVinod Koul #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 1005920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 1006920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac 1007920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 1008920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 1009920abc10SVinod Koul #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc 1010920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 1011920abc10SVinod Koul #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 1012920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c 1013920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 1014920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_SEL 0x158 1015920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c 1016920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 1017920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 1018920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 1019920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 1020920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 1021920abc10SVinod Koul 102210c744d4SJack Pham /* Only for QMP V5 PHY - TX registers */ 102310c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 102410c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38 102510c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c 102610c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40 102710c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_1 0x84 102810c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_2 0x88 102910c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_3 0x8c 103010c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_4 0x90 103110c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_5 0x94 103210c744d4SJack Pham #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4 103310c744d4SJack Pham #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0 103410c744d4SJack Pham #define QSERDES_V5_TX_PI_QEC_CTRL 0xe4 1035920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 1036920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 1037920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 1038920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 103910c744d4SJack Pham 104010c744d4SJack Pham /* Only for QMP V5 PHY - RX registers */ 104110c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 104210c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 104310c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 104410c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 104510c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 104610c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 104710c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 104810c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 104910c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c 105010c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 105110c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 105210c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 105310c744d4SJack Pham #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 105410c744d4SJack Pham #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 105510c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 105610c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 105710c744d4SJack Pham #define QSERDES_V5_RX_RX_TERM_BW 0x080 105810c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 105910c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 106010c744d4SJack Pham #define QSERDES_V5_RX_GM_CAL 0x0dc 106110c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 106210c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 106310c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 106410c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 106510c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 106610c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 106710c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 106810c744d4SJack Pham #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 106910c744d4SJack Pham #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 107010c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 107110c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c 107210c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_LVL 0x120 107310c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 107410c744d4SJack Pham #define QSERDES_V5_RX_RX_BAND 0x128 107510c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 107610c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 107710c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 107810c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 107910c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c 108010c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 108110c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 108210c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 108310c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c 108410c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 108510c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 108610c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 108710c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 108810c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 108910c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 109010c744d4SJack Pham #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 109110c744d4SJack Pham #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 109210c744d4SJack Pham #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 109310c744d4SJack Pham #define QSERDES_V5_RX_VTH_CODE 0x1b0 109410c744d4SJack Pham 1095920abc10SVinod Koul /* Only for QMP V5 PHY - UFS PCS registers */ 1096920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 1097920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 1098920abc10SVinod Koul #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 1099920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 1100920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 1101920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 1102920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 1103920abc10SVinod Koul #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 1104920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 1105920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 1106920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 1107920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 1108920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 1109920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 1110920abc10SVinod Koul #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 1111920abc10SVinod Koul 111210c744d4SJack Pham /* Only for QMP V5 PHY - USB3 have different offsets than V4 */ 111310c744d4SJack Pham #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x300 111410c744d4SJack Pham #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 111510c744d4SJack Pham #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 111610c744d4SJack Pham #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 111710c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 111810c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 111910c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 112010c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x31c 112110c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 112210c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 112310c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x328 112410c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x32c 112510c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x330 112610c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x334 112710c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x338 112810c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x33c 112910c744d4SJack Pham #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x340 113010c744d4SJack Pham #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x344 113110c744d4SJack Pham #define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x348 113210c744d4SJack Pham #define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x34c 113310c744d4SJack Pham #define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x350 113410c744d4SJack Pham #define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x354 113510c744d4SJack Pham #define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x358 113610c744d4SJack Pham #define QPHY_V5_PCS_USB3_TEST_CONTROL 0x35c 113710c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x360 113810c744d4SJack Pham 113910c744d4SJack Pham /* Only for QMP V5 PHY - UNI has 0x1000 offset for PCS_USB3 regs */ 114010c744d4SJack Pham #define QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x1018 114110c744d4SJack Pham #define QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x103c 114210c744d4SJack Pham 1143e2248617SManu Gautam #endif 1144