1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 99e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com.h" 109e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx.h" 119e1bae6dSDmitry Baryshkov 12a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v3.h" 13a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v3.h" 14a7fc833eSDmitry Baryshkov 15*32d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v4.h" 16*32d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v4.h" 17*32d2cf53SDmitry Baryshkov 18520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ 19520264dbSSelvam Sathappan Periakaruppan 20520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TIMER 0x00c 21520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER1 0x01c 22520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER2 0x020 23520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 24520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 25520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 26520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 27520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 28520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_ENABLE1 0x040 29520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYS_CLK_CTRL 0x044 30520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 31520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_IVCO 0x050 32520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 33520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 34520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 35520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 36520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TRIM 0x074 37520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 38520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c 39520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE0 0x080 40520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE1 0x084 41520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 42fe841d5bSJohan Hovold #define QSERDES_PLL_PLL_RCTRL_MODE1 0x08c 43520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 44520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 45520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 46520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 47520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_RESETSM_CNTRL 0x0b0 48520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP_EN 0x0c4 49520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE0 0x0cc 50520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE1 0x0d0 51520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 52520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc 53520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 54520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 55520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 56fe841d5bSJohan Hovold #define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0ec 57520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 58520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 59520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 60520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c 61520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_MAP 0x120 62520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 63520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 64520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c 65520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 66520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c 67520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 68520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_SELECT 0x16c 69520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_HSCLK_SEL 0x170 70520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV 0x17c 71520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORE_CLK_EN 0x184 72520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CMN_CONFIG 0x18c 73520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 74520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 75520264dbSSelvam Sathappan Periakaruppan 76e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 776cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04 786cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24 796cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x28 806cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x34 816cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x38 826cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x3c 836cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x40 846cad2983SDmitry Baryshkov #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x54 856cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x58 866cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x60 876cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x64 886cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x6c 896cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x80 906cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x84 916cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x88 926cad2983SDmitry Baryshkov #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 936cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 946cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc 956cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c 966cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140 976cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148 986cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154 996cad2983SDmitry Baryshkov #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 1006cad2983SDmitry Baryshkov #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac 1016cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 1026cad2983SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 1036cad2983SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 104e2248617SManu Gautam 1059a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 1069c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 1079c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 1089c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 1099c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 1109c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 1119c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 1129c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 1139c7761a3SManu Gautam 114a7fc833eSDmitry Baryshkov /* QSERDES V3 COM bits */ 11552e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 11652e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 11752e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 11852e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 11952e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 12052e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 12152e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 1229c7761a3SManu Gautam 123a7fc833eSDmitry Baryshkov /* QSERDES V3 TX bits */ 12452e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 12552e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 12652e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 12752e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 12852e013d0SStephen Boyd 1299c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 1309c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 1319c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 1329c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 1339c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 1349c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 1359c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 1369c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 137cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 138cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 1399c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 1409c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 1419c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 1429c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 1439c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 1449c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 1459c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 1469c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 1479c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 1489c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 1499c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 1509c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 1519c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 1529c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 1539c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 1549c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 1559c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 1569c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 1579c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 1589c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 1599c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 1609c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 1619c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 1629c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 1639c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 1649c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 1659c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 1669c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 16773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 1689c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 1699c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 1709c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 1719c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 1729c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 1739c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 1749c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 1759c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 176cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 177cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 178cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 179cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 18073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 18173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 18273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 183cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 184cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 1859c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 18673d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 18773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 188f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 189f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 1909c7761a3SManu Gautam 191ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 192ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 19373d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 19473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 19573d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 19673d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 19773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 198ac0d2399SManu Gautam 1995c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 2005c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 2015c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 2025c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 2035c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 2045c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 2055c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 20652e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 20752e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 20852e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 20952e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 21052e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 21152e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 21252e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 2135c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 2145c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 2155c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 2165c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 2175c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 2185c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 2195c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 2205c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 2215c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 2225c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 2235c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 22452e013d0SStephen Boyd 2255c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 22652e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 22752e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 22852e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 22952e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 23052e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 23152e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 23252e013d0SStephen Boyd 23352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 23452e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 23552e013d0SStephen Boyd 23652e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 23752e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 23852e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 23952e013d0SStephen Boyd 24052e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 24152e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 24252e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 24352e013d0SStephen Boyd 24452e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 24552e013d0SStephen Boyd 246a88c85eeSVinod Koul 247be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - TX registers */ 248be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 249be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 250be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 251be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 252be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 253be0ddb5dSManivannan Sadhasivam 254aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 255aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 256aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 257aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 258aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 259aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 260aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 261aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 262aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 263aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 264aff188feSDmitry Baryshkov 265be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - RX registers */ 266be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 267be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 268be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 269be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_3 0x110 270be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 271be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 272be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 273be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 274be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 275be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 276be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 277be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 278be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 279be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 280be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 281be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 282be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 283be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 284be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 285be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 286be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 287be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 288be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 289be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 290be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 291be0ddb5dSManivannan Sadhasivam 2929a24b929SJack Pham /* Only for QMP V4 PHY - UFS PCS registers */ 29378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PHY_START 0x000 29478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 29578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_SW_RESET 0x008 29678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 29778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 29878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 29978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 30078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 30178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 30278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 30378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 30478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 30578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 30678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 30778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 30878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 30978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 31078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 31178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 31278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 313a88c85eeSVinod Koul 314909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 315909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 316909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 317909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 318909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 319909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 320909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 321909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 322909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 323909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 324909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 325909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 326909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 327909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 328909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 329909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 330909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 331909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 332909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 333909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 334909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 335909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 336909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 337909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 338909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 339909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 340909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 341909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 342909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 343909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 344909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 345909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 346909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 347909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 348909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 349909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 350909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 351909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 352909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 353909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 354909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 355909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 356909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 357909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 358909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 359909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 360909a5c78SBjorn Andersson 361909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 362909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 363909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 364909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 365909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 366909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 367909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 368909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 369909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 370909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 371909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 372909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 373909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 374909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 375909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 376909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 377909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 378909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 379909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 380909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 381909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 382909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 383909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 384909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 385909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 386909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 387909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 388909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 389909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 390909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 391909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 392909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 393909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 394909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 395909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 396909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 397909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 398909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 399909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 400909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 401909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 402909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 403909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 404909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 405909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 406909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 407909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 408909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 409909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 410909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 411909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 412909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 413909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 414909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 415909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 416909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 417909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 418909a5c78SBjorn Andersson 419909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 420909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 421909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 422909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 423909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 424909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 425909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 426909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 427909a5c78SBjorn Andersson 4289a24b929SJack Pham /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 4299a24b929SJack Pham #define QPHY_V4_PCS_SW_RESET 0x000 4309a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID0 0x004 4319a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID1 0x008 4329a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID2 0x00c 4339a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID3 0x010 4349a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS1 0x014 4359a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS2 0x018 4369a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS3 0x01c 4379a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS4 0x020 4389a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS5 0x024 4399a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS6 0x028 4409a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS7 0x02c 4419a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 4429a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 4439a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 4449a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 4459a24b929SJack Pham #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 4469a24b929SJack Pham #define QPHY_V4_PCS_START_CONTROL 0x044 4479a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 4489a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 4499a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 4509a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 4519a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 4529a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 4539a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 4549a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 4559a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 4569a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 4579a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 4589a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 4599a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 4609a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 4619a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 4629a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 4639a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 4649a24b929SJack Pham #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 4659a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 4669a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 4679a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL1 0x098 4689a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 4699a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 4709a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 4719a24b929SJack Pham #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 4729a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 4739a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 4749a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 4759a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 4769a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 4779a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 4789a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 4799a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 4809a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 4819a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 4829a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 4839a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 4849a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 4859a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 4869a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 4879a24b929SJack Pham #define QPHY_V4_PCS_BIST_CTRL 0x0e8 4889a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 4899a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 4909a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 4919a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 4929a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 4939a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT3 0x100 4949a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT4 0x104 4959a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT5 0x108 4969a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT6 0x10c 4979a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT7 0x110 4989a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT8 0x114 4999a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT9 0x118 5009a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT10 0x11c 5019a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT11 0x120 5029a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT12 0x124 5039a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT13 0x128 5049a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT14 0x12c 5059a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT15 0x130 5069a24b929SJack Pham #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 5079a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 5089a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 5099a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 5109a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 5119a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 5129a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 5139a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 5149a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 5159a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 5169a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 5179a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 5189a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 5199a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 5209a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 5219a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 5229a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 5239a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 5249a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 5259a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 5269a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 5279a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 5289a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 5299a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 5309a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 5319a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 5329a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 5339a24b929SJack Pham #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 5349a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 5359a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 5369a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 5379a24b929SJack Pham #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 5389a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 5399a24b929SJack Pham #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 5409a24b929SJack Pham #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 5419a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 5429a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 5439a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 5449a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 5459a24b929SJack Pham #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 5469a24b929SJack Pham #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 5479a24b929SJack Pham #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 5489a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 5499a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 5509a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 5519a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 5529a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 553fc646236SDmitry Baryshkov 554fc646236SDmitry Baryshkov /* Only for QMP V4 PHY - USB3 PCS registers */ 555fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000 556fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 557fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 558fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 559fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 560fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 561fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 562fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c 563fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 564fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 565fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028 566fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c 567fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030 568fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034 569fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038 570fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c 571fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040 572fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044 573fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048 574fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c 575fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050 576fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054 577fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058 5789a24b929SJack Pham 579be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 580be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 581be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 582be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 583be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 584be0ddb5dSManivannan Sadhasivam 5859a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 5869a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 5879a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 5889a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 5899a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 5909a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 5919a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 5929a24b929SJack Pham 5936edf7700SManivannan Sadhasivam /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 5946edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 5956edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 5966edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 5976edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 5986edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 5996edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 6006edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 60160f23414SDmitry Baryshkov #define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0 6026edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 6036edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 6046edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 6056edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 6066edf7700SManivannan Sadhasivam 607be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 608be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 609be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 610be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 611be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 612be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 613be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 614be0ddb5dSManivannan Sadhasivam 615920abc10SVinod Koul /* Only for QMP V5 PHY - QSERDES COM registers */ 616107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_EN_CENTER 0x010 617107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_PER1 0x01c 618107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_PER2 0x020 619107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0 0x024 620107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0 0x028 621107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1 0x030 622107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1 0x034 6232c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_BIAS_EN_CLKBUFLR_EN 0x044 624107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_CLK_ENABLE1 0x048 625107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_SYSCLK_BUF_ENABLE 0x050 626920abc10SVinod Koul #define QSERDES_V5_COM_PLL_IVCO 0x058 627920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 628920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 629920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c 630920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 631920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 632920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 633920abc10SVinod Koul #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 634920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 6352c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_LOCK_CMP_CFG 0x0a8 636920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac 637920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 638920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 639920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 64074acf0eeSJohan Hovold #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc 641920abc10SVinod Koul #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 642107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START1_MODE0 0x0cc 643107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START2_MODE0 0x0d0 644107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START3_MODE0 0x0d4 645107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START1_MODE1 0x0d8 646107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START2_MODE1 0x0dc 647107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_DIV_FRAC_START3_MODE1 0x0e0 648920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c 649107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE1_MODE0 0x110 650107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE2_MODE0 0x114 651107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE1_MODE1 0x118 652107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_VCO_TUNE2_MODE1 0x11c 653920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 654107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_CLK_SELECT 0x154 655920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_SEL 0x158 656920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c 6572c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CORECLK_DIV_MODE0 0x168 658107ba9bfSDmitry Baryshkov #define QSERDES_V5_COM_CORECLK_DIV_MODE1 0x16c 6592c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CORE_CLK_EN 0x174 6602c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CMN_CONFIG 0x17c 6612c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_CMN_MISC1 0x19c 662488987b2SDmitry Baryshkov #define QSERDES_V5_COM_CMN_MODE 0x1a0 663488987b2SDmitry Baryshkov #define QSERDES_V5_COM_CMN_MODE_CONTD 0x1a4 6642c91bf6bSDmitry Baryshkov #define QSERDES_V5_COM_VCO_DC_LEVEL_CTRL 0x1a8 665920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 666920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 667920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 668920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 66974acf0eeSJohan Hovold #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 670920abc10SVinod Koul 67110c744d4SJack Pham /* Only for QMP V5 PHY - TX registers */ 67210c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 67310c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38 67410c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c 67510c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40 67610c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_1 0x84 67710c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_2 0x88 67810c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_3 0x8c 67910c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_4 0x90 68010c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_5 0x94 68110c744d4SJack Pham #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4 68210c744d4SJack Pham #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0 68310c744d4SJack Pham #define QSERDES_V5_TX_PI_QEC_CTRL 0xe4 684920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 685920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 686920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 687920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 68810c744d4SJack Pham 6892c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - TX registers */ 6902c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 6912c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 6922c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 6932c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 6942c91bf6bSDmitry Baryshkov 69510c744d4SJack Pham /* Only for QMP V5 PHY - RX registers */ 69610c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 69710c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 69810c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 69910c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 70010c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 70110c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 70210c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 70310c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 70410c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c 70510c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 70610c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 70710c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 70810c744d4SJack Pham #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 70910c744d4SJack Pham #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 71010c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 71110c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 71210c744d4SJack Pham #define QSERDES_V5_RX_RX_TERM_BW 0x080 713107ba9bfSDmitry Baryshkov #define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc 71410c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 71510c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 71610c744d4SJack Pham #define QSERDES_V5_RX_GM_CAL 0x0dc 71710c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 71810c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 71910c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 72010c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 72110c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 72210c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 72310c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 72410c744d4SJack Pham #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 72510c744d4SJack Pham #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 72610c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 72710c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c 72810c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_LVL 0x120 72910c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 73010c744d4SJack Pham #define QSERDES_V5_RX_RX_BAND 0x128 73110c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 73210c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 73310c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 73410c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 73510c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c 73610c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 73710c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 73810c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 73910c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c 74010c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 74110c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 74210c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 74310c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 74410c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 74510c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 74610c744d4SJack Pham #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 74710c744d4SJack Pham #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 74810c744d4SJack Pham #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 74910c744d4SJack Pham #define QSERDES_V5_RX_VTH_CODE 0x1b0 75010c744d4SJack Pham 7512c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - RX registers */ 7522c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 7532c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c 7542c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 7552c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c 7562c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 7572c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c 7582c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_3 0x090 7592c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 7602c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 7612c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 7622c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc 7632c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_GM_CAL 0x0ec 7642c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 7652c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 7662c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 7672c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c 7682c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 7692c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 7702c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c 7712c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 7722c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 7732c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 7742c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c 7752c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 7762c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 7772c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 7782c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c 7792c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 7802c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 7812c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 7822c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac 7832c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 7842c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 7852c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 7862c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 7872c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 7882c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc 7892c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 7902c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 7912c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 7922c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 7932c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 7942c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 7952c91bf6bSDmitry Baryshkov 796107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - USB/PCIe PCS registers */ 797107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc 7982c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 799107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 800107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 8012c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 8022c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 803107ba9bfSDmitry Baryshkov 804107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - PCS_PCIE registers */ 805107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 806107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 807107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 808107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 809107ba9bfSDmitry Baryshkov 8102c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - PCIe PCS registers */ 8112c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 8122c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 8132c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 8142c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 8152c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 8162c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 8172c91bf6bSDmitry Baryshkov 818920abc10SVinod Koul /* Only for QMP V5 PHY - UFS PCS registers */ 819920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 820920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 821920abc10SVinod Koul #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 822920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 823920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 824920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 825920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 826920abc10SVinod Koul #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 827920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 828920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 829920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 830920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 831920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 832920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 833920abc10SVinod Koul #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 834920abc10SVinod Koul 83510c744d4SJack Pham /* Only for QMP V5 PHY - USB3 have different offsets than V4 */ 836fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000 837fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 838fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 839fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 840fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 841fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 842fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 843fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c 844fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 845fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 846fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028 847fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c 848fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030 849fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034 850fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038 851fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c 852fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040 853fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044 854fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048 855fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c 856fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050 857fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054 858fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058 859fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c 860fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060 86110c744d4SJack Pham 862e2248617SManu Gautam #endif 863