1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 99e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com.h" 109e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx.h" 119e1bae6dSDmitry Baryshkov 12a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v3.h" 13a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v3.h" 14a7fc833eSDmitry Baryshkov 1532d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v4.h" 1632d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v4.h" 175fc21d1bSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v4_20.h" 1832d2cf53SDmitry Baryshkov 19f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v5.h" 20f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v5.h" 215fc21d1bSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v5_20.h" 22a2e927b0SBjorn Andersson #include "phy-qcom-qmp-qserdes-txrx-v5_5nm.h" 23f1f923adSDmitry Baryshkov 24*2df32d96SAbel Vesa #include "phy-qcom-qmp-qserdes-com-v6.h" 25*2df32d96SAbel Vesa 26147924ffSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-pll.h" 27520264dbSSelvam Sathappan Periakaruppan 285ae11aa4SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v2.h" 29e2248617SManu Gautam 3056a1fa09SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v3.h" 3156a1fa09SDmitry Baryshkov 3241ad371fSDmitry Baryshkov #include "phy-qcom-qmp-pcs-v4.h" 3341ad371fSDmitry Baryshkov 3425ad4a4cSDmitry Baryshkov #include "phy-qcom-qmp-pcs-v4_20.h" 3525ad4a4cSDmitry Baryshkov 36b7a2f882SDmitry Baryshkov #include "phy-qcom-qmp-pcs-v5.h" 37eb5793fbSDmitry Baryshkov 38883aebf6SManivannan Sadhasivam #include "phy-qcom-qmp-pcs-v5_20.h" 3987d71378SDmitry Baryshkov 409a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 419c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 429c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 439c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 449c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 459c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 469c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 479c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 489c7761a3SManu Gautam 49a7fc833eSDmitry Baryshkov /* QSERDES V3 COM bits */ 5052e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 5152e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 5252e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 5352e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 5452e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 5552e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 5652e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 579c7761a3SManu Gautam 58a7fc833eSDmitry Baryshkov /* QSERDES V3 TX bits */ 5952e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 6052e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 6152e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 6252e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 6352e013d0SStephen Boyd 645c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 655c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 665c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 675c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 685c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 695c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 705c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 7152e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 7252e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 7352e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 7452e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 7552e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 7652e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 7752e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 785c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 795c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 805c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 815c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 825c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 835c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 845c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 855c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 865c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 875c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 885c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 8952e013d0SStephen Boyd 905c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 9152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 9252e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 9352e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 9452e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 9552e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 9652e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 9752e013d0SStephen Boyd 9852e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 9952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 10052e013d0SStephen Boyd 10152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 10252e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 10352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 10452e013d0SStephen Boyd 10552e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 10652e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 10752e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 10852e013d0SStephen Boyd 10952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 11052e013d0SStephen Boyd 111aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 112aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 113aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 114aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 115aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 116aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 117aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 118aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 119aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 120aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 121aff188feSDmitry Baryshkov 1229a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 1239a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 1249a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 1259a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 1269a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 1279a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 1289a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 1299a24b929SJack Pham 130e2248617SManu Gautam #endif 131