1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 9520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - QSERDES PLL registers */ 10520264dbSSelvam Sathappan Periakaruppan 11520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TIMER 0x00c 12520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER1 0x01c 13520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_PER2 0x020 14520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE0 0x024 15520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE0 0x028 16520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE1_MODE1 0x02c 17520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SSC_STEP_SIZE2_MODE1 0x030 18520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CLKBUFLR_EN 0x03c 19520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_ENABLE1 0x040 20520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYS_CLK_CTRL 0x044 21520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_BUF_ENABLE 0x048 22520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_IVCO 0x050 23520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE0 0x054 24520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE0 0x058 25520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP1_MODE1 0x060 26520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP2_MODE1 0x064 27520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BG_TRIM 0x074 28520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE0 0x078 29520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_EP_DIV_MODE1 0x07c 30520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE0 0x080 31520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CP_CTRL_MODE1 0x084 32520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_RCTRL_MODE0 0x088 33520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_RCTRL_MODE1 0x08C 34520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE0 0x090 35520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_PLL_CCTRL_MODE1 0x094 36520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_BIAS_EN_CTRL_BY_PSM 0x0a4 37520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SYSCLK_EN_SEL 0x0a8 38520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_RESETSM_CNTRL 0x0b0 39520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_LOCK_CMP_EN 0x0c4 40520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE0 0x0cc 41520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DEC_START_MODE1 0x0d0 42520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE0 0x0d8 43520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE0 0x0dc 44520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START3_MODE0 0x0e0 45520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START1_MODE1 0x0e4 46520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START2_MODE1 0x0e8 47520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_DIV_FRAC_START3_MODE1 0x0eC 48520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE0 0x100 49520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE0 0x104 50520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN0_MODE1 0x108 51520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_INTEGLOOP_GAIN1_MODE1 0x10c 52520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_MAP 0x120 53520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE0 0x124 54520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE0 0x128 55520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE1_MODE1 0x12c 56520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE2_MODE1 0x130 57520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER1 0x13c 58520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_VCO_TUNE_TIMER2 0x140 59520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CLK_SELECT 0x16c 60520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_HSCLK_SEL 0x170 61520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV 0x17c 62520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORE_CLK_EN 0x184 63520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CMN_CONFIG 0x18c 64520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_SVS_MODE_CLK_SEL 0x194 65520264dbSSelvam Sathappan Periakaruppan #define QSERDES_PLL_CORECLK_DIV_MODE1 0x1b4 66520264dbSSelvam Sathappan Periakaruppan 67520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - QSERDES TX registers */ 68520264dbSSelvam Sathappan Periakaruppan 69520264dbSSelvam Sathappan Periakaruppan #define QSERDES_TX0_RES_CODE_LANE_OFFSET_TX 0x03c 70520264dbSSelvam Sathappan Periakaruppan #define QSERDES_TX0_HIGHZ_DRVR_EN 0x058 71520264dbSSelvam Sathappan Periakaruppan #define QSERDES_TX0_LANE_MODE_1 0x084 72520264dbSSelvam Sathappan Periakaruppan #define QSERDES_TX0_RCV_DETECT_LVL_2 0x09c 73520264dbSSelvam Sathappan Periakaruppan 74520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - QSERDES RX registers */ 75520264dbSSelvam Sathappan Periakaruppan 76520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_UCDR_FO_GAIN 0x008 77520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_UCDR_SO_GAIN 0x014 78520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_UCDR_SO_SATURATION_AND_ENABLE 0x034 79520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_UCDR_PI_CONTROLS 0x044 80520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL2 0x0ec 81520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL3 0x0f0 82520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_EQU_ADAPTOR_CNTRL4 0x0f4 83520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_IDAC_TSETTLE_LOW 0x0f8 84520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_IDAC_TSETTLE_HIGH 0x0fc 85520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 86520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_OFFSET_ADAPTOR_CNTRL2 0x114 87520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_SIGDET_ENABLES 0x118 88520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_SIGDET_CNTRL 0x11c 89520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_SIGDET_DEGLITCH_CNTRL 0x124 90520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_LOW 0x170 91520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_HIGH 0x174 92520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_HIGH2 0x178 93520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_HIGH3 0x17c 94520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_00_HIGH4 0x180 95520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_LOW 0x184 96520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_HIGH 0x188 97520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_HIGH2 0x18c 98520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_HIGH3 0x190 99520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_01_HIGH4 0x194 100520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_LOW 0x198 101520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_HIGH 0x19c 102520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_HIGH2 0x1a0 103520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_HIGH3 0x1a4 104520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_RX_MODE_10_HIGH4 0x1a8 105520264dbSSelvam Sathappan Periakaruppan #define QSERDES_RX0_DFE_EN_TIMER 0x1b4 106520264dbSSelvam Sathappan Periakaruppan 107520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - PCS registers */ 108520264dbSSelvam Sathappan Periakaruppan 109520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNTRL1 0x098 110520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNTRL2 0x09c 111520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNT_VAL_L 0x0a0 112520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_CNT_VAL_H_TOL 0x0a4 113520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_FLL_MAN_CODE 0x0a8 114520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_REFGEN_REQ_CONFIG1 0x0dc 115520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_G12S1_TXDEEMPH_M3P5DB 0x16c 116520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_RX_SIGDET_LVL 0x188 117520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 118520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 119520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_RX_DCC_CAL_CONFIG 0x1d8 120520264dbSSelvam Sathappan Periakaruppan #define PCS_COM_EQ_CONFIG5 0x1ec 121520264dbSSelvam Sathappan Periakaruppan 122520264dbSSelvam Sathappan Periakaruppan /* QMP V2 PHY for PCIE gen3 ports - PCS Misc registers */ 123520264dbSSelvam Sathappan Periakaruppan 124520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_POWER_STATE_CONFIG2 0x40c 125520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_POWER_STATE_CONFIG4 0x414 126520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x41c 127520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x440 128520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_H 0x444 129520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x448 130520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_H 0x44c 131520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_CONFIG2 0x45c 132520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG2 0x478 133520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG4 0x480 134520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_MODE2_CONFIG5 0x484 135520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_OSC_DTCT_ACTIONS 0x490 136520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_EQ_CONFIG1 0x4a0 137520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_EQ_CONFIG2 0x4a4 138520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_PRESET_P10_PRE 0x4bc 139520264dbSSelvam Sathappan Periakaruppan #define PCS_PCIE_PRESET_P10_POST 0x4e0 140520264dbSSelvam Sathappan Periakaruppan 141e2248617SManu Gautam /* Only for QMP V2 PHY - QSERDES COM registers */ 142e2248617SManu Gautam #define QSERDES_COM_BG_TIMER 0x00c 143e2248617SManu Gautam #define QSERDES_COM_SSC_EN_CENTER 0x010 144e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER1 0x014 145e2248617SManu Gautam #define QSERDES_COM_SSC_ADJ_PER2 0x018 146e2248617SManu Gautam #define QSERDES_COM_SSC_PER1 0x01c 147e2248617SManu Gautam #define QSERDES_COM_SSC_PER2 0x020 148e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE1 0x024 149e2248617SManu Gautam #define QSERDES_COM_SSC_STEP_SIZE2 0x028 150e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CLKBUFLR_EN 0x034 151e2248617SManu Gautam #define QSERDES_COM_CLK_ENABLE1 0x038 152e2248617SManu Gautam #define QSERDES_COM_SYS_CLK_CTRL 0x03c 153e2248617SManu Gautam #define QSERDES_COM_SYSCLK_BUF_ENABLE 0x040 154e2248617SManu Gautam #define QSERDES_COM_PLL_IVCO 0x048 155e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE0 0x04c 156e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE0 0x050 157e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE0 0x054 158e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP1_MODE1 0x058 159e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP2_MODE1 0x05c 160e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP3_MODE1 0x060 161e2248617SManu Gautam #define QSERDES_COM_BG_TRIM 0x070 162e2248617SManu Gautam #define QSERDES_COM_CLK_EP_DIV 0x074 163e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE0 0x078 164e2248617SManu Gautam #define QSERDES_COM_CP_CTRL_MODE1 0x07c 165e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE0 0x084 166e2248617SManu Gautam #define QSERDES_COM_PLL_RCTRL_MODE1 0x088 167e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE0 0x090 168e2248617SManu Gautam #define QSERDES_COM_PLL_CCTRL_MODE1 0x094 169e2248617SManu Gautam #define QSERDES_COM_BIAS_EN_CTRL_BY_PSM 0x0a8 170e2248617SManu Gautam #define QSERDES_COM_SYSCLK_EN_SEL 0x0ac 171e2248617SManu Gautam #define QSERDES_COM_RESETSM_CNTRL 0x0b4 172e2248617SManu Gautam #define QSERDES_COM_RESTRIM_CTRL 0x0bc 173e2248617SManu Gautam #define QSERDES_COM_RESCODE_DIV_NUM 0x0c4 174e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_EN 0x0c8 175e2248617SManu Gautam #define QSERDES_COM_LOCK_CMP_CFG 0x0cc 176e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE0 0x0d0 177e2248617SManu Gautam #define QSERDES_COM_DEC_START_MODE1 0x0d4 178e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE0 0x0dc 179e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE0 0x0e0 180e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE0 0x0e4 181e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START1_MODE1 0x0e8 182e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START2_MODE1 0x0ec 183e2248617SManu Gautam #define QSERDES_COM_DIV_FRAC_START3_MODE1 0x0f0 184e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE0 0x108 185e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE0 0x10c 186e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN0_MODE1 0x110 187e2248617SManu Gautam #define QSERDES_COM_INTEGLOOP_GAIN1_MODE1 0x114 188e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_CTRL 0x124 189e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_MAP 0x128 190e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE0 0x12c 191e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE0 0x130 192e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE1_MODE1 0x134 193e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE2_MODE1 0x138 194*152a810eSIskren Chernev #define QSERDES_COM_VCO_TUNE_INITVAL1 0x13c 195*152a810eSIskren Chernev #define QSERDES_COM_VCO_TUNE_INITVAL2 0x140 196e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER1 0x144 197e2248617SManu Gautam #define QSERDES_COM_VCO_TUNE_TIMER2 0x148 198e2248617SManu Gautam #define QSERDES_COM_BG_CTRL 0x170 199e2248617SManu Gautam #define QSERDES_COM_CLK_SELECT 0x174 200e2248617SManu Gautam #define QSERDES_COM_HSCLK_SEL 0x178 201e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV 0x184 202e2248617SManu Gautam #define QSERDES_COM_CORE_CLK_EN 0x18c 203e2248617SManu Gautam #define QSERDES_COM_C_READY_STATUS 0x190 204e2248617SManu Gautam #define QSERDES_COM_CMN_CONFIG 0x194 205e2248617SManu Gautam #define QSERDES_COM_SVS_MODE_CLK_SEL 0x19c 206e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS0 0x1a0 207e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS1 0x1a4 208e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS2 0x1a8 209e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS3 0x1ac 210e2248617SManu Gautam #define QSERDES_COM_DEBUG_BUS_SEL 0x1b0 211e2248617SManu Gautam #define QSERDES_COM_CORECLK_DIV_MODE1 0x1bc 212e2248617SManu Gautam 213e2248617SManu Gautam /* Only for QMP V2 PHY - TX registers */ 214afd55e6dSSivaprakash Murugesan #define QSERDES_TX_EMP_POST1_LVL 0x018 215afd55e6dSSivaprakash Murugesan #define QSERDES_TX_SLEW_CNTL 0x040 216e2248617SManu Gautam #define QSERDES_TX_RES_CODE_LANE_OFFSET 0x054 217e2248617SManu Gautam #define QSERDES_TX_DEBUG_BUS_SEL 0x064 218e2248617SManu Gautam #define QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN 0x068 219e2248617SManu Gautam #define QSERDES_TX_LANE_MODE 0x094 220e2248617SManu Gautam #define QSERDES_TX_RCV_DETECT_LVL_2 0x0ac 221e2248617SManu Gautam 222e2248617SManu Gautam /* Only for QMP V2 PHY - RX registers */ 223e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN_HALF 0x010 224e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_GAIN 0x01c 225*152a810eSIskren Chernev #define QSERDES_RX_UCDR_SVS_SO_GAIN_HALF 0x030 226*152a810eSIskren Chernev #define QSERDES_RX_UCDR_SVS_SO_GAIN_QUARTER 0x034 227*152a810eSIskren Chernev #define QSERDES_RX_UCDR_SVS_SO_GAIN_EIGHTH 0x038 228*152a810eSIskren Chernev #define QSERDES_RX_UCDR_SVS_SO_GAIN 0x03c 229e2248617SManu Gautam #define QSERDES_RX_UCDR_FASTLOCK_FO_GAIN 0x040 230e2248617SManu Gautam #define QSERDES_RX_UCDR_SO_SATURATION_AND_ENABLE 0x048 231e2248617SManu Gautam #define QSERDES_RX_RX_TERM_BW 0x090 232e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_LSB 0x0c4 233e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN1_MSB 0x0c8 234e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_LSB 0x0cc 235e2248617SManu Gautam #define QSERDES_RX_RX_EQ_GAIN2_MSB 0x0d0 236e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d8 237e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3 0x0dc 238e2248617SManu Gautam #define QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4 0x0e0 239e2248617SManu Gautam #define QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x108 240e2248617SManu Gautam #define QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x10c 241e2248617SManu Gautam #define QSERDES_RX_SIGDET_ENABLES 0x110 242e2248617SManu Gautam #define QSERDES_RX_SIGDET_CNTRL 0x114 243e2248617SManu Gautam #define QSERDES_RX_SIGDET_LVL 0x118 244e2248617SManu Gautam #define QSERDES_RX_SIGDET_DEGLITCH_CNTRL 0x11c 245e2248617SManu Gautam #define QSERDES_RX_RX_BAND 0x120 246e2248617SManu Gautam #define QSERDES_RX_RX_INTERFACE_MODE 0x12c 247e2248617SManu Gautam 248e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 249e2248617SManu Gautam #define QPHY_POWER_DOWN_CONTROL 0x04 250e2248617SManu Gautam #define QPHY_TXDEEMPH_M6DB_V0 0x24 251e2248617SManu Gautam #define QPHY_TXDEEMPH_M3P5DB_V0 0x28 252*152a810eSIskren Chernev #define QPHY_TX_LARGE_AMP_DRV_LVL 0x34 253*152a810eSIskren Chernev #define QPHY_TX_LARGE_AMP_POST_EMP_LVL 0x38 254*152a810eSIskren Chernev #define QPHY_TX_SMALL_AMP_DRV_LVL 0x3c 255*152a810eSIskren Chernev #define QPHY_TX_SMALL_AMP_POST_EMP_LVL 0x40 256e2248617SManu Gautam #define QPHY_ENDPOINT_REFCLK_DRIVE 0x54 257e2248617SManu Gautam #define QPHY_RX_IDLE_DTCT_CNTRL 0x58 258e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG1 0x60 259e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG2 0x64 260e2248617SManu Gautam #define QPHY_POWER_STATE_CONFIG4 0x6c 261e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG1 0x80 262e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG2 0x84 263e2248617SManu Gautam #define QPHY_LOCK_DETECT_CONFIG3 0x88 264e2248617SManu Gautam #define QPHY_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 265e2248617SManu Gautam #define QPHY_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 266*152a810eSIskren Chernev #define QPHY_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc 267*152a810eSIskren Chernev #define QPHY_RX_SYM_RESYNC_CTRL 0x13c 268*152a810eSIskren Chernev #define QPHY_RX_MIN_HIBERN8_TIME 0x140 269*152a810eSIskren Chernev #define QPHY_RX_SIGDET_CTRL2 0x148 270*152a810eSIskren Chernev #define QPHY_RX_PWM_GEAR_BAND 0x154 271e2248617SManu Gautam #define QPHY_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1A8 272e2248617SManu Gautam #define QPHY_OSC_DTCT_ACTIONS 0x1AC 273e2248617SManu Gautam #define QPHY_RX_SIGDET_LVL 0x1D8 274e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1DC 275e2248617SManu Gautam #define QPHY_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1E0 276e2248617SManu Gautam 2779a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 2789c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 2799c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 2809c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 2819c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 2829c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 2839c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 2849c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 2859c7761a3SManu Gautam 2869c7761a3SManu Gautam /* Only for QMP V3 PHY - QSERDES COM registers */ 28752e013d0SStephen Boyd #define QSERDES_V3_COM_ATB_SEL1 0x000 28852e013d0SStephen Boyd #define QSERDES_V3_COM_ATB_SEL2 0x004 28952e013d0SStephen Boyd #define QSERDES_V3_COM_FREQ_UPDATE 0x008 2909c7761a3SManu Gautam #define QSERDES_V3_COM_BG_TIMER 0x00c 2919c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_EN_CENTER 0x010 2929c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER1 0x014 2939c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_ADJ_PER2 0x018 2949c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER1 0x01c 2959c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_PER2 0x020 2969c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE1 0x024 2979c7761a3SManu Gautam #define QSERDES_V3_COM_SSC_STEP_SIZE2 0x028 298*152a810eSIskren Chernev #define QSERDES_V3_COM_POST_DIV 0x02c 299*152a810eSIskren Chernev #define QSERDES_V3_COM_POST_DIV_MUX 0x030 3009c7761a3SManu Gautam #define QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN 0x034 30152e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 30252e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 30352e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 30452e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 30552e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 30652e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 30752e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 3089c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_ENABLE1 0x038 3099c7761a3SManu Gautam #define QSERDES_V3_COM_SYS_CLK_CTRL 0x03c 3109c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_BUF_ENABLE 0x040 311*152a810eSIskren Chernev #define QSERDES_V3_COM_PLL_EN 0x044 3129c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_IVCO 0x048 3139c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE0 0x098 3149c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE0 0x09c 3159c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE0 0x0a0 3169c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP1_MODE1 0x0a4 3179c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP2_MODE1 0x0a8 3189c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP3_MODE1 0x0ac 3199c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_EP_DIV 0x05c 3209c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE0 0x060 3219c7761a3SManu Gautam #define QSERDES_V3_COM_CP_CTRL_MODE1 0x064 3229c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE0 0x068 3239c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_RCTRL_MODE1 0x06c 3249c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE0 0x070 3259c7761a3SManu Gautam #define QSERDES_V3_COM_PLL_CCTRL_MODE1 0x074 3269c7761a3SManu Gautam #define QSERDES_V3_COM_SYSCLK_EN_SEL 0x080 3279c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL 0x088 3289c7761a3SManu Gautam #define QSERDES_V3_COM_RESETSM_CNTRL2 0x08c 3299c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_EN 0x090 3309c7761a3SManu Gautam #define QSERDES_V3_COM_LOCK_CMP_CFG 0x094 3319c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE0 0x0b0 3329c7761a3SManu Gautam #define QSERDES_V3_COM_DEC_START_MODE1 0x0b4 3339c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE0 0x0b8 3349c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE0 0x0bc 3359c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE0 0x0c0 3369c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START1_MODE1 0x0c4 3379c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START2_MODE1 0x0c8 3389c7761a3SManu Gautam #define QSERDES_V3_COM_DIV_FRAC_START3_MODE1 0x0cc 339a51969faSJeffrey Hugo #define QSERDES_V3_COM_INTEGLOOP_INITVAL 0x0d0 3409c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0 0x0d8 3419c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0 0x0dc 3429c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE1 0x0e0 3439c7761a3SManu Gautam #define QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE1 0x0e4 3449c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_CTRL 0x0ec 3459c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_MAP 0x0f0 3469c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE0 0x0f4 3479c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE0 0x0f8 3489c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE1_MODE1 0x0fc 3499c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE2_MODE1 0x100 350cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL1 0x104 351cc31cdbeSCan Guo #define QSERDES_V3_COM_VCO_TUNE_INITVAL2 0x108 3529c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER1 0x11c 3539c7761a3SManu Gautam #define QSERDES_V3_COM_VCO_TUNE_TIMER2 0x120 3549c7761a3SManu Gautam #define QSERDES_V3_COM_CLK_SELECT 0x138 3559c7761a3SManu Gautam #define QSERDES_V3_COM_HSCLK_SEL 0x13c 3569c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE0 0x148 3579c7761a3SManu Gautam #define QSERDES_V3_COM_CORECLK_DIV_MODE1 0x14c 3589c7761a3SManu Gautam #define QSERDES_V3_COM_CORE_CLK_EN 0x154 3599c7761a3SManu Gautam #define QSERDES_V3_COM_C_READY_STATUS 0x158 3609c7761a3SManu Gautam #define QSERDES_V3_COM_CMN_CONFIG 0x15c 3619c7761a3SManu Gautam #define QSERDES_V3_COM_SVS_MODE_CLK_SEL 0x164 3629c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS0 0x168 3639c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS1 0x16c 3649c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS2 0x170 3659c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS3 0x174 3669c7761a3SManu Gautam #define QSERDES_V3_COM_DEBUG_BUS_SEL 0x178 367a51969faSJeffrey Hugo #define QSERDES_V3_COM_CMN_MODE 0x184 3689c7761a3SManu Gautam 3699c7761a3SManu Gautam /* Only for QMP V3 PHY - TX registers */ 37052e013d0SStephen Boyd #define QSERDES_V3_TX_BIST_MODE_LANENO 0x000 37152e013d0SStephen Boyd #define QSERDES_V3_TX_CLKBUF_ENABLE 0x008 37252e013d0SStephen Boyd #define QSERDES_V3_TX_TX_EMP_POST1_LVL 0x00c 37352e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 37452e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 37552e013d0SStephen Boyd 37652e013d0SStephen Boyd #define QSERDES_V3_TX_TX_DRV_LVL 0x01c 37752e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 37852e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 37952e013d0SStephen Boyd 38052e013d0SStephen Boyd #define QSERDES_V3_TX_RESET_TSYNC_EN 0x024 38152e013d0SStephen Boyd #define QSERDES_V3_TX_PRE_STALL_LDO_BOOST_EN 0x028 38252e013d0SStephen Boyd 38352e013d0SStephen Boyd #define QSERDES_V3_TX_TX_BAND 0x02c 38452e013d0SStephen Boyd #define QSERDES_V3_TX_SLEW_CNTL 0x030 38552e013d0SStephen Boyd #define QSERDES_V3_TX_INTERFACE_SELECT 0x034 38652e013d0SStephen Boyd #define QSERDES_V3_TX_RES_CODE_LANE_TX 0x03c 38752e013d0SStephen Boyd #define QSERDES_V3_TX_RES_CODE_LANE_RX 0x040 3889c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX 0x044 3899c7761a3SManu Gautam #define QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX 0x048 3909c7761a3SManu Gautam #define QSERDES_V3_TX_DEBUG_BUS_SEL 0x058 39152e013d0SStephen Boyd #define QSERDES_V3_TX_TRANSCEIVER_BIAS_EN 0x05c 3929c7761a3SManu Gautam #define QSERDES_V3_TX_HIGHZ_DRVR_EN 0x060 39352e013d0SStephen Boyd #define QSERDES_V3_TX_TX_POL_INV 0x064 39452e013d0SStephen Boyd #define QSERDES_V3_TX_PARRATE_REC_DETECT_IDLE_EN 0x068 3959c7761a3SManu Gautam #define QSERDES_V3_TX_LANE_MODE_1 0x08c 3969c7761a3SManu Gautam #define QSERDES_V3_TX_RCV_DETECT_LVL_2 0x0a4 39752e013d0SStephen Boyd #define QSERDES_V3_TX_TRAN_DRVR_EMP_EN 0x0c0 39852e013d0SStephen Boyd #define QSERDES_V3_TX_TX_INTERFACE_MODE 0x0c4 39952e013d0SStephen Boyd #define QSERDES_V3_TX_VMODE_CTRL1 0x0f0 4009c7761a3SManu Gautam 4019c7761a3SManu Gautam /* Only for QMP V3 PHY - RX registers */ 402a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FO_GAIN 0x008 4039c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN_HALF 0x00c 4049c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_GAIN 0x014 405cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_HALF 0x024 406cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN_QUARTER 0x028 407cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_SVS_SO_GAIN 0x02c 4089c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN 0x030 4099c7761a3SManu Gautam #define QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 410cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 411a51969faSJeffrey Hugo #define QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 412cc31cdbeSCan Guo #define QSERDES_V3_RX_UCDR_PI_CONTROLS 0x044 4139c7761a3SManu Gautam #define QSERDES_V3_RX_RX_TERM_BW 0x07c 414f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL1 0x0bc 415f6721e5cSManu Gautam #define QSERDES_V3_RX_VGA_CAL_CNTRL2 0x0c0 4169c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_LSB 0x0c8 4179c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_GAIN2_MSB 0x0cc 4189c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2 0x0d4 4199c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3 0x0d8 4209c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4 0x0dc 4219c7761a3SManu Gautam #define QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x0f8 4229c7761a3SManu Gautam #define QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x0fc 4239c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_ENABLES 0x100 4249c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_CNTRL 0x104 4259c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_LVL 0x108 4269c7761a3SManu Gautam #define QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL 0x10c 4279c7761a3SManu Gautam #define QSERDES_V3_RX_RX_BAND 0x110 4289c7761a3SManu Gautam #define QSERDES_V3_RX_RX_INTERFACE_MODE 0x11c 429f6721e5cSManu Gautam #define QSERDES_V3_RX_RX_MODE_00 0x164 43073d7ec89SMarc Gonzalez #define QSERDES_V3_RX_RX_MODE_01 0x168 4319c7761a3SManu Gautam 4329c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 4339c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 4349c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 4359c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 4369c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 4379c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 4389c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 4399c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 440cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 441cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 4429c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 4439c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 4449c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 4459c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 4469c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 4479c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 4489c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 4499c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 4509c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 4519c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 4529c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 4539c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 4549c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 4559c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 4569c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 4579c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 4589c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 4599c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 4609c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 4619c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 4629c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 4639c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 4649c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 4659c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 4669c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 4679c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 4689c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 4699c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 47073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 4719c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 4729c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 4739c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 4749c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 4759c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 4769c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 4779c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 4789c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 479cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 480cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 481cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 482cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 48373d7ec89SMarc Gonzalez #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 48473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 48573d7ec89SMarc Gonzalez #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 486cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 487cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 4889c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 48973d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 49073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 491f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 492f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 4939c7761a3SManu Gautam 494ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 495ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 49673d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 49773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 49873d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 49973d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 50073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 501ac0d2399SManu Gautam 5025c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 5035c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 5045c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 5055c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 5065c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 5075c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 5085c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 50952e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 51052e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 51152e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 51252e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 51352e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 51452e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 51552e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 5165c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 5175c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 5185c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 5195c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 5205c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 5215c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 5225c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 5235c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 5245c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 5255c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 5265c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 52752e013d0SStephen Boyd 5285c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 52952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 53052e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 53152e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 53252e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 53352e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 53452e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 53552e013d0SStephen Boyd 53652e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 53752e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 53852e013d0SStephen Boyd 53952e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 54052e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 54152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 54252e013d0SStephen Boyd 54352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 54452e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 54552e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 54652e013d0SStephen Boyd 54752e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 54852e013d0SStephen Boyd 549a88c85eeSVinod Koul /* Only for QMP V4 PHY - QSERDES COM registers */ 550aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BG_TIMER 0x00c 5519a24b929SJack Pham #define QSERDES_V4_COM_SSC_EN_CENTER 0x010 5529a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER1 0x01c 5539a24b929SJack Pham #define QSERDES_V4_COM_SSC_PER2 0x020 5549a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0 0x024 5559a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0 0x028 5569a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1 0x030 5579a24b929SJack Pham #define QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1 0x034 558aff188feSDmitry Baryshkov #define QSERDES_V4_COM_BIAS_EN_CLKBUFLR_EN 0x044 5596edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_ENABLE1 0x048 560aff188feSDmitry Baryshkov #define QSERDES_V4_COM_SYS_CLK_CTRL 0x04c 5619a24b929SJack Pham #define QSERDES_V4_COM_SYSCLK_BUF_ENABLE 0x050 562a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_IVCO 0x058 563a88c85eeSVinod Koul #define QSERDES_V4_COM_CMN_IPTRIM 0x060 564a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE0 0x074 565a88c85eeSVinod Koul #define QSERDES_V4_COM_CP_CTRL_MODE1 0x078 566a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE0 0x07c 567a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_RCTRL_MODE1 0x080 568a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE0 0x084 569a88c85eeSVinod Koul #define QSERDES_V4_COM_PLL_CCTRL_MODE1 0x088 570a88c85eeSVinod Koul #define QSERDES_V4_COM_SYSCLK_EN_SEL 0x094 571aff188feSDmitry Baryshkov #define QSERDES_V4_COM_RESETSM_CNTRL 0x09c 572a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP_EN 0x0a4 573be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_LOCK_CMP_CFG 0x0a8 574a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE0 0x0ac 575a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE0 0x0b0 576a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP1_MODE1 0x0b4 577a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE0 0x0bc 578a88c85eeSVinod Koul #define QSERDES_V4_COM_LOCK_CMP2_MODE1 0x0b8 579a88c85eeSVinod Koul #define QSERDES_V4_COM_DEC_START_MODE1 0x0c4 5809a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE0 0x0cc 5819a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE0 0x0d0 5829a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE0 0x0d4 5839a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START1_MODE1 0x0d8 5849a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START2_MODE1 0x0dc 5859a24b929SJack Pham #define QSERDES_V4_COM_DIV_FRAC_START3_MODE1 0x0e0 586aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE0 0x0ec 587aff188feSDmitry Baryshkov #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE0 0x0f0 588be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTEGLOOP_GAIN0_MODE1 0x0f4 589be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTEGLOOP_GAIN1_MODE1 0x0f8 590aff188feSDmitry Baryshkov #define QSERDES_V4_COM_VCO_TUNE_CTRL 0x108 591a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_MAP 0x10c 5929a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE0 0x110 5939a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE0 0x114 5949a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE1_MODE1 0x118 5959a24b929SJack Pham #define QSERDES_V4_COM_VCO_TUNE2_MODE1 0x11c 596a88c85eeSVinod Koul #define QSERDES_V4_COM_VCO_TUNE_INITVAL2 0x124 597aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_STATUS 0x140 5986edf7700SManivannan Sadhasivam #define QSERDES_V4_COM_CLK_SELECT 0x154 599a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_SEL 0x158 600a88c85eeSVinod Koul #define QSERDES_V4_COM_HSCLK_HS_SWITCH_SEL 0x15c 601aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORECLK_DIV_MODE0 0x168 6029a24b929SJack Pham #define QSERDES_V4_COM_CORECLK_DIV_MODE1 0x16c 603aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CORE_CLK_EN 0x174 604aff188feSDmitry Baryshkov #define QSERDES_V4_COM_C_READY_STATUS 0x178 605aff188feSDmitry Baryshkov #define QSERDES_V4_COM_CMN_CONFIG 0x17c 6069a24b929SJack Pham #define QSERDES_V4_COM_SVS_MODE_CLK_SEL 0x184 607be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_CMN_MISC1 0x19c 608be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_INTERNAL_DIG_CORECLK_DIV 0x1a0 609be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_CMN_MODE 0x1a4 610be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_VCO_DC_LEVEL_CTRL 0x1a8 611a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 612a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 613a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 614a88c85eeSVinod Koul #define QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 615be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 616a88c85eeSVinod Koul 617a88c85eeSVinod Koul /* Only for QMP V4 PHY - TX registers */ 618aff188feSDmitry Baryshkov #define QSERDES_V4_TX_CLKBUF_ENABLE 0x08 619aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_EMP_POST1_LVL 0x0c 620aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_DRV_LVL 0x14 621aff188feSDmitry Baryshkov #define QSERDES_V4_TX_RESET_TSYNC_EN 0x1c 622aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PRE_STALL_LDO_BOOST_EN 0x20 623aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_BAND 0x24 624aff188feSDmitry Baryshkov #define QSERDES_V4_TX_INTERFACE_SELECT 0x2c 6259a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_TX 0x34 6269a24b929SJack Pham #define QSERDES_V4_TX_RES_CODE_LANE_RX 0x38 6277b675ba1SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX 0x3c 62890b65347SJonathan Marek #define QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX 0x40 629aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRANSCEIVER_BIAS_EN 0x54 630aff188feSDmitry Baryshkov #define QSERDES_V4_TX_HIGHZ_DRVR_EN 0x58 631aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_POL_INV 0x5c 632aff188feSDmitry Baryshkov #define QSERDES_V4_TX_PARRATE_REC_DETECT_IDLE_EN 0x60 633a88c85eeSVinod Koul #define QSERDES_V4_TX_LANE_MODE_1 0x84 63490b65347SJonathan Marek #define QSERDES_V4_TX_LANE_MODE_2 0x88 6359a24b929SJack Pham #define QSERDES_V4_TX_RCV_DETECT_LVL_2 0x9c 636aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TRAN_DRVR_EMP_EN 0xb8 637aff188feSDmitry Baryshkov #define QSERDES_V4_TX_TX_INTERFACE_MODE 0xbc 638a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0xd8 639a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0xdC 640a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0xe0 641a88c85eeSVinod Koul #define QSERDES_V4_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0xe4 642aff188feSDmitry Baryshkov #define QSERDES_V4_TX_VMODE_CTRL1 0xe8 6439a24b929SJack Pham #define QSERDES_V4_TX_PI_QEC_CTRL 0x104 644a88c85eeSVinod Koul 645be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - TX registers */ 646be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 647be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 648be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 649be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 650be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 651be0ddb5dSManivannan Sadhasivam 652a88c85eeSVinod Koul /* Only for QMP V4 PHY - RX registers */ 653a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FO_GAIN 0x008 654a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_GAIN 0x014 655a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN 0x030 656a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 657a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 6589a24b929SJack Pham #define QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 659a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CONTROLS 0x044 660a88c85eeSVinod Koul #define QSERDES_V4_RX_UCDR_PI_CTRL2 0x048 6619a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH1 0x04c 6629a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_THRESH2 0x050 6639a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN1 0x054 6649a24b929SJack Pham #define QSERDES_V4_RX_UCDR_SB2_GAIN2 0x058 6659a24b929SJack Pham #define QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE 0x060 6666edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RCLK_AUXDATA_SEL 0x064 667a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_ENABLE 0x068 668a88c85eeSVinod Koul #define QSERDES_V4_RX_AC_JTAG_MODE 0x078 669a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_TERM_BW 0x080 6709a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL1 0x0d4 6719a24b929SJack Pham #define QSERDES_V4_RX_VGA_CAL_CNTRL2 0x0d8 6729a24b929SJack Pham #define QSERDES_V4_RX_GM_CAL 0x0dc 6736edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 674a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 675a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 676a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 677a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW 0x0f8 678a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 679a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_IDAC_MEASURE_TIME 0x100 6809a24b929SJack Pham #define QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 681a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 6826edf7700SManivannan Sadhasivam #define QSERDES_V4_RX_SIGDET_ENABLES 0x118 683a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_CNTRL 0x11c 684a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_LVL 0x120 685a88c85eeSVinod Koul #define QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL 0x124 686a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_BAND 0x128 687a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_LOW 0x170 688a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH 0x174 689a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH2 0x178 690a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH3 0x17c 691a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_00_HIGH4 0x180 692a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_LOW 0x184 693a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH 0x188 694a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH2 0x18c 695a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH3 0x190 696a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_01_HIGH4 0x194 697a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_LOW 0x198 698a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH 0x19c 699a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH2 0x1a0 700a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH3 0x1a4 701a88c85eeSVinod Koul #define QSERDES_V4_RX_RX_MODE_10_HIGH4 0x1a8 7029a24b929SJack Pham #define QSERDES_V4_RX_DFE_EN_TIMER 0x1b4 7039a24b929SJack Pham #define QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET 0x1b8 704a88c85eeSVinod Koul #define QSERDES_V4_RX_DCC_CTRL1 0x1bc 7059a24b929SJack Pham #define QSERDES_V4_RX_VTH_CODE 0x1c4 706a88c85eeSVinod Koul 707aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 708aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 709aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 710aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 711aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 712aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 713aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 714aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 715aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 716aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 717aff188feSDmitry Baryshkov 718be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - RX registers */ 719be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 720be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 721be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 722be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_3 0x110 723be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 724be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 725be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 726be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 727be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 728be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 729be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 730be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 731be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 732be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 733be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 734be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 735be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 736be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 737be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 738be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 739be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 740be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 741be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 742be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 743be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 744be0ddb5dSManivannan Sadhasivam 7459a24b929SJack Pham /* Only for QMP V4 PHY - UFS PCS registers */ 74678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PHY_START 0x000 74778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 74878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_SW_RESET 0x008 74978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 75078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 75178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 75278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 75378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 75478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 75578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 75678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 75778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 75878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 75978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 76078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 76178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 76278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 76378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 76478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 76578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 766a88c85eeSVinod Koul 767909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 768909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 769909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 770909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 771909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 772909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 773909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 774909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 775909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 776909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 777909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 778909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 779909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 780909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 781909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 782909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 783909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 784909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 785909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 786909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 787909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 788909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 789909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 790909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 791909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 792909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 793909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 794909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 795909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 796909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 797909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 798909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 799909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 800909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 801909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 802909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 803909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 804909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 805909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 806909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 807909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 808909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 809909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 810909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 811909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 812909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 813909a5c78SBjorn Andersson 814909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 815909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 816909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 817909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 818909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 819909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 820909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 821909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 822909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 823909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 824909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 825909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 826909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 827909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 828909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 829909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 830909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 831909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 832909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 833909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 834909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 835909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 836909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 837909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 838909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 839909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 840909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 841909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 842909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 843909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 844909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 845909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 846909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 847909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 848909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 849909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 850909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 851909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 852909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 853909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 854909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 855909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 856909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 857909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 858909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 859909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 860909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 861909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 862909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 863909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 864909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 865909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 866909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 867909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 868909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 869909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 870909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 871909a5c78SBjorn Andersson 872909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 873909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 874909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 875909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 876909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 877909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 878909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 879909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 880909a5c78SBjorn Andersson 8819a24b929SJack Pham /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 8829a24b929SJack Pham #define QPHY_V4_PCS_SW_RESET 0x000 8839a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID0 0x004 8849a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID1 0x008 8859a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID2 0x00c 8869a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID3 0x010 8879a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS1 0x014 8889a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS2 0x018 8899a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS3 0x01c 8909a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS4 0x020 8919a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS5 0x024 8929a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS6 0x028 8939a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS7 0x02c 8949a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 8959a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 8969a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 8979a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 8989a24b929SJack Pham #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 8999a24b929SJack Pham #define QPHY_V4_PCS_START_CONTROL 0x044 9009a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 9019a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 9029a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 9039a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 9049a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 9059a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 9069a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 9079a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 9089a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 9099a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 9109a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 9119a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 9129a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 9139a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 9149a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 9159a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 9169a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 9179a24b929SJack Pham #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 9189a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 9199a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 9209a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL1 0x098 9219a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 9229a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 9239a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 9249a24b929SJack Pham #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 9259a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 9269a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 9279a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 9289a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 9299a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 9309a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 9319a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 9329a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 9339a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 9349a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 9359a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 9369a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 9379a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 9389a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 9399a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 9409a24b929SJack Pham #define QPHY_V4_PCS_BIST_CTRL 0x0e8 9419a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 9429a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 9439a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 9449a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 9459a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 9469a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT3 0x100 9479a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT4 0x104 9489a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT5 0x108 9499a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT6 0x10c 9509a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT7 0x110 9519a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT8 0x114 9529a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT9 0x118 9539a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT10 0x11c 9549a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT11 0x120 9559a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT12 0x124 9569a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT13 0x128 9579a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT14 0x12c 9589a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT15 0x130 9599a24b929SJack Pham #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 9609a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 9619a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 9629a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 9639a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 9649a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 9659a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 9669a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 9679a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 9689a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 9699a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 9709a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 9719a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 9729a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 9739a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 9749a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 9759a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 9769a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 9779a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 9789a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 9799a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 9809a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 9819a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 9829a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 9839a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 9849a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 9859a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 9869a24b929SJack Pham #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 9879a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 9889a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 9899a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 9909a24b929SJack Pham #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 9919a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 9929a24b929SJack Pham #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 9939a24b929SJack Pham #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 9949a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 9959a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 9969a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 9979a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 9989a24b929SJack Pham #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 9999a24b929SJack Pham #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 10009a24b929SJack Pham #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 10019a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 10029a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 10039a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 10049a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 10059a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 10069a24b929SJack Pham #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x300 10079a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 10089a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 10099a24b929SJack Pham #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 10109a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 10119a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 10129a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 10139a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x31c 10149a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 10159a24b929SJack Pham #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 10169a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x328 10179a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x32c 10189a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x330 10199a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x334 10209a24b929SJack Pham #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x338 10219a24b929SJack Pham #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x33c 10229a24b929SJack Pham #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x340 10239a24b929SJack Pham #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x344 10249a24b929SJack Pham #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x348 10259a24b929SJack Pham #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x34c 10269a24b929SJack Pham #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x350 10279a24b929SJack Pham #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x354 10289a24b929SJack Pham #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x358 10299a24b929SJack Pham 1030be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 1031be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 1032be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 1033be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 1034be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 1035be0ddb5dSManivannan Sadhasivam 10367b675ba1SJonathan Marek /* Only for QMP V4 PHY - UNI has 0x300 offset for PCS_USB3 regs */ 10377b675ba1SJonathan Marek #define QPHY_V4_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x618 10387b675ba1SJonathan Marek #define QPHY_V4_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x638 10397b675ba1SJonathan Marek 10409a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 10419a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 10429a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 10439a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 10449a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 10459a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 10469a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 10479a24b929SJack Pham 10486edf7700SManivannan Sadhasivam /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 10496edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 10506edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 10516edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 10526edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 10536edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 10546edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 10556edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 10566edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 10576edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 10586edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 10596edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 10606edf7700SManivannan Sadhasivam 1061be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 1062be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 1063be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 1064be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 1065be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 1066be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 1067be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 1068be0ddb5dSManivannan Sadhasivam 1069920abc10SVinod Koul /* Only for QMP V5 PHY - QSERDES COM registers */ 1070920abc10SVinod Koul #define QSERDES_V5_COM_PLL_IVCO 0x058 1071920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE0 0x074 1072920abc10SVinod Koul #define QSERDES_V5_COM_CP_CTRL_MODE1 0x078 1073920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE0 0x07c 1074920abc10SVinod Koul #define QSERDES_V5_COM_PLL_RCTRL_MODE1 0x080 1075920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE0 0x084 1076920abc10SVinod Koul #define QSERDES_V5_COM_PLL_CCTRL_MODE1 0x088 1077920abc10SVinod Koul #define QSERDES_V5_COM_SYSCLK_EN_SEL 0x094 1078920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP_EN 0x0a4 1079920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE0 0x0ac 1080920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE0 0x0b0 1081920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP1_MODE1 0x0b4 1082920abc10SVinod Koul #define QSERDES_V5_COM_DEC_START_MODE0 0x0bc 1083920abc10SVinod Koul #define QSERDES_V5_COM_LOCK_CMP2_MODE1 0x0b8 1084920abc10SVinod Koul #define QSERDES_V5_COM_DEC_START_MODE1 0x0c4 1085920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_MAP 0x10c 1086920abc10SVinod Koul #define QSERDES_V5_COM_VCO_TUNE_INITVAL2 0x124 1087920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_SEL 0x158 1088920abc10SVinod Koul #define QSERDES_V5_COM_HSCLK_HS_SWITCH_SEL 0x15c 1089920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0 0x1ac 1090920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0 0x1b0 1091920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1 0x1b4 1092920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL 0x1bc 1093920abc10SVinod Koul #define QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1 0x1b8 1094920abc10SVinod Koul 109510c744d4SJack Pham /* Only for QMP V5 PHY - TX registers */ 109610c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x34 109710c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x38 109810c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x3c 109910c744d4SJack Pham #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x40 110010c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_1 0x84 110110c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_2 0x88 110210c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_3 0x8c 110310c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_4 0x90 110410c744d4SJack Pham #define QSERDES_V5_TX_LANE_MODE_5 0x94 110510c744d4SJack Pham #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0xa4 110610c744d4SJack Pham #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0xc0 110710c744d4SJack Pham #define QSERDES_V5_TX_PI_QEC_CTRL 0xe4 1108920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 1109920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 1110920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 1111920abc10SVinod Koul #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 111210c744d4SJack Pham 111310c744d4SJack Pham /* Only for QMP V5 PHY - RX registers */ 111410c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 111510c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 111610c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 111710c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 111810c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 111910c744d4SJack Pham #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 112010c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 112110c744d4SJack Pham #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 112210c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c 112310c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 112410c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 112510c744d4SJack Pham #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 112610c744d4SJack Pham #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 112710c744d4SJack Pham #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 112810c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 112910c744d4SJack Pham #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 113010c744d4SJack Pham #define QSERDES_V5_RX_RX_TERM_BW 0x080 113110c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 113210c744d4SJack Pham #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 113310c744d4SJack Pham #define QSERDES_V5_RX_GM_CAL 0x0dc 113410c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 113510c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 113610c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 113710c744d4SJack Pham #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 113810c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 113910c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 114010c744d4SJack Pham #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 114110c744d4SJack Pham #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 114210c744d4SJack Pham #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 114310c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 114410c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c 114510c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_LVL 0x120 114610c744d4SJack Pham #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 114710c744d4SJack Pham #define QSERDES_V5_RX_RX_BAND 0x128 114810c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 114910c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 115010c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 115110c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 115210c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c 115310c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 115410c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 115510c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 115610c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c 115710c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 115810c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 115910c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 116010c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 116110c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 116210c744d4SJack Pham #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 116310c744d4SJack Pham #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 116410c744d4SJack Pham #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 116510c744d4SJack Pham #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 116610c744d4SJack Pham #define QSERDES_V5_RX_VTH_CODE 0x1b0 116710c744d4SJack Pham 1168920abc10SVinod Koul /* Only for QMP V5 PHY - UFS PCS registers */ 1169920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 1170920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 1171920abc10SVinod Koul #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 1172920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 1173920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 1174920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 1175920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 1176920abc10SVinod Koul #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 1177920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 1178920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 1179920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 1180920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 1181920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 1182920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 1183920abc10SVinod Koul #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 1184920abc10SVinod Koul 118510c744d4SJack Pham /* Only for QMP V5 PHY - USB3 have different offsets than V4 */ 118610c744d4SJack Pham #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x300 118710c744d4SJack Pham #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x304 118810c744d4SJack Pham #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x308 118910c744d4SJack Pham #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x30c 119010c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x310 119110c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x314 119210c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x318 119310c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x31c 119410c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x320 119510c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x324 119610c744d4SJack Pham #define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x328 119710c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x32c 119810c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x330 119910c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x334 120010c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x338 120110c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x33c 120210c744d4SJack Pham #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x340 120310c744d4SJack Pham #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x344 120410c744d4SJack Pham #define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x348 120510c744d4SJack Pham #define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x34c 120610c744d4SJack Pham #define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x350 120710c744d4SJack Pham #define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x354 120810c744d4SJack Pham #define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x358 120910c744d4SJack Pham #define QPHY_V5_PCS_USB3_TEST_CONTROL 0x35c 121010c744d4SJack Pham #define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x360 121110c744d4SJack Pham 121210c744d4SJack Pham /* Only for QMP V5 PHY - UNI has 0x1000 offset for PCS_USB3 regs */ 121310c744d4SJack Pham #define QPHY_V5_PCS_USB3_UNI_LFPS_DET_HIGH_COUNT_VAL 0x1018 121410c744d4SJack Pham #define QPHY_V5_PCS_USB3_UNI_RXEQTRAINING_DFE_TIME_S2 0x103c 121510c744d4SJack Pham 1216e2248617SManu Gautam #endif 1217