1a3a06415SNishad Kamdar /* SPDX-License-Identifier: GPL-2.0 */ 2e2248617SManu Gautam /* 3e2248617SManu Gautam * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4e2248617SManu Gautam */ 5e2248617SManu Gautam 6e2248617SManu Gautam #ifndef QCOM_PHY_QMP_H_ 7e2248617SManu Gautam #define QCOM_PHY_QMP_H_ 8e2248617SManu Gautam 99e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com.h" 109e1bae6dSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx.h" 119e1bae6dSDmitry Baryshkov 12a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v3.h" 13a7fc833eSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v3.h" 14a7fc833eSDmitry Baryshkov 1532d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v4.h" 1632d2cf53SDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v4.h" 1732d2cf53SDmitry Baryshkov 18f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-com-v5.h" 19f1f923adSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-txrx-v5.h" 20f1f923adSDmitry Baryshkov 21*147924ffSDmitry Baryshkov #include "phy-qcom-qmp-qserdes-pll.h" 22520264dbSSelvam Sathappan Periakaruppan 23e2248617SManu Gautam /* Only for QMP V2 PHY - PCS registers */ 246cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_DOWN_CONTROL 0x04 256cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M6DB_V0 0x24 266cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TXDEEMPH_M3P5DB_V0 0x28 276cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_LARGE_AMP_DRV_LVL 0x34 286cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_LARGE_AMP_POST_EMP_LVL 0x38 296cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_SMALL_AMP_DRV_LVL 0x3c 306cad2983SDmitry Baryshkov #define QPHY_V2_PCS_TX_SMALL_AMP_POST_EMP_LVL 0x40 316cad2983SDmitry Baryshkov #define QPHY_V2_PCS_ENDPOINT_REFCLK_DRIVE 0x54 326cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_IDLE_DTCT_CNTRL 0x58 336cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG1 0x60 346cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG2 0x64 356cad2983SDmitry Baryshkov #define QPHY_V2_PCS_POWER_STATE_CONFIG4 0x6c 366cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG1 0x80 376cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG2 0x84 386cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LOCK_DETECT_CONFIG3 0x88 396cad2983SDmitry Baryshkov #define QPHY_V2_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0xa0 406cad2983SDmitry Baryshkov #define QPHY_V2_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0xa4 416cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_MIN_STALL_NOCONFIG_TIME_CAP 0xcc 426cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SYM_RESYNC_CTRL 0x13c 436cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_MIN_HIBERN8_TIME 0x140 446cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SIGDET_CTRL2 0x148 456cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_PWM_GEAR_BAND 0x154 466cad2983SDmitry Baryshkov #define QPHY_V2_PCS_PLL_LOCK_CHK_DLY_TIME_AUXCLK_LSB 0x1a8 476cad2983SDmitry Baryshkov #define QPHY_V2_PCS_OSC_DTCT_ACTIONS 0x1ac 486cad2983SDmitry Baryshkov #define QPHY_V2_PCS_RX_SIGDET_LVL 0x1d8 496cad2983SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 506cad2983SDmitry Baryshkov #define QPHY_V2_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 51e2248617SManu Gautam 529a24b929SJack Pham /* Only for QMP V3 & V4 PHY - DP COM registers */ 539c7761a3SManu Gautam #define QPHY_V3_DP_COM_PHY_MODE_CTRL 0x00 549c7761a3SManu Gautam #define QPHY_V3_DP_COM_SW_RESET 0x04 559c7761a3SManu Gautam #define QPHY_V3_DP_COM_POWER_DOWN_CTRL 0x08 569c7761a3SManu Gautam #define QPHY_V3_DP_COM_SWI_CTRL 0x0c 579c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_CTRL 0x10 589c7761a3SManu Gautam #define QPHY_V3_DP_COM_TYPEC_PWRDN_CTRL 0x14 599c7761a3SManu Gautam #define QPHY_V3_DP_COM_RESET_OVRD_CTRL 0x1c 609c7761a3SManu Gautam 61a7fc833eSDmitry Baryshkov /* QSERDES V3 COM bits */ 6252e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN 0x0001 6352e013d0SStephen Boyd # define QSERDES_V3_COM_BIAS_EN_MUX 0x0002 6452e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_R_EN 0x0004 6552e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_L_EN 0x0008 6652e013d0SStephen Boyd # define QSERDES_V3_COM_EN_SYSCLK_TX_SEL 0x0010 6752e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_L 0x0020 6852e013d0SStephen Boyd # define QSERDES_V3_COM_CLKBUF_RX_DRIVE_R 0x0040 699c7761a3SManu Gautam 70a7fc833eSDmitry Baryshkov /* QSERDES V3 TX bits */ 7152e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MASK 0x001f 7252e013d0SStephen Boyd # define DP_PHY_TXn_TX_EMP_POST1_LVL_MUX_EN 0x0020 7352e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MASK 0x001f 7452e013d0SStephen Boyd # define DP_PHY_TXn_TX_DRV_LVL_MUX_EN 0x0020 7552e013d0SStephen Boyd 769c7761a3SManu Gautam /* Only for QMP V3 PHY - PCS registers */ 779c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_DOWN_CONTROL 0x004 789c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V0 0x00c 799c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V1 0x010 809c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V2 0x014 819c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V3 0x018 829c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_V4 0x01c 839c7761a3SManu Gautam #define QPHY_V3_PCS_TXMGN_LS 0x020 84cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_LARGE_AMP_DRV_LVL 0x02c 85cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_SMALL_AMP_DRV_LVL 0x034 869c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V0 0x024 879c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0 0x028 889c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V1 0x02c 899c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1 0x030 909c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V2 0x034 919c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2 0x038 929c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V3 0x03c 939c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3 0x040 949c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_V4 0x044 959c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4 0x048 969c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M6DB_LS 0x04c 979c7761a3SManu Gautam #define QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS 0x050 989c7761a3SManu Gautam #define QPHY_V3_PCS_ENDPOINT_REFCLK_DRIVE 0x054 999c7761a3SManu Gautam #define QPHY_V3_PCS_RX_IDLE_DTCT_CNTRL 0x058 1009c7761a3SManu Gautam #define QPHY_V3_PCS_RATE_SLEW_CNTRL 0x05c 1019c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG1 0x060 1029c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG2 0x064 1039c7761a3SManu Gautam #define QPHY_V3_PCS_POWER_STATE_CONFIG4 0x06c 1049c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L 0x070 1059c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H 0x074 1069c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L 0x078 1079c7761a3SManu Gautam #define QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H 0x07c 1089c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG1 0x080 1099c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG2 0x084 1109c7761a3SManu Gautam #define QPHY_V3_PCS_LOCK_DETECT_CONFIG3 0x088 1119c7761a3SManu Gautam #define QPHY_V3_PCS_TSYNC_RSYNC_TIME 0x08c 1129c7761a3SManu Gautam #define QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x0a0 1139c7761a3SManu Gautam #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK 0x0a4 11473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_PLL_LOCK_CHK_DLY_TIME 0x0a8 1159c7761a3SManu Gautam #define QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK 0x0b0 1169c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME 0x0b8 1179c7761a3SManu Gautam #define QPHY_V3_PCS_RXEQTRAINING_RUN_TIME 0x0bc 1189c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL1 0x0c4 1199c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNTRL2 0x0c8 1209c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_L 0x0cc 1219c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_CNT_VAL_H_TOL 0x0d0 1229c7761a3SManu Gautam #define QPHY_V3_PCS_FLL_MAN_CODE 0x0d4 123cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SYM_RESYNC_CTRL 0x134 124cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_MIN_HIBERN8_TIME 0x138 125cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL1 0x13c 126cc31cdbeSCan Guo #define QPHY_V3_PCS_RX_SIGDET_CTRL2 0x140 12773d7ec89SMarc Gonzalez #define QPHY_V3_PCS_LP_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1a8 12873d7ec89SMarc Gonzalez #define QPHY_V3_PCS_OSC_DTCT_ACTIONS 0x1ac 12973d7ec89SMarc Gonzalez #define QPHY_V3_PCS_SIGDET_CNTRL 0x1b0 130cc31cdbeSCan Guo #define QPHY_V3_PCS_TX_MID_TERM_CTRL1 0x1bc 131cc31cdbeSCan Guo #define QPHY_V3_PCS_MULTI_LANE_CTRL1 0x1c4 1329c7761a3SManu Gautam #define QPHY_V3_PCS_RX_SIGDET_LVL 0x1d8 13373d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_LSB 0x1dc 13473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_L1SS_WAKEUP_DLY_TIME_AUXCLK_MSB 0x1e0 135f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG1 0x20c 136f6721e5cSManu Gautam #define QPHY_V3_PCS_REFGEN_REQ_CONFIG2 0x210 1379c7761a3SManu Gautam 138ac0d2399SManu Gautam /* Only for QMP V3 PHY - PCS_MISC registers */ 139ac0d2399SManu Gautam #define QPHY_V3_PCS_MISC_CLAMP_ENABLE 0x0c 14073d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_CONFIG2 0x2c 14173d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_PCIE_INT_AUX_CLK_CONFIG1 0x44 14273d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG2 0x54 14373d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG4 0x5c 14473d7ec89SMarc Gonzalez #define QPHY_V3_PCS_MISC_OSC_DTCT_MODE2_CONFIG5 0x60 145ac0d2399SManu Gautam 1465c393917SDmitry Baryshkov /* QMP PHY - DP PHY registers */ 1475c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID0 0x000 1485c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID1 0x004 1495c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID2 0x008 1505c393917SDmitry Baryshkov #define QSERDES_DP_PHY_REVISION_ID3 0x00c 1515c393917SDmitry Baryshkov #define QSERDES_DP_PHY_CFG 0x010 1525c393917SDmitry Baryshkov #define QSERDES_DP_PHY_PD_CTL 0x018 15352e013d0SStephen Boyd # define DP_PHY_PD_CTL_PWRDN 0x001 15452e013d0SStephen Boyd # define DP_PHY_PD_CTL_PSR_PWRDN 0x002 15552e013d0SStephen Boyd # define DP_PHY_PD_CTL_AUX_PWRDN 0x004 15652e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_0_1_PWRDN 0x008 15752e013d0SStephen Boyd # define DP_PHY_PD_CTL_LANE_2_3_PWRDN 0x010 15852e013d0SStephen Boyd # define DP_PHY_PD_CTL_PLL_PWRDN 0x020 15952e013d0SStephen Boyd # define DP_PHY_PD_CTL_DP_CLAMP_EN 0x040 1605c393917SDmitry Baryshkov #define QSERDES_DP_PHY_MODE 0x01c 1615c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG0 0x020 1625c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG1 0x024 1635c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG2 0x028 1645c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG3 0x02c 1655c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG4 0x030 1665c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG5 0x034 1675c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG6 0x038 1685c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG7 0x03c 1695c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG8 0x040 1705c393917SDmitry Baryshkov #define QSERDES_DP_PHY_AUX_CFG9 0x044 17152e013d0SStephen Boyd 1725c393917SDmitry Baryshkov /* Only for QMP V3 PHY - DP PHY registers */ 17352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_MASK 0x048 17452e013d0SStephen Boyd # define PHY_AUX_STOP_ERR_MASK 0x01 17552e013d0SStephen Boyd # define PHY_AUX_DEC_ERR_MASK 0x02 17652e013d0SStephen Boyd # define PHY_AUX_SYNC_ERR_MASK 0x04 17752e013d0SStephen Boyd # define PHY_AUX_ALIGN_ERR_MASK 0x08 17852e013d0SStephen Boyd # define PHY_AUX_REQ_ERR_MASK 0x10 17952e013d0SStephen Boyd 18052e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_INTERRUPT_CLEAR 0x04c 18152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_AUX_BIST_CFG 0x050 18252e013d0SStephen Boyd 18352e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_VCO_DIV 0x064 18452e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX0_TX1_LANE_CTL 0x06c 18552e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_TX2_TX3_LANE_CTL 0x088 18652e013d0SStephen Boyd 18752e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_SPARE0 0x0ac 18852e013d0SStephen Boyd #define DP_PHY_SPARE0_MASK 0x0f 18952e013d0SStephen Boyd #define DP_PHY_SPARE0_ORIENTATION_INFO_SHIFT 0x04(0x0004) 19052e013d0SStephen Boyd 19152e013d0SStephen Boyd #define QSERDES_V3_DP_PHY_STATUS 0x0c0 19252e013d0SStephen Boyd 193a88c85eeSVinod Koul 194be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - TX registers */ 195be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_1 0x88 196be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_2 0x8c 197be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_LANE_MODE_3 0x90 198be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_VMODE_CTRL1 0xc4 199be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_TX_PI_QEC_CTRL 0xe0 200be0ddb5dSManivannan Sadhasivam 201aff188feSDmitry Baryshkov /* Only for QMP V4 PHY - DP PHY registers */ 202aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_CFG_1 0x014 203aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_MASK 0x054 204aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_CLEAR 0x058 205aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_VCO_DIV 0x070 206aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX0_TX1_LANE_CTL 0x078 207aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_TX2_TX3_LANE_CTL 0x09c 208aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_SPARE0 0x0c8 209aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_AUX_INTERRUPT_STATUS 0x0d8 210aff188feSDmitry Baryshkov #define QSERDES_V4_DP_PHY_STATUS 0x0dc 211aff188feSDmitry Baryshkov 212be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - RX registers */ 213be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_FO_GAIN_RATE2 0x008 214be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_UCDR_PI_CONTROLS 0x058 215be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_AUX_DATA_TCOARSE_TFINE 0x0ac 216be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_3 0x110 217be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE1 0x134 218be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_DAC_ENABLE2 0x138 219be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_VGA_CAL_CNTRL2 0x150 220be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x178 221be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B1 0x1c8 222be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B2 0x1cc 223be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B3 0x1d0 224be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE_0_1_B4 0x1d4 225be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B0 0x1d8 226be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B1 0x1dc 227be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B2 0x1e0 228be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B3 0x1e4 229be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE2_B4 0x1e8 230be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B0 0x1ec 231be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B1 0x1f0 232be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B2 0x1f4 233be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B3 0x1f8 234be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_RX_MODE_RATE3_B4 0x1fc 235be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_PHPRE_CTRL 0x200 236be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x20c 237be0ddb5dSManivannan Sadhasivam #define QSERDES_V4_20_RX_MARG_COARSE_CTRL2 0x23c 238be0ddb5dSManivannan Sadhasivam 2399a24b929SJack Pham /* Only for QMP V4 PHY - UFS PCS registers */ 24078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PHY_START 0x000 24178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_POWER_DOWN_CONTROL 0x004 24278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_SW_RESET 0x008 24378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 24478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 24578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_PLL_CNTL 0x02c 24678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 24778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 24878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_BIST_FIXED_PAT_CTRL 0x060 24978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 25078c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 25178c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 25278c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_LINECFG_DISABLE 0x148 25378c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 25478c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_RX_SIGDET_CTRL2 0x158 25578c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_PWM_GEAR_BAND 0x160 25678c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_HS_GEAR_BAND 0x168 25778c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_READY_STATUS 0x180 25878c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 25978c2aac2SWesley Cheng #define QPHY_V4_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 260a88c85eeSVinod Koul 261909a5c78SBjorn Andersson /* PCIE GEN3 COM registers */ 262909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_EN_CENTER 0x14 263909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER1 0x20 264909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_PER2 0x24 265909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1 0x28 266909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2 0x2c 267909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE1_MODE1 0x34 268909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SSC_STEP_SIZE2_MODE1 0x38 269909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BIAS_EN_CKBUFLR_EN 0x54 270909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_ENABLE1 0x58 271909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE0 0x6c 272909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE0 0x70 273909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP1_MODE1 0x78 274909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP2_MODE1 0x7c 275909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BGV_TRIM 0x98 276909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE0 0xb4 277909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CP_CTRL_MODE1 0xb8 278909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE0 0xc0 279909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_RCTRL_MODE1 0xc4 280909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE0 0xcc 281909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_PLL_CCTRL_MODE1 0xd0 282909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SYSCLK_EN_SEL 0xdc 283909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_RESTRIM_CTRL2 0xf0 284909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_LOCK_CMP_EN 0xf8 285909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE0 0x100 286909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DEC_START_MODE1 0x108 287909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE0 0x11c 288909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE0 0x120 289909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE0 0x124 290909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START1_MODE1 0x128 291909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START2_MODE1 0x12c 292909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_DIV_FRAC_START3_MODE1 0x130 293909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE0 0x150 294909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_INTEGLOOP_GAIN0_MODE1 0x158 295909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VCO_TUNE_MAP 0x178 296909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_BG_CTRL 0x1c8 297909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CLK_SELECT 0x1cc 298909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_HSCLK_SEL1 0x1d0 299909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV 0x1e0 300909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORE_CLK_EN 0x1e8 301909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_CONFIG 0x1f0 302909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_SVS_MODE_CLK_SEL 0x1fc 303909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CORECLK_DIV_MODE1 0x21c 304909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_CMN_MODE 0x224 305909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV1 0x228 306909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_COM_VREGCLK_DIV2 0x22c 307909a5c78SBjorn Andersson 308909a5c78SBjorn Andersson /* PCIE GEN3 QHP Lane registers */ 309909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL0 0xc 310909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL1 0x10 311909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_CTRL2 0x14 312909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DRVR_TAP_EN 0x18 313909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TX_BAND_MODE 0x60 314909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_LANE_MODE 0x64 315909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PARALLEL_RATE 0x7c 316909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE0 0xc0 317909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE1 0xc4 318909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CML_CTRL_MODE2 0xc8 319909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE1 0xd0 320909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PREAMP_CTRL_MODE2 0xd4 321909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE0 0xd8 322909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE1 0xdc 323909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_MIXER_CTRL_MODE2 0xe0 324909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_THRESH_DFE 0xfc 325909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CGA_THRESH_DFE 0x100 326909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXENGINE_EN0 0x108 327909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_TRAIN_TIME 0x114 328909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_CTLE_DFE_OVRLP_TIME 0x118 329909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_REFRESH_TIME 0x11c 330909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_ENABLE_TIME 0x120 331909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_GAIN 0x124 332909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DFE_GAIN 0x128 333909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_GAIN 0x130 334909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_OFFSET_GAIN 0x134 335909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PRE_GAIN 0x138 336909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_VGA_INITVAL 0x13c 337909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EQ_INTVAL 0x154 338909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_EDAC_INITVAL 0x160 339909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB0 0x168 340909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_INITB1 0x16c 341909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RCVRDONE_THRESH1 0x178 342909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RXEQ_CTRL 0x180 343909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE0 0x184 344909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE1 0x188 345909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_FO_GAIN_MODE2 0x18c 346909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE0 0x190 347909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE1 0x194 348909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_GAIN_MODE2 0x198 349909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_UCDR_SO_CONFIG 0x19c 350909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_BAND 0x1a4 351909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE0 0x1c0 352909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE1 0x1c4 353909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RCVR_PATH1_MODE2 0x1c8 354909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_ENABLES 0x230 355909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_CNTRL 0x234 356909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_SIGDET_DEGLITCH_CNTRL 0x238 357909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DCC_GAIN 0x2a4 358909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RSM_START 0x2a8 359909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_EN_SIGNAL 0x2ac 360909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_PSM_RX_EN_CAL 0x2b0 361909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_MISC_CNTRL0 0x2b8 362909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_TS0_TIMER 0x2c0 363909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_DLL_HIGHDATARATE 0x2c4 364909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_L0_RX_RESETCODE_OFFSET 0x2cc 365909a5c78SBjorn Andersson 366909a5c78SBjorn Andersson /* PCIE GEN3 PCS registers */ 367909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M3P5DB 0x2c 368909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M3P5DB 0x40 369909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_MAIN_V0_M6DB 0x54 370909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_TXMGN_POST_V0_M6DB 0x68 371909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG 0x15c 372909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_POWER_STATE_CONFIG5 0x16c 373909a5c78SBjorn Andersson #define PCIE_GEN3_QHP_PHY_PCS_TX_RX_CONFIG 0x174 374909a5c78SBjorn Andersson 3759a24b929SJack Pham /* Only for QMP V4 PHY - USB/PCIe PCS registers */ 3769a24b929SJack Pham #define QPHY_V4_PCS_SW_RESET 0x000 3779a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID0 0x004 3789a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID1 0x008 3799a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID2 0x00c 3809a24b929SJack Pham #define QPHY_V4_PCS_REVISION_ID3 0x010 3819a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS1 0x014 3829a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS2 0x018 3839a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS3 0x01c 3849a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS4 0x020 3859a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS5 0x024 3869a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS6 0x028 3879a24b929SJack Pham #define QPHY_V4_PCS_PCS_STATUS7 0x02c 3889a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_0_STATUS 0x030 3899a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_1_STATUS 0x034 3909a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_2_STATUS 0x038 3919a24b929SJack Pham #define QPHY_V4_PCS_DEBUG_BUS_3_STATUS 0x03c 3929a24b929SJack Pham #define QPHY_V4_PCS_POWER_DOWN_CONTROL 0x040 3939a24b929SJack Pham #define QPHY_V4_PCS_START_CONTROL 0x044 3949a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL1 0x048 3959a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL2 0x04c 3969a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL3 0x050 3979a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL4 0x054 3989a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL5 0x058 3999a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL6 0x05c 4009a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL7 0x060 4019a24b929SJack Pham #define QPHY_V4_PCS_INSIG_SW_CTRL8 0x064 4029a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL1 0x068 4039a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL2 0x06c 4049a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL3 0x070 4059a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL4 0x074 4069a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL5 0x078 4079a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL7 0x07c 4089a24b929SJack Pham #define QPHY_V4_PCS_INSIG_MX_CTRL8 0x080 4099a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_SW_CTRL1 0x084 4109a24b929SJack Pham #define QPHY_V4_PCS_OUTSIG_MX_CTRL1 0x088 4119a24b929SJack Pham #define QPHY_V4_PCS_CLAMP_ENABLE 0x08c 4129a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG1 0x090 4139a24b929SJack Pham #define QPHY_V4_PCS_POWER_STATE_CONFIG2 0x094 4149a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL1 0x098 4159a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNTRL2 0x09c 4169a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_L 0x0a0 4179a24b929SJack Pham #define QPHY_V4_PCS_FLL_CNT_VAL_H_TOL 0x0a4 4189a24b929SJack Pham #define QPHY_V4_PCS_FLL_MAN_CODE 0x0a8 4199a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL1 0x0ac 4209a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL2 0x0b0 4219a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL3 0x0b4 4229a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL4 0x0b8 4239a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL5 0x0bc 4249a24b929SJack Pham #define QPHY_V4_PCS_TEST_CONTROL6 0x0c0 4259a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG1 0x0c4 4269a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG2 0x0c8 4279a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG3 0x0cc 4289a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG4 0x0d0 4299a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG5 0x0d4 4309a24b929SJack Pham #define QPHY_V4_PCS_LOCK_DETECT_CONFIG6 0x0d8 4319a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG1 0x0dc 4329a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG2 0x0e0 4339a24b929SJack Pham #define QPHY_V4_PCS_REFGEN_REQ_CONFIG3 0x0e4 4349a24b929SJack Pham #define QPHY_V4_PCS_BIST_CTRL 0x0e8 4359a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY0 0x0ec 4369a24b929SJack Pham #define QPHY_V4_PCS_PRBS_POLY1 0x0f0 4379a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT0 0x0f4 4389a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT1 0x0f8 4399a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT2 0x0fc 4409a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT3 0x100 4419a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT4 0x104 4429a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT5 0x108 4439a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT6 0x10c 4449a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT7 0x110 4459a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT8 0x114 4469a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT9 0x118 4479a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT10 0x11c 4489a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT11 0x120 4499a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT12 0x124 4509a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT13 0x128 4519a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT14 0x12c 4529a24b929SJack Pham #define QPHY_V4_PCS_FIXED_PAT15 0x130 4539a24b929SJack Pham #define QPHY_V4_PCS_TXMGN_CONFIG 0x134 4549a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0 0x138 4559a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1 0x13c 4569a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2 0x140 4579a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3 0x144 4589a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4 0x148 4599a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V0_RS 0x14c 4609a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V1_RS 0x150 4619a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V2_RS 0x154 4629a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V3_RS 0x158 4639a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXMGN_V4_RS 0x15c 4649a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN 0x160 4659a24b929SJack Pham #define QPHY_V4_PCS_G3S2_TXMGN_MAIN_RS 0x164 4669a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M6DB 0x168 4679a24b929SJack Pham #define QPHY_V4_PCS_G12S1_TXDEEMPH_M3P5DB 0x16c 4689a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN 0x170 4699a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN 0x174 4709a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET 0x178 4719a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_GAIN_RS 0x17c 4729a24b929SJack Pham #define QPHY_V4_PCS_G3S2_POST_GAIN_RS 0x180 4739a24b929SJack Pham #define QPHY_V4_PCS_G3S2_PRE_POST_OFFSET_RS 0x184 4749a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_LVL 0x188 4759a24b929SJack Pham #define QPHY_V4_PCS_RX_SIGDET_DTCT_CNTRL 0x18c 4769a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L 0x190 4779a24b929SJack Pham #define QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H 0x194 4789a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL1 0x198 4799a24b929SJack Pham #define QPHY_V4_PCS_RATE_SLEW_CNTRL2 0x19c 4809a24b929SJack Pham #define QPHY_V4_PCS_PWRUP_RESET_DLY_TIME_AUXCLK 0x1a0 4819a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_L 0x1a4 4829a24b929SJack Pham #define QPHY_V4_PCS_P2U3_WAKEUP_DLY_TIME_AUXCLK_H 0x1a8 4839a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_RSYNC_TIME 0x1ac 4849a24b929SJack Pham #define QPHY_V4_PCS_CDR_RESET_TIME 0x1b0 4859a24b929SJack Pham #define QPHY_V4_PCS_TSYNC_DLY_TIME 0x1b4 4869a24b929SJack Pham #define QPHY_V4_PCS_ELECIDLE_DLY_SEL 0x1b8 4879a24b929SJack Pham #define QPHY_V4_PCS_CMN_ACK_OUT_SEL 0x1bc 4889a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG1 0x1c0 4899a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG2 0x1c4 4909a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG3 0x1c8 4919a24b929SJack Pham #define QPHY_V4_PCS_ALIGN_DETECT_CONFIG4 0x1cc 4929a24b929SJack Pham #define QPHY_V4_PCS_PCS_TX_RX_CONFIG 0x1d0 4939a24b929SJack Pham #define QPHY_V4_PCS_RX_IDLE_DTCT_CNTRL 0x1d4 4949a24b929SJack Pham #define QPHY_V4_PCS_RX_DCC_CAL_CONFIG 0x1d8 4959a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG1 0x1dc 4969a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG2 0x1e0 4979a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG3 0x1e4 4989a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG4 0x1e8 4999a24b929SJack Pham #define QPHY_V4_PCS_EQ_CONFIG5 0x1ec 500fc646236SDmitry Baryshkov 501fc646236SDmitry Baryshkov /* Only for QMP V4 PHY - USB3 PCS registers */ 502fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_POWER_STATE_CONFIG1 0x000 503fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 504fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 505fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 506fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 507fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 508fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 509fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_ECSTART 0x01c 510fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 511fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 512fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x028 513fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x02c 514fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x030 515fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x034 516fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x038 517fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x03c 518fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x040 519fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x044 520fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ARCVR_DTCT_CM_DLY 0x048 521fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x04c 522fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_ALFPS_DEGLITCH_VAL 0x050 523fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x054 524fc646236SDmitry Baryshkov #define QPHY_V4_PCS_USB3_TEST_CONTROL 0x058 5259a24b929SJack Pham 526be0ddb5dSManivannan Sadhasivam /* Only for QMP V4_20 PHY - USB/PCIe PCS registers */ 527be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_RX_SIGDET_LVL 0x188 528be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG2 0x1d8 529be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG4 0x1e0 530be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_EQ_CONFIG5 0x1e4 531be0ddb5dSManivannan Sadhasivam 5329a24b929SJack Pham /* Only for QMP V4 PHY - PCS_MISC registers */ 5339a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_CTRL 0x00 5349a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_PWRDN_CTRL 0x04 5359a24b929SJack Pham #define QPHY_V4_PCS_MISC_PCS_MISC_CONFIG1 0x08 5369a24b929SJack Pham #define QPHY_V4_PCS_MISC_CLAMP_ENABLE 0x0c 5379a24b929SJack Pham #define QPHY_V4_PCS_MISC_TYPEC_STATUS 0x10 5389a24b929SJack Pham #define QPHY_V4_PCS_MISC_PLACEHOLDER_STATUS 0x14 5399a24b929SJack Pham 5406edf7700SManivannan Sadhasivam /* Only for QMP V4 PHY - PCS_PCIE registers (same as PCS_MISC?) */ 5416edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG2 0x0c 5426edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_POWER_STATE_CONFIG4 0x14 5436edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x1c 5446edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P1_WAKEUP_DLY_TIME_AUXCLK_L 0x40 5456edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_L1P2_WAKEUP_DLY_TIME_AUXCLK_L 0x48 5466edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x50 5476edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_OSC_DTCT_ACTIONS 0x90 54860f23414SDmitry Baryshkov #define QPHY_V4_PCS_PCIE_EQ_CONFIG1 0xa0 5496edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_EQ_CONFIG2 0xa4 5506edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P6_P7_PRE 0xb4 5516edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_PRE 0xbc 5526edf7700SManivannan Sadhasivam #define QPHY_V4_PCS_PCIE_PRESET_P10_POST 0xe0 5536edf7700SManivannan Sadhasivam 554be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_EQ_CONFIG1 0x0a0 555be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G3_RXEQEVAL_TIME 0x0f0 556be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_RXEQEVAL_TIME 0x0f4 557be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG2 0x0fc 558be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 559be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_SW_CTRL2 0x824 560be0ddb5dSManivannan Sadhasivam #define QPHY_V4_20_PCS_LANE1_INSIG_MX_CTRL2 0x828 561be0ddb5dSManivannan Sadhasivam 5622c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - TX registers */ 5632c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 5642c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 5652c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 5662c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 5672c91bf6bSDmitry Baryshkov 5682c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - RX registers */ 5692c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 5702c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c 5712c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 5722c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c 5732c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 5742c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c 5752c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_3 0x090 5762c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 5772c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 5782c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 5792c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc 5802c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_GM_CAL 0x0ec 5812c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 5822c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 5832c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 5842c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c 5852c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 5862c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 5872c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c 5882c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 5892c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 5902c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 5912c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c 5922c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 5932c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 5942c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 5952c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c 5962c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 5972c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 5982c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 5992c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac 6002c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 6012c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 6022c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 6032c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 6042c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 6052c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc 6062c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 6072c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 6082c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 6092c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 6102c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 6112c91bf6bSDmitry Baryshkov #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 6122c91bf6bSDmitry Baryshkov 613107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - USB/PCIe PCS registers */ 614107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_REFGEN_REQ_CONFIG1 0x0dc 6152c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_G3S2_PRE_GAIN 0x170 616107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RX_SIGDET_LVL 0x188 617107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_RATE_SLEW_CNTRL1 0x198 6182c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG2 0x1e0 6192c91bf6bSDmitry Baryshkov #define QPHY_V5_PCS_EQ_CONFIG3 0x1e4 620107ba9bfSDmitry Baryshkov 621107ba9bfSDmitry Baryshkov /* Only for QMP V5 PHY - PCS_PCIE registers */ 622107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x20 623107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_INT_AUX_CLK_CONFIG1 0x54 624107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_OSC_DTCT_ACTIONS 0x94 625107ba9bfSDmitry Baryshkov #define QPHY_V5_PCS_PCIE_EQ_CONFIG2 0xa8 626107ba9bfSDmitry Baryshkov 6272c91bf6bSDmitry Baryshkov /* Only for QMP V5_20 PHY - PCIe PCS registers */ 6282c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_ENDPOINT_REFCLK_DRIVE 0x01c 6292c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_OSC_DTCT_ACTIONS 0x090 6302c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_EQ_CONFIG1 0x0a0 6312c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_EQ_CONFIG5 0x108 6322c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_G4_PRE_GAIN 0x15c 6332c91bf6bSDmitry Baryshkov #define QPHY_V5_20_PCS_PCIE_RX_MARGINING_CONFIG3 0x184 6342c91bf6bSDmitry Baryshkov 635920abc10SVinod Koul /* Only for QMP V5 PHY - UFS PCS registers */ 636920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_MSB 0x00c 637920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TIMER_20US_CORECLK_STEPS_LSB 0x010 638920abc10SVinod Koul #define QPHY_V5_PCS_UFS_PLL_CNTL 0x02c 639920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_LARGE_AMP_DRV_LVL 0x030 640920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_SMALL_AMP_DRV_LVL 0x038 641920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HSGEAR_CAPABILITY 0x074 642920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_HSGEAR_CAPABILITY 0x0b4 643920abc10SVinod Koul #define QPHY_V5_PCS_UFS_DEBUG_BUS_CLKSEL 0x124 644920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_MIN_HIBERN8_TIME 0x150 645920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL1 0x154 646920abc10SVinod Koul #define QPHY_V5_PCS_UFS_RX_SIGDET_CTRL2 0x158 647920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_PWM_GEAR_BAND 0x160 648920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_HS_GEAR_BAND 0x168 649920abc10SVinod Koul #define QPHY_V5_PCS_UFS_TX_MID_TERM_CTRL1 0x1d8 650920abc10SVinod Koul #define QPHY_V5_PCS_UFS_MULTI_LANE_CTRL1 0x1e0 651920abc10SVinod Koul 65210c744d4SJack Pham /* Only for QMP V5 PHY - USB3 have different offsets than V4 */ 653fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1 0x000 654fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_STATUS 0x004 655fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL 0x008 656fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL2 0x00c 657fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_SOURCE_STATUS 0x010 658fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR 0x014 659fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL 0x018 660fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_ECSTART 0x01c 661fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_PER_TIMER_VAL 0x020 662fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_TX_END_CNT_U3_START 0x024 663fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_LFPS_CONFIG1 0x028 664fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_LOCK_TIME 0x02c 665fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME 0x030 666fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_CTLE_TIME 0x034 667fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_WAIT_TIME_S2 0x038 668fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2 0x03c 669fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L 0x040 670fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H 0x044 671fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_EN_PERIOD 0x048 672fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ARCVR_DTCT_CM_DLY 0x04c 673fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TXONESZEROS_RUN_LENGTH 0x050 674fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_ALFPS_DEGLITCH_VAL 0x054 675fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_SIGDET_STARTUP_TIMER_VAL 0x058 676fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_TEST_CONTROL 0x05c 677fc646236SDmitry Baryshkov #define QPHY_V5_PCS_USB3_RXTERMINATION_DLY_SEL 0x060 67810c744d4SJack Pham 679e2248617SManu Gautam #endif 680