1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include "phy-qcom-qmp.h" 24 #include "phy-qcom-qmp-pcs-misc-v3.h" 25 #include "phy-qcom-qmp-pcs-usb-v4.h" 26 #include "phy-qcom-qmp-pcs-usb-v5.h" 27 28 /* QPHY_SW_RESET bit */ 29 #define SW_RESET BIT(0) 30 /* QPHY_POWER_DOWN_CONTROL */ 31 #define SW_PWRDN BIT(0) 32 /* QPHY_START_CONTROL bits */ 33 #define SERDES_START BIT(0) 34 #define PCS_START BIT(1) 35 /* QPHY_PCS_STATUS bit */ 36 #define PHYSTATUS BIT(6) 37 38 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 39 /* DP PHY soft reset */ 40 #define SW_DPPHY_RESET BIT(0) 41 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 42 #define SW_DPPHY_RESET_MUX BIT(1) 43 /* USB3 PHY soft reset */ 44 #define SW_USB3PHY_RESET BIT(2) 45 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 46 #define SW_USB3PHY_RESET_MUX BIT(3) 47 48 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 49 #define USB3_MODE BIT(0) /* enables USB3 mode */ 50 #define DP_MODE BIT(1) /* enables DP mode */ 51 52 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 53 #define ARCVR_DTCT_EN BIT(0) 54 #define ALFPS_DTCT_EN BIT(1) 55 #define ARCVR_DTCT_EVENT_SEL BIT(4) 56 57 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 58 #define IRQ_CLEAR BIT(0) 59 60 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 61 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 62 63 #define PHY_INIT_COMPLETE_TIMEOUT 10000 64 65 struct qmp_phy_init_tbl { 66 unsigned int offset; 67 unsigned int val; 68 /* 69 * mask of lanes for which this register is written 70 * for cases when second lane needs different values 71 */ 72 u8 lane_mask; 73 }; 74 75 #define QMP_PHY_INIT_CFG(o, v) \ 76 { \ 77 .offset = o, \ 78 .val = v, \ 79 .lane_mask = 0xff, \ 80 } 81 82 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 83 { \ 84 .offset = o, \ 85 .val = v, \ 86 .lane_mask = l, \ 87 } 88 89 /* set of registers with offsets different per-PHY */ 90 enum qphy_reg_layout { 91 /* PCS registers */ 92 QPHY_SW_RESET, 93 QPHY_START_CTRL, 94 QPHY_PCS_STATUS, 95 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 96 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 97 QPHY_PCS_POWER_DOWN_CONTROL, 98 /* Keep last to ensure regs_layout arrays are properly initialized */ 99 QPHY_LAYOUT_SIZE 100 }; 101 102 static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 103 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 104 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 105 [QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS, 106 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL, 107 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR, 108 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, 109 }; 110 111 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 112 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 113 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 114 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 115 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 116 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 117 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 118 }; 119 120 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 121 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 122 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 123 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 124 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 125 126 /* In PCS_USB */ 127 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 128 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 129 }; 130 131 static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 132 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 133 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 134 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 135 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 136 137 /* In PCS_USB */ 138 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 139 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 140 }; 141 142 static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = { 143 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), 144 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 145 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 146 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 147 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 148 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 149 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 150 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 151 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 152 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 153 /* PLL and Loop filter settings */ 154 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68), 155 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab), 156 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa), 157 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02), 158 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09), 159 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 160 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 161 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0), 162 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa), 163 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29), 164 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 165 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 166 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 167 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 168 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 169 /* SSC settings */ 170 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 171 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d), 172 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 173 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 174 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 175 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a), 176 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05), 177 }; 178 179 static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = { 180 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 181 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 182 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 183 }; 184 185 static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = { 186 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), 187 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 188 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c), 189 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 190 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), 191 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 192 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 193 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 194 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 195 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c), 196 }; 197 198 static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = { 199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 207 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 210 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 211 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 212 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 213 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 214 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 215 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 216 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 217 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 218 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 219 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 220 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 221 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 222 }; 223 224 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { 225 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), 226 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 227 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 228 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 229 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 230 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 231 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 232 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 233 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 234 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 235 /* PLL and Loop filter settings */ 236 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 237 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 238 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 239 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 240 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 241 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 242 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 243 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 244 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 245 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 246 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 247 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 248 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 249 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 250 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 251 /* SSC settings */ 252 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 253 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 254 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 255 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 256 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 257 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 258 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 259 }; 260 261 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { 262 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), 263 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 264 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 265 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), 266 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 267 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 268 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 269 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 270 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), 271 }; 272 273 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { 274 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 275 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 276 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 277 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 278 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 279 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 280 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 281 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 282 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 283 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 294 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 295 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 297 }; 298 299 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { 300 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 301 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 302 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 303 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 304 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 305 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 306 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 307 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 308 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), 309 /* PLL and Loop filter settings */ 310 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 311 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 312 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 313 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 314 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 315 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 316 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 317 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 318 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 319 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 320 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 321 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 322 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 323 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 324 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 325 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 326 /* SSC settings */ 327 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 328 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 329 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 330 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 331 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 332 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 333 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 334 }; 335 336 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { 337 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 338 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 339 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 340 }; 341 342 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { 343 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 344 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 345 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 346 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 347 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), 348 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 349 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 350 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 351 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), 352 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 353 }; 354 355 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { 356 /* FLL settings */ 357 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03), 358 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02), 359 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09), 360 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42), 361 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85), 362 363 /* Lock Det settings */ 364 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1), 365 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f), 366 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47), 367 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08), 368 }; 369 370 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { 371 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 372 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 373 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 374 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 375 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 376 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 377 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 378 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 379 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 380 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 381 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 382 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 383 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 384 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 385 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 386 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 387 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 388 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 389 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 390 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 391 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 392 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 393 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 394 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 395 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 396 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 397 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 400 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 407 }; 408 409 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { 410 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 411 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 412 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 413 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 414 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 415 }; 416 417 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { 418 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), 419 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), 420 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 421 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 422 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 423 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 424 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 425 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 426 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 427 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 428 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 429 }; 430 431 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { 432 /* FLL settings */ 433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 434 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 435 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 436 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 437 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 438 439 /* Lock Det settings */ 440 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 441 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 442 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 443 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 444 445 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 446 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 447 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 448 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), 449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), 450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), 451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), 452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 454 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 459 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 464 465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 474 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 475 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 476 477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 479 }; 480 481 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { 482 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 483 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 484 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 485 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), 486 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 487 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 488 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 489 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 490 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 491 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 492 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 493 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 494 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 495 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 496 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 497 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 498 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 499 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 500 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 501 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 502 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 503 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 504 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 505 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 506 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), 512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 520 }; 521 522 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { 523 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 524 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 525 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 526 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 527 }; 528 529 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { 530 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 531 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 532 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 533 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 534 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), 535 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 536 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), 537 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 538 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 539 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 540 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 541 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 542 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 543 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 544 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 545 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), 546 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 547 }; 548 549 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { 550 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 551 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 552 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 553 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 554 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 555 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 556 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 557 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 558 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 559 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 560 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 561 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 562 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 563 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 564 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 565 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 566 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 567 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 568 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 569 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 570 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 571 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 572 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), 573 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 574 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 575 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 576 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 577 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), 585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 588 }; 589 590 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { 591 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 592 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 593 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 594 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 595 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 596 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 597 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 598 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 599 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 600 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 601 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 602 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 603 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 604 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 605 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 606 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 607 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 608 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 609 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 610 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 611 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 612 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 613 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 614 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 615 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 616 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 617 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 618 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 619 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 620 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 621 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 622 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 623 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 624 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 625 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 626 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 627 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 630 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 631 }; 632 633 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { 634 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 635 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), 636 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 637 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), 638 }; 639 640 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { 641 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 642 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 643 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), 644 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), 645 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), 646 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 647 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 648 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 649 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 650 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 651 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 652 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 653 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 654 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 655 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 656 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 657 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 658 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 659 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 660 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), 661 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 662 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 663 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), 675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 677 }; 678 679 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { 680 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 681 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 682 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 683 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 684 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 685 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 686 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 687 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), 688 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 689 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 690 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 691 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 692 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 693 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 694 }; 695 696 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = { 697 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 698 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 699 }; 700 701 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { 702 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 703 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 704 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), 705 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 706 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 707 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 708 }; 709 710 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { 711 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 712 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), 713 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 714 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 715 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 716 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 717 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 718 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 719 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 720 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 721 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 722 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 723 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 724 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 725 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 726 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 727 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 728 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 729 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 730 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), 731 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 732 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 733 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 734 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 735 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 736 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 737 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 738 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 739 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 740 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 741 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 742 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 743 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 744 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 745 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 746 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 747 }; 748 749 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { 750 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 751 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 752 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 753 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 754 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 755 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 756 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 757 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 758 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 759 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 760 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 761 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 762 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 763 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 764 }; 765 766 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = { 767 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 768 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 769 }; 770 771 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { 772 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 773 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 774 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), 775 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 776 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), 777 }; 778 779 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { 780 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), 781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), 792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), 794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), 795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), 800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 812 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 813 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 814 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 815 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 816 }; 817 818 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { 819 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 820 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 821 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 822 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 823 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 824 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 825 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), 826 }; 827 828 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { 829 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 830 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 831 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 832 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 833 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 834 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 835 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 836 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 837 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 838 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 839 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 840 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 841 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 842 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 843 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 844 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 845 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 846 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 847 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 848 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 849 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 850 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 851 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 852 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 853 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 854 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 855 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 856 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 857 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 858 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 859 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 860 }; 861 862 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { 863 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 864 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 865 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 866 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 867 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 868 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 869 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 870 }; 871 872 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { 873 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), 874 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 875 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 876 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 877 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 878 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 879 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 880 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 881 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 882 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 883 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 884 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 885 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 886 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 887 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 888 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 889 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 890 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 891 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 892 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 893 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 894 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 895 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 896 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 897 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 898 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 899 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 900 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 901 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 902 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 903 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 904 }; 905 906 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { 907 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 908 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 909 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 910 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 911 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 912 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 913 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 914 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 915 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 916 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 917 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 918 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 919 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 920 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 921 }; 922 923 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = { 924 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 925 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 926 }; 927 928 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { 929 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 930 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 931 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 932 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 933 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), 934 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), 935 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 936 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 937 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 938 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 939 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 940 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 941 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 942 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 943 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 944 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 945 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 946 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 947 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 948 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 949 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 950 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 951 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), 952 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 953 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 954 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 955 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 956 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 957 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 958 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 959 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 960 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 961 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 962 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 963 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 964 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 965 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), 966 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), 967 }; 968 969 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { 970 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 971 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 972 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 973 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 974 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), 975 }; 976 977 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { 978 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 979 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 980 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 981 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 982 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 983 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 984 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 985 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 986 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 987 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 988 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 989 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 990 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), 991 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 992 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 993 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 994 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), 995 }; 996 997 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { 998 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 999 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 1000 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 1001 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 1002 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 1003 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 1004 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 1005 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 1006 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 1007 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 1008 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 1009 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 1010 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 1011 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 1012 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 1013 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 1014 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1015 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1016 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 1017 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 1018 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 1019 }; 1020 1021 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = { 1022 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1023 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1024 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1025 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1026 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab), 1027 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea), 1028 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02), 1029 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1030 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1031 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1032 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1033 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1034 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1035 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1036 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1037 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1038 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1039 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02), 1040 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24), 1041 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1042 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82), 1043 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1044 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea), 1045 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1046 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1047 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1048 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1049 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1050 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1051 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 1052 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 1053 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1054 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1055 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1056 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde), 1057 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07), 1058 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1059 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1060 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1061 }; 1062 1063 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = { 1064 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1065 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1066 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1067 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1068 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1069 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 1070 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1071 }; 1072 1073 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = { 1074 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), 1075 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1076 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1077 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1078 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1079 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1080 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1081 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1082 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1083 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1084 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1085 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1086 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1087 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1088 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1089 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1090 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1091 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1092 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a), 1093 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1105 }; 1106 1107 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = { 1108 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1109 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1110 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1111 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1112 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1113 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1114 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1115 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1116 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1117 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1118 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a), 1119 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1120 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1121 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1122 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1123 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1124 }; 1125 1126 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = { 1127 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1128 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89), 1129 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1130 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1131 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1132 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1133 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1134 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1135 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1136 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1137 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f), 1138 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a), 1139 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1140 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1141 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1142 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1143 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1144 }; 1145 1146 struct qmp_usb_offsets { 1147 u16 serdes; 1148 u16 pcs; 1149 u16 pcs_misc; 1150 u16 pcs_usb; 1151 u16 tx; 1152 u16 rx; 1153 /* for PHYs with >= 2 lanes */ 1154 u16 tx2; 1155 u16 rx2; 1156 }; 1157 1158 /* struct qmp_phy_cfg - per-PHY initialization config */ 1159 struct qmp_phy_cfg { 1160 int lanes; 1161 1162 const struct qmp_usb_offsets *offsets; 1163 1164 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1165 const struct qmp_phy_init_tbl *serdes_tbl; 1166 int serdes_tbl_num; 1167 const struct qmp_phy_init_tbl *tx_tbl; 1168 int tx_tbl_num; 1169 const struct qmp_phy_init_tbl *rx_tbl; 1170 int rx_tbl_num; 1171 const struct qmp_phy_init_tbl *pcs_tbl; 1172 int pcs_tbl_num; 1173 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1174 int pcs_usb_tbl_num; 1175 1176 /* clock ids to be requested */ 1177 const char * const *clk_list; 1178 int num_clks; 1179 /* resets to be requested */ 1180 const char * const *reset_list; 1181 int num_resets; 1182 /* regulators to be requested */ 1183 const char * const *vreg_list; 1184 int num_vregs; 1185 1186 /* array of registers with different offsets */ 1187 const unsigned int *regs; 1188 1189 /* true, if PHY needs delay after POWER_DOWN */ 1190 bool has_pwrdn_delay; 1191 1192 /* Offset from PCS to PCS_USB region */ 1193 unsigned int pcs_usb_offset; 1194 }; 1195 1196 struct qmp_usb { 1197 struct device *dev; 1198 1199 const struct qmp_phy_cfg *cfg; 1200 1201 void __iomem *serdes; 1202 void __iomem *pcs; 1203 void __iomem *pcs_misc; 1204 void __iomem *pcs_usb; 1205 void __iomem *tx; 1206 void __iomem *rx; 1207 void __iomem *tx2; 1208 void __iomem *rx2; 1209 1210 struct clk *pipe_clk; 1211 struct clk_bulk_data *clks; 1212 struct reset_control_bulk_data *resets; 1213 struct regulator_bulk_data *vregs; 1214 1215 enum phy_mode mode; 1216 1217 struct phy *phy; 1218 1219 struct clk_fixed_rate pipe_clk_fixed; 1220 }; 1221 1222 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1223 { 1224 u32 reg; 1225 1226 reg = readl(base + offset); 1227 reg |= val; 1228 writel(reg, base + offset); 1229 1230 /* ensure that above write is through */ 1231 readl(base + offset); 1232 } 1233 1234 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1235 { 1236 u32 reg; 1237 1238 reg = readl(base + offset); 1239 reg &= ~val; 1240 writel(reg, base + offset); 1241 1242 /* ensure that above write is through */ 1243 readl(base + offset); 1244 } 1245 1246 /* list of clocks required by phy */ 1247 static const char * const msm8996_phy_clk_l[] = { 1248 "aux", "cfg_ahb", "ref", 1249 }; 1250 1251 static const char * const qmp_v3_phy_clk_l[] = { 1252 "aux", "cfg_ahb", "ref", "com_aux", 1253 }; 1254 1255 static const char * const qmp_v4_phy_clk_l[] = { 1256 "aux", "ref", "com_aux", 1257 }; 1258 1259 static const char * const qmp_v4_ref_phy_clk_l[] = { 1260 "aux", "ref_clk_src", "ref", "com_aux", 1261 }; 1262 1263 /* usb3 phy on sdx55 doesn't have com_aux clock */ 1264 static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { 1265 "aux", "cfg_ahb", "ref" 1266 }; 1267 1268 static const char * const qcm2290_usb3phy_clk_l[] = { 1269 "cfg_ahb", "ref", "com_aux", 1270 }; 1271 1272 /* list of resets */ 1273 static const char * const msm8996_usb3phy_reset_l[] = { 1274 "phy", "common", 1275 }; 1276 1277 static const char * const qcm2290_usb3phy_reset_l[] = { 1278 "phy_phy", "phy", 1279 }; 1280 1281 /* list of regulators */ 1282 static const char * const qmp_phy_vreg_l[] = { 1283 "vdda-phy", "vdda-pll", 1284 }; 1285 1286 static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = { 1287 .serdes = 0, 1288 .pcs = 0x800, 1289 .pcs_usb = 0x800, 1290 .tx = 0x200, 1291 .rx = 0x400, 1292 }; 1293 1294 static const struct qmp_usb_offsets qmp_usb_offsets_v3 = { 1295 .serdes = 0, 1296 .pcs = 0xc00, 1297 .pcs_misc = 0xa00, 1298 .tx = 0x200, 1299 .rx = 0x400, 1300 .tx2 = 0x600, 1301 .rx2 = 0x800, 1302 }; 1303 1304 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { 1305 .serdes = 0, 1306 .pcs = 0x0200, 1307 .pcs_usb = 0x1200, 1308 .tx = 0x0e00, 1309 .rx = 0x1000, 1310 }; 1311 1312 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { 1313 .lanes = 1, 1314 1315 .serdes_tbl = ipq8074_usb3_serdes_tbl, 1316 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), 1317 .tx_tbl = msm8996_usb3_tx_tbl, 1318 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1319 .rx_tbl = ipq8074_usb3_rx_tbl, 1320 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), 1321 .pcs_tbl = ipq8074_usb3_pcs_tbl, 1322 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), 1323 .clk_list = msm8996_phy_clk_l, 1324 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1325 .reset_list = msm8996_usb3phy_reset_l, 1326 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1327 .vreg_list = qmp_phy_vreg_l, 1328 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1329 .regs = qmp_v3_usb3phy_regs_layout, 1330 }; 1331 1332 static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = { 1333 .lanes = 1, 1334 1335 .offsets = &qmp_usb_offsets_ipq9574, 1336 1337 .serdes_tbl = ipq9574_usb3_serdes_tbl, 1338 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl), 1339 .tx_tbl = ipq9574_usb3_tx_tbl, 1340 .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl), 1341 .rx_tbl = ipq9574_usb3_rx_tbl, 1342 .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl), 1343 .pcs_tbl = ipq9574_usb3_pcs_tbl, 1344 .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl), 1345 .clk_list = msm8996_phy_clk_l, 1346 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1347 .reset_list = qcm2290_usb3phy_reset_l, 1348 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 1349 .vreg_list = qmp_phy_vreg_l, 1350 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1351 .regs = qmp_v3_usb3phy_regs_layout, 1352 }; 1353 1354 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { 1355 .lanes = 1, 1356 1357 .serdes_tbl = msm8996_usb3_serdes_tbl, 1358 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), 1359 .tx_tbl = msm8996_usb3_tx_tbl, 1360 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1361 .rx_tbl = msm8996_usb3_rx_tbl, 1362 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), 1363 .pcs_tbl = msm8996_usb3_pcs_tbl, 1364 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), 1365 .clk_list = msm8996_phy_clk_l, 1366 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1367 .reset_list = msm8996_usb3phy_reset_l, 1368 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1369 .vreg_list = qmp_phy_vreg_l, 1370 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1371 .regs = qmp_v2_usb3phy_regs_layout, 1372 }; 1373 1374 static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = { 1375 .lanes = 1, 1376 1377 .offsets = &qmp_usb_offsets_v5, 1378 1379 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, 1380 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), 1381 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl, 1382 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl), 1383 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl, 1384 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl), 1385 .pcs_tbl = sa8775p_usb3_uniphy_pcs_tbl, 1386 .pcs_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl), 1387 .clk_list = qmp_v4_phy_clk_l, 1388 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1389 .reset_list = qcm2290_usb3phy_reset_l, 1390 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 1391 .vreg_list = qmp_phy_vreg_l, 1392 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1393 .regs = qmp_v5_usb3phy_regs_layout, 1394 }; 1395 1396 static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { 1397 .lanes = 1, 1398 1399 .offsets = &qmp_usb_offsets_v5, 1400 1401 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, 1402 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), 1403 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl, 1404 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl), 1405 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl, 1406 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl), 1407 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl, 1408 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl), 1409 .clk_list = qmp_v4_phy_clk_l, 1410 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1411 .reset_list = qcm2290_usb3phy_reset_l, 1412 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 1413 .vreg_list = qmp_phy_vreg_l, 1414 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1415 .regs = qmp_v5_usb3phy_regs_layout, 1416 }; 1417 1418 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { 1419 .lanes = 1, 1420 1421 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, 1422 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), 1423 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, 1424 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), 1425 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, 1426 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), 1427 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, 1428 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), 1429 .clk_list = qmp_v3_phy_clk_l, 1430 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1431 .reset_list = msm8996_usb3phy_reset_l, 1432 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1433 .vreg_list = qmp_phy_vreg_l, 1434 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1435 .regs = qmp_v3_usb3phy_regs_layout, 1436 1437 .has_pwrdn_delay = true, 1438 }; 1439 1440 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { 1441 .lanes = 2, 1442 1443 .serdes_tbl = msm8998_usb3_serdes_tbl, 1444 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), 1445 .tx_tbl = msm8998_usb3_tx_tbl, 1446 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), 1447 .rx_tbl = msm8998_usb3_rx_tbl, 1448 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), 1449 .pcs_tbl = msm8998_usb3_pcs_tbl, 1450 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), 1451 .clk_list = msm8996_phy_clk_l, 1452 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1453 .reset_list = msm8996_usb3phy_reset_l, 1454 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1455 .vreg_list = qmp_phy_vreg_l, 1456 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1457 .regs = qmp_v3_usb3phy_regs_layout, 1458 }; 1459 1460 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { 1461 .lanes = 1, 1462 1463 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1464 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1465 .tx_tbl = sm8150_usb3_uniphy_tx_tbl, 1466 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), 1467 .rx_tbl = sm8150_usb3_uniphy_rx_tbl, 1468 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), 1469 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, 1470 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), 1471 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl, 1472 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl), 1473 .clk_list = qmp_v4_ref_phy_clk_l, 1474 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1475 .reset_list = msm8996_usb3phy_reset_l, 1476 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1477 .vreg_list = qmp_phy_vreg_l, 1478 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1479 .regs = qmp_v4_usb3phy_regs_layout, 1480 .pcs_usb_offset = 0x600, 1481 1482 .has_pwrdn_delay = true, 1483 }; 1484 1485 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { 1486 .lanes = 1, 1487 1488 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1489 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1490 .tx_tbl = sm8250_usb3_uniphy_tx_tbl, 1491 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), 1492 .rx_tbl = sm8250_usb3_uniphy_rx_tbl, 1493 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), 1494 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1495 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1496 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, 1497 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), 1498 .clk_list = qmp_v4_ref_phy_clk_l, 1499 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1500 .reset_list = msm8996_usb3phy_reset_l, 1501 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1502 .vreg_list = qmp_phy_vreg_l, 1503 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1504 .regs = qmp_v4_usb3phy_regs_layout, 1505 .pcs_usb_offset = 0x600, 1506 1507 .has_pwrdn_delay = true, 1508 }; 1509 1510 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { 1511 .lanes = 1, 1512 1513 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1514 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1515 .tx_tbl = sdx55_usb3_uniphy_tx_tbl, 1516 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), 1517 .rx_tbl = sdx55_usb3_uniphy_rx_tbl, 1518 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), 1519 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1520 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1521 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, 1522 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), 1523 .clk_list = qmp_v4_sdx55_usbphy_clk_l, 1524 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), 1525 .reset_list = msm8996_usb3phy_reset_l, 1526 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1527 .vreg_list = qmp_phy_vreg_l, 1528 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1529 .regs = qmp_v4_usb3phy_regs_layout, 1530 .pcs_usb_offset = 0x600, 1531 1532 .has_pwrdn_delay = true, 1533 }; 1534 1535 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { 1536 .lanes = 1, 1537 1538 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1539 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1540 .tx_tbl = sdx65_usb3_uniphy_tx_tbl, 1541 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), 1542 .rx_tbl = sdx65_usb3_uniphy_rx_tbl, 1543 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), 1544 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 1545 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 1546 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, 1547 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), 1548 .clk_list = qmp_v4_sdx55_usbphy_clk_l, 1549 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), 1550 .reset_list = msm8996_usb3phy_reset_l, 1551 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1552 .vreg_list = qmp_phy_vreg_l, 1553 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1554 .regs = qmp_v5_usb3phy_regs_layout, 1555 .pcs_usb_offset = 0x1000, 1556 1557 .has_pwrdn_delay = true, 1558 }; 1559 1560 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { 1561 .lanes = 1, 1562 1563 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1564 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1565 .tx_tbl = sm8350_usb3_uniphy_tx_tbl, 1566 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), 1567 .rx_tbl = sm8350_usb3_uniphy_rx_tbl, 1568 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), 1569 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 1570 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 1571 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, 1572 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), 1573 .clk_list = qmp_v4_ref_phy_clk_l, 1574 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1575 .reset_list = msm8996_usb3phy_reset_l, 1576 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1577 .vreg_list = qmp_phy_vreg_l, 1578 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1579 .regs = qmp_v5_usb3phy_regs_layout, 1580 .pcs_usb_offset = 0x1000, 1581 1582 .has_pwrdn_delay = true, 1583 }; 1584 1585 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { 1586 .lanes = 2, 1587 1588 .offsets = &qmp_usb_offsets_v3, 1589 1590 .serdes_tbl = qcm2290_usb3_serdes_tbl, 1591 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 1592 .tx_tbl = qcm2290_usb3_tx_tbl, 1593 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 1594 .rx_tbl = qcm2290_usb3_rx_tbl, 1595 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 1596 .pcs_tbl = qcm2290_usb3_pcs_tbl, 1597 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 1598 .clk_list = qcm2290_usb3phy_clk_l, 1599 .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), 1600 .reset_list = qcm2290_usb3phy_reset_l, 1601 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 1602 .vreg_list = qmp_phy_vreg_l, 1603 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1604 .regs = qmp_v3_usb3phy_regs_layout, 1605 }; 1606 1607 static void qmp_usb_configure_lane(void __iomem *base, 1608 const struct qmp_phy_init_tbl tbl[], 1609 int num, 1610 u8 lane_mask) 1611 { 1612 int i; 1613 const struct qmp_phy_init_tbl *t = tbl; 1614 1615 if (!t) 1616 return; 1617 1618 for (i = 0; i < num; i++, t++) { 1619 if (!(t->lane_mask & lane_mask)) 1620 continue; 1621 1622 writel(t->val, base + t->offset); 1623 } 1624 } 1625 1626 static void qmp_usb_configure(void __iomem *base, 1627 const struct qmp_phy_init_tbl tbl[], 1628 int num) 1629 { 1630 qmp_usb_configure_lane(base, tbl, num, 0xff); 1631 } 1632 1633 static int qmp_usb_serdes_init(struct qmp_usb *qmp) 1634 { 1635 const struct qmp_phy_cfg *cfg = qmp->cfg; 1636 void __iomem *serdes = qmp->serdes; 1637 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1638 int serdes_tbl_num = cfg->serdes_tbl_num; 1639 1640 qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num); 1641 1642 return 0; 1643 } 1644 1645 static int qmp_usb_init(struct phy *phy) 1646 { 1647 struct qmp_usb *qmp = phy_get_drvdata(phy); 1648 const struct qmp_phy_cfg *cfg = qmp->cfg; 1649 void __iomem *pcs = qmp->pcs; 1650 int ret; 1651 1652 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1653 if (ret) { 1654 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1655 return ret; 1656 } 1657 1658 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1659 if (ret) { 1660 dev_err(qmp->dev, "reset assert failed\n"); 1661 goto err_disable_regulators; 1662 } 1663 1664 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 1665 if (ret) { 1666 dev_err(qmp->dev, "reset deassert failed\n"); 1667 goto err_disable_regulators; 1668 } 1669 1670 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1671 if (ret) 1672 goto err_assert_reset; 1673 1674 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 1675 1676 return 0; 1677 1678 err_assert_reset: 1679 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1680 err_disable_regulators: 1681 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1682 1683 return ret; 1684 } 1685 1686 static int qmp_usb_exit(struct phy *phy) 1687 { 1688 struct qmp_usb *qmp = phy_get_drvdata(phy); 1689 const struct qmp_phy_cfg *cfg = qmp->cfg; 1690 1691 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1692 1693 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1694 1695 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 1696 1697 return 0; 1698 } 1699 1700 static int qmp_usb_power_on(struct phy *phy) 1701 { 1702 struct qmp_usb *qmp = phy_get_drvdata(phy); 1703 const struct qmp_phy_cfg *cfg = qmp->cfg; 1704 void __iomem *tx = qmp->tx; 1705 void __iomem *rx = qmp->rx; 1706 void __iomem *pcs = qmp->pcs; 1707 void __iomem *status; 1708 unsigned int val; 1709 int ret; 1710 1711 qmp_usb_serdes_init(qmp); 1712 1713 ret = clk_prepare_enable(qmp->pipe_clk); 1714 if (ret) { 1715 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 1716 return ret; 1717 } 1718 1719 /* Tx, Rx, and PCS configurations */ 1720 qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 1721 qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 1722 1723 if (cfg->lanes >= 2) { 1724 qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 1725 qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 1726 } 1727 1728 qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 1729 1730 if (cfg->has_pwrdn_delay) 1731 usleep_range(10, 20); 1732 1733 /* Pull PHY out of reset state */ 1734 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1735 1736 /* start SerDes and Phy-Coding-Sublayer */ 1737 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 1738 1739 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 1740 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 1741 PHY_INIT_COMPLETE_TIMEOUT); 1742 if (ret) { 1743 dev_err(qmp->dev, "phy initialization timed-out\n"); 1744 goto err_disable_pipe_clk; 1745 } 1746 1747 return 0; 1748 1749 err_disable_pipe_clk: 1750 clk_disable_unprepare(qmp->pipe_clk); 1751 1752 return ret; 1753 } 1754 1755 static int qmp_usb_power_off(struct phy *phy) 1756 { 1757 struct qmp_usb *qmp = phy_get_drvdata(phy); 1758 const struct qmp_phy_cfg *cfg = qmp->cfg; 1759 1760 clk_disable_unprepare(qmp->pipe_clk); 1761 1762 /* PHY reset */ 1763 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 1764 1765 /* stop SerDes and Phy-Coding-Sublayer */ 1766 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 1767 SERDES_START | PCS_START); 1768 1769 /* Put PHY into POWER DOWN state: active low */ 1770 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 1771 SW_PWRDN); 1772 1773 return 0; 1774 } 1775 1776 static int qmp_usb_enable(struct phy *phy) 1777 { 1778 int ret; 1779 1780 ret = qmp_usb_init(phy); 1781 if (ret) 1782 return ret; 1783 1784 ret = qmp_usb_power_on(phy); 1785 if (ret) 1786 qmp_usb_exit(phy); 1787 1788 return ret; 1789 } 1790 1791 static int qmp_usb_disable(struct phy *phy) 1792 { 1793 int ret; 1794 1795 ret = qmp_usb_power_off(phy); 1796 if (ret) 1797 return ret; 1798 return qmp_usb_exit(phy); 1799 } 1800 1801 static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 1802 { 1803 struct qmp_usb *qmp = phy_get_drvdata(phy); 1804 1805 qmp->mode = mode; 1806 1807 return 0; 1808 } 1809 1810 static const struct phy_ops qmp_usb_phy_ops = { 1811 .init = qmp_usb_enable, 1812 .exit = qmp_usb_disable, 1813 .set_mode = qmp_usb_set_mode, 1814 .owner = THIS_MODULE, 1815 }; 1816 1817 static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp) 1818 { 1819 const struct qmp_phy_cfg *cfg = qmp->cfg; 1820 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 1821 void __iomem *pcs_misc = qmp->pcs_misc; 1822 u32 intr_mask; 1823 1824 if (qmp->mode == PHY_MODE_USB_HOST_SS || 1825 qmp->mode == PHY_MODE_USB_DEVICE_SS) 1826 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 1827 else 1828 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 1829 1830 /* Clear any pending interrupts status */ 1831 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1832 /* Writing 1 followed by 0 clears the interrupt */ 1833 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1834 1835 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1836 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 1837 1838 /* Enable required PHY autonomous mode interrupts */ 1839 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 1840 1841 /* Enable i/o clamp_n for autonomous mode */ 1842 if (pcs_misc) 1843 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 1844 } 1845 1846 static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp) 1847 { 1848 const struct qmp_phy_cfg *cfg = qmp->cfg; 1849 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 1850 void __iomem *pcs_misc = qmp->pcs_misc; 1851 1852 /* Disable i/o clamp_n on resume for normal mode */ 1853 if (pcs_misc) 1854 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 1855 1856 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 1857 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 1858 1859 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1860 /* Writing 1 followed by 0 clears the interrupt */ 1861 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 1862 } 1863 1864 static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev) 1865 { 1866 struct qmp_usb *qmp = dev_get_drvdata(dev); 1867 const struct qmp_phy_cfg *cfg = qmp->cfg; 1868 1869 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 1870 1871 if (!qmp->phy->init_count) { 1872 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1873 return 0; 1874 } 1875 1876 qmp_usb_enable_autonomous_mode(qmp); 1877 1878 clk_disable_unprepare(qmp->pipe_clk); 1879 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1880 1881 return 0; 1882 } 1883 1884 static int __maybe_unused qmp_usb_runtime_resume(struct device *dev) 1885 { 1886 struct qmp_usb *qmp = dev_get_drvdata(dev); 1887 const struct qmp_phy_cfg *cfg = qmp->cfg; 1888 int ret = 0; 1889 1890 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 1891 1892 if (!qmp->phy->init_count) { 1893 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 1894 return 0; 1895 } 1896 1897 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 1898 if (ret) 1899 return ret; 1900 1901 ret = clk_prepare_enable(qmp->pipe_clk); 1902 if (ret) { 1903 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 1904 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 1905 return ret; 1906 } 1907 1908 qmp_usb_disable_autonomous_mode(qmp); 1909 1910 return 0; 1911 } 1912 1913 static const struct dev_pm_ops qmp_usb_pm_ops = { 1914 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend, 1915 qmp_usb_runtime_resume, NULL) 1916 }; 1917 1918 static int qmp_usb_vreg_init(struct qmp_usb *qmp) 1919 { 1920 const struct qmp_phy_cfg *cfg = qmp->cfg; 1921 struct device *dev = qmp->dev; 1922 int num = cfg->num_vregs; 1923 int i; 1924 1925 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 1926 if (!qmp->vregs) 1927 return -ENOMEM; 1928 1929 for (i = 0; i < num; i++) 1930 qmp->vregs[i].supply = cfg->vreg_list[i]; 1931 1932 return devm_regulator_bulk_get(dev, num, qmp->vregs); 1933 } 1934 1935 static int qmp_usb_reset_init(struct qmp_usb *qmp) 1936 { 1937 const struct qmp_phy_cfg *cfg = qmp->cfg; 1938 struct device *dev = qmp->dev; 1939 int i; 1940 int ret; 1941 1942 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 1943 sizeof(*qmp->resets), GFP_KERNEL); 1944 if (!qmp->resets) 1945 return -ENOMEM; 1946 1947 for (i = 0; i < cfg->num_resets; i++) 1948 qmp->resets[i].id = cfg->reset_list[i]; 1949 1950 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 1951 if (ret) 1952 return dev_err_probe(dev, ret, "failed to get resets\n"); 1953 1954 return 0; 1955 } 1956 1957 static int qmp_usb_clk_init(struct qmp_usb *qmp) 1958 { 1959 const struct qmp_phy_cfg *cfg = qmp->cfg; 1960 struct device *dev = qmp->dev; 1961 int num = cfg->num_clks; 1962 int i; 1963 1964 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 1965 if (!qmp->clks) 1966 return -ENOMEM; 1967 1968 for (i = 0; i < num; i++) 1969 qmp->clks[i].id = cfg->clk_list[i]; 1970 1971 return devm_clk_bulk_get(dev, num, qmp->clks); 1972 } 1973 1974 static void phy_clk_release_provider(void *res) 1975 { 1976 of_clk_del_provider(res); 1977 } 1978 1979 /* 1980 * Register a fixed rate pipe clock. 1981 * 1982 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 1983 * controls it. The <s>_pipe_clk coming out of the GCC is requested 1984 * by the PHY driver for its operations. 1985 * We register the <s>_pipe_clksrc here. The gcc driver takes care 1986 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 1987 * Below picture shows this relationship. 1988 * 1989 * +---------------+ 1990 * | PHY block |<<---------------------------------------+ 1991 * | | | 1992 * | +-------+ | +-----+ | 1993 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 1994 * clk | +-------+ | +-----+ 1995 * +---------------+ 1996 */ 1997 static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np) 1998 { 1999 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2000 struct clk_init_data init = { }; 2001 int ret; 2002 2003 ret = of_property_read_string(np, "clock-output-names", &init.name); 2004 if (ret) { 2005 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2006 return ret; 2007 } 2008 2009 init.ops = &clk_fixed_rate_ops; 2010 2011 /* controllers using QMP phys use 125MHz pipe clock interface */ 2012 fixed->fixed_rate = 125000000; 2013 fixed->hw.init = &init; 2014 2015 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2016 if (ret) 2017 return ret; 2018 2019 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2020 if (ret) 2021 return ret; 2022 2023 /* 2024 * Roll a devm action because the clock provider is the child node, but 2025 * the child node is not actually a device. 2026 */ 2027 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2028 } 2029 2030 static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np, 2031 int index, bool exclusive) 2032 { 2033 struct resource res; 2034 2035 if (!exclusive) { 2036 if (of_address_to_resource(np, index, &res)) 2037 return IOMEM_ERR_PTR(-EINVAL); 2038 2039 return devm_ioremap(dev, res.start, resource_size(&res)); 2040 } 2041 2042 return devm_of_iomap(dev, np, index, NULL); 2043 } 2044 2045 static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np) 2046 { 2047 struct platform_device *pdev = to_platform_device(qmp->dev); 2048 const struct qmp_phy_cfg *cfg = qmp->cfg; 2049 struct device *dev = qmp->dev; 2050 bool exclusive = true; 2051 2052 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2053 if (IS_ERR(qmp->serdes)) 2054 return PTR_ERR(qmp->serdes); 2055 2056 /* 2057 * FIXME: These bindings should be fixed to not rely on overlapping 2058 * mappings for PCS. 2059 */ 2060 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy")) 2061 exclusive = false; 2062 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy")) 2063 exclusive = false; 2064 2065 /* 2066 * Get memory resources for the PHY: 2067 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2068 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2069 * For single lane PHYs: pcs_misc (optional) -> 3. 2070 */ 2071 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2072 if (IS_ERR(qmp->tx)) 2073 return PTR_ERR(qmp->tx); 2074 2075 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2076 if (IS_ERR(qmp->rx)) 2077 return PTR_ERR(qmp->rx); 2078 2079 qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive); 2080 if (IS_ERR(qmp->pcs)) 2081 return PTR_ERR(qmp->pcs); 2082 2083 if (cfg->pcs_usb_offset) 2084 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 2085 2086 if (cfg->lanes >= 2) { 2087 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2088 if (IS_ERR(qmp->tx2)) 2089 return PTR_ERR(qmp->tx2); 2090 2091 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2092 if (IS_ERR(qmp->rx2)) 2093 return PTR_ERR(qmp->rx2); 2094 2095 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2096 } else { 2097 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2098 } 2099 2100 if (IS_ERR(qmp->pcs_misc)) { 2101 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2102 qmp->pcs_misc = NULL; 2103 } 2104 2105 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2106 if (IS_ERR(qmp->pipe_clk)) { 2107 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2108 "failed to get pipe clock\n"); 2109 } 2110 2111 return 0; 2112 } 2113 2114 static int qmp_usb_parse_dt(struct qmp_usb *qmp) 2115 { 2116 struct platform_device *pdev = to_platform_device(qmp->dev); 2117 const struct qmp_phy_cfg *cfg = qmp->cfg; 2118 const struct qmp_usb_offsets *offs = cfg->offsets; 2119 struct device *dev = qmp->dev; 2120 void __iomem *base; 2121 2122 if (!offs) 2123 return -EINVAL; 2124 2125 base = devm_platform_ioremap_resource(pdev, 0); 2126 if (IS_ERR(base)) 2127 return PTR_ERR(base); 2128 2129 qmp->serdes = base + offs->serdes; 2130 qmp->pcs = base + offs->pcs; 2131 qmp->pcs_misc = base + offs->pcs_misc; 2132 qmp->pcs_usb = base + offs->pcs_usb; 2133 qmp->tx = base + offs->tx; 2134 qmp->rx = base + offs->rx; 2135 2136 if (cfg->lanes >= 2) { 2137 qmp->tx2 = base + offs->tx2; 2138 qmp->rx2 = base + offs->rx2; 2139 } 2140 2141 qmp->pipe_clk = devm_clk_get(dev, "pipe"); 2142 if (IS_ERR(qmp->pipe_clk)) { 2143 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2144 "failed to get pipe clock\n"); 2145 } 2146 2147 return 0; 2148 } 2149 2150 static int qmp_usb_probe(struct platform_device *pdev) 2151 { 2152 struct device *dev = &pdev->dev; 2153 struct phy_provider *phy_provider; 2154 struct device_node *np; 2155 struct qmp_usb *qmp; 2156 int ret; 2157 2158 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2159 if (!qmp) 2160 return -ENOMEM; 2161 2162 qmp->dev = dev; 2163 2164 qmp->cfg = of_device_get_match_data(dev); 2165 if (!qmp->cfg) 2166 return -EINVAL; 2167 2168 ret = qmp_usb_clk_init(qmp); 2169 if (ret) 2170 return ret; 2171 2172 ret = qmp_usb_reset_init(qmp); 2173 if (ret) 2174 return ret; 2175 2176 ret = qmp_usb_vreg_init(qmp); 2177 if (ret) 2178 return ret; 2179 2180 /* Check for legacy binding with child node. */ 2181 np = of_get_next_available_child(dev->of_node, NULL); 2182 if (np) { 2183 ret = qmp_usb_parse_dt_legacy(qmp, np); 2184 } else { 2185 np = of_node_get(dev->of_node); 2186 ret = qmp_usb_parse_dt(qmp); 2187 } 2188 if (ret) 2189 goto err_node_put; 2190 2191 pm_runtime_set_active(dev); 2192 ret = devm_pm_runtime_enable(dev); 2193 if (ret) 2194 goto err_node_put; 2195 /* 2196 * Prevent runtime pm from being ON by default. Users can enable 2197 * it using power/control in sysfs. 2198 */ 2199 pm_runtime_forbid(dev); 2200 2201 ret = phy_pipe_clk_register(qmp, np); 2202 if (ret) 2203 goto err_node_put; 2204 2205 qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops); 2206 if (IS_ERR(qmp->phy)) { 2207 ret = PTR_ERR(qmp->phy); 2208 dev_err(dev, "failed to create PHY: %d\n", ret); 2209 goto err_node_put; 2210 } 2211 2212 phy_set_drvdata(qmp->phy, qmp); 2213 2214 of_node_put(np); 2215 2216 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2217 2218 return PTR_ERR_OR_ZERO(phy_provider); 2219 2220 err_node_put: 2221 of_node_put(np); 2222 return ret; 2223 } 2224 2225 static const struct of_device_id qmp_usb_of_match_table[] = { 2226 { 2227 .compatible = "qcom,ipq6018-qmp-usb3-phy", 2228 .data = &ipq8074_usb3phy_cfg, 2229 }, { 2230 .compatible = "qcom,ipq8074-qmp-usb3-phy", 2231 .data = &ipq8074_usb3phy_cfg, 2232 }, { 2233 .compatible = "qcom,ipq9574-qmp-usb3-phy", 2234 .data = &ipq9574_usb3phy_cfg, 2235 }, { 2236 .compatible = "qcom,msm8996-qmp-usb3-phy", 2237 .data = &msm8996_usb3phy_cfg, 2238 }, { 2239 .compatible = "qcom,msm8998-qmp-usb3-phy", 2240 .data = &msm8998_usb3phy_cfg, 2241 }, { 2242 .compatible = "qcom,qcm2290-qmp-usb3-phy", 2243 .data = &qcm2290_usb3phy_cfg, 2244 }, { 2245 .compatible = "qcom,sa8775p-qmp-usb3-uni-phy", 2246 .data = &sa8775p_usb3_uniphy_cfg, 2247 }, { 2248 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy", 2249 .data = &sc8280xp_usb3_uniphy_cfg, 2250 }, { 2251 .compatible = "qcom,sdm845-qmp-usb3-uni-phy", 2252 .data = &qmp_v3_usb3_uniphy_cfg, 2253 }, { 2254 .compatible = "qcom,sdx55-qmp-usb3-uni-phy", 2255 .data = &sdx55_usb3_uniphy_cfg, 2256 }, { 2257 .compatible = "qcom,sdx65-qmp-usb3-uni-phy", 2258 .data = &sdx65_usb3_uniphy_cfg, 2259 }, { 2260 .compatible = "qcom,sm6115-qmp-usb3-phy", 2261 .data = &qcm2290_usb3phy_cfg, 2262 }, { 2263 .compatible = "qcom,sm8150-qmp-usb3-uni-phy", 2264 .data = &sm8150_usb3_uniphy_cfg, 2265 }, { 2266 .compatible = "qcom,sm8250-qmp-usb3-uni-phy", 2267 .data = &sm8250_usb3_uniphy_cfg, 2268 }, { 2269 .compatible = "qcom,sm8350-qmp-usb3-uni-phy", 2270 .data = &sm8350_usb3_uniphy_cfg, 2271 }, 2272 { }, 2273 }; 2274 MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table); 2275 2276 static struct platform_driver qmp_usb_driver = { 2277 .probe = qmp_usb_probe, 2278 .driver = { 2279 .name = "qcom-qmp-usb-phy", 2280 .pm = &qmp_usb_pm_ops, 2281 .of_match_table = qmp_usb_of_match_table, 2282 }, 2283 }; 2284 2285 module_platform_driver(qmp_usb_driver); 2286 2287 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2288 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver"); 2289 MODULE_LICENSE("GPL v2"); 2290