1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include "phy-qcom-qmp.h" 24 25 /* QPHY_SW_RESET bit */ 26 #define SW_RESET BIT(0) 27 /* QPHY_POWER_DOWN_CONTROL */ 28 #define SW_PWRDN BIT(0) 29 /* QPHY_START_CONTROL bits */ 30 #define SERDES_START BIT(0) 31 #define PCS_START BIT(1) 32 /* QPHY_PCS_STATUS bit */ 33 #define PHYSTATUS BIT(6) 34 35 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 36 /* DP PHY soft reset */ 37 #define SW_DPPHY_RESET BIT(0) 38 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 39 #define SW_DPPHY_RESET_MUX BIT(1) 40 /* USB3 PHY soft reset */ 41 #define SW_USB3PHY_RESET BIT(2) 42 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 43 #define SW_USB3PHY_RESET_MUX BIT(3) 44 45 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 46 #define USB3_MODE BIT(0) /* enables USB3 mode */ 47 #define DP_MODE BIT(1) /* enables DP mode */ 48 49 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 50 #define ARCVR_DTCT_EN BIT(0) 51 #define ALFPS_DTCT_EN BIT(1) 52 #define ARCVR_DTCT_EVENT_SEL BIT(4) 53 54 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 55 #define IRQ_CLEAR BIT(0) 56 57 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 58 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 59 60 #define PHY_INIT_COMPLETE_TIMEOUT 10000 61 62 struct qmp_phy_init_tbl { 63 unsigned int offset; 64 unsigned int val; 65 /* 66 * mask of lanes for which this register is written 67 * for cases when second lane needs different values 68 */ 69 u8 lane_mask; 70 }; 71 72 #define QMP_PHY_INIT_CFG(o, v) \ 73 { \ 74 .offset = o, \ 75 .val = v, \ 76 .lane_mask = 0xff, \ 77 } 78 79 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 80 { \ 81 .offset = o, \ 82 .val = v, \ 83 .lane_mask = l, \ 84 } 85 86 /* set of registers with offsets different per-PHY */ 87 enum qphy_reg_layout { 88 /* PCS registers */ 89 QPHY_SW_RESET, 90 QPHY_START_CTRL, 91 QPHY_PCS_STATUS, 92 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 93 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 94 QPHY_PCS_POWER_DOWN_CONTROL, 95 /* PCS_MISC registers */ 96 QPHY_PCS_MISC_TYPEC_CTRL, 97 /* Keep last to ensure regs_layout arrays are properly initialized */ 98 QPHY_LAYOUT_SIZE 99 }; 100 101 static const unsigned int usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 102 [QPHY_SW_RESET] = 0x00, 103 [QPHY_START_CTRL] = 0x08, 104 [QPHY_PCS_STATUS] = 0x17c, 105 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d4, 106 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0d8, 107 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 108 }; 109 110 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 111 [QPHY_SW_RESET] = 0x00, 112 [QPHY_START_CTRL] = 0x08, 113 [QPHY_PCS_STATUS] = 0x174, 114 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x0d8, 115 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x0dc, 116 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 117 }; 118 119 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 120 [QPHY_SW_RESET] = 0x00, 121 [QPHY_START_CTRL] = 0x44, 122 [QPHY_PCS_STATUS] = 0x14, 123 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x40, 124 125 /* In PCS_USB */ 126 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0x008, 127 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0x014, 128 }; 129 130 static const unsigned int qcm2290_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 131 [QPHY_SW_RESET] = 0x00, 132 [QPHY_PCS_POWER_DOWN_CONTROL] = 0x04, 133 [QPHY_START_CTRL] = 0x08, 134 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = 0xd8, 135 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = 0xdc, 136 [QPHY_PCS_STATUS] = 0x174, 137 [QPHY_PCS_MISC_TYPEC_CTRL] = 0x00, 138 }; 139 140 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { 141 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), 142 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 143 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 144 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 145 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 146 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 147 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 148 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 149 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 150 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 151 /* PLL and Loop filter settings */ 152 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 153 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 154 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 155 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 156 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 157 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 158 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 159 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 160 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 161 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 162 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 163 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 164 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 165 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 166 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 167 /* SSC settings */ 168 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 169 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 170 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 171 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 172 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 173 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 174 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 175 }; 176 177 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { 178 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), 179 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 180 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 181 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), 182 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 183 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 184 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 185 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 186 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), 187 }; 188 189 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { 190 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 191 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 192 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 194 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 195 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 196 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 207 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 210 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 211 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 212 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 213 }; 214 215 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { 216 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 217 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 218 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 219 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 220 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 221 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 222 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 223 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 224 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), 225 /* PLL and Loop filter settings */ 226 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 227 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 228 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 229 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 230 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 231 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 232 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 233 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 234 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 235 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 236 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 237 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 238 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 239 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 240 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 241 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 242 /* SSC settings */ 243 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 244 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 245 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 246 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 247 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 248 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 249 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 250 }; 251 252 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { 253 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 254 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 255 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 256 }; 257 258 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { 259 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 260 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 261 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 262 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 263 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), 264 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 265 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 266 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 267 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), 268 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 269 }; 270 271 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { 272 /* FLL settings */ 273 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03), 274 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02), 275 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09), 276 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42), 277 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85), 278 279 /* Lock Det settings */ 280 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1), 281 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f), 282 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47), 283 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08), 284 }; 285 286 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 287 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 288 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 289 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 290 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 291 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 301 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 310 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 311 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 319 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 320 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 321 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 323 }; 324 325 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 326 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 327 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 328 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 329 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 330 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 331 }; 332 333 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 334 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 335 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 336 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 337 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 338 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 339 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 340 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 341 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 342 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 343 }; 344 345 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 346 /* FLL settings */ 347 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 348 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 349 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 350 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 351 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 352 353 /* Lock Det settings */ 354 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 355 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 356 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 357 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 358 359 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 360 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 361 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 362 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 363 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 364 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 369 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 374 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 378 379 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 386 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 389 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 390 }; 391 392 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { 393 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 394 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 395 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 396 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 397 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 400 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 429 }; 430 431 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { 432 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 433 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 434 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 435 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 436 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 437 }; 438 439 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { 440 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), 441 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), 442 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 443 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 444 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 445 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 446 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 447 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 448 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 449 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 450 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 451 }; 452 453 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { 454 /* FLL settings */ 455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 459 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 460 461 /* Lock Det settings */ 462 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 466 467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), 471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), 472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), 473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), 474 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 475 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 480 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 486 487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 488 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 491 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 492 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 494 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 498 499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 500 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 501 }; 502 503 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { 504 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 505 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 506 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), 508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 542 }; 543 544 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { 545 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 546 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 547 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 548 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 549 }; 550 551 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { 552 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 553 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 554 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 555 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 556 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), 557 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 558 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), 559 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 560 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 561 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 562 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 563 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 564 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 565 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 566 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 567 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), 568 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 569 }; 570 571 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { 572 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 573 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 574 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 575 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 576 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 577 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), 595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), 607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 610 }; 611 612 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 613 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 614 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 615 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 616 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 617 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 618 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 619 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 620 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 621 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 622 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 623 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 624 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 625 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 626 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 627 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 630 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 631 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 632 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 633 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 640 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 647 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 648 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 649 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 650 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 651 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 652 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 653 }; 654 655 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 656 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 657 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 658 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 659 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 660 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 661 }; 662 663 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 664 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 665 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 700 }; 701 702 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 703 /* Lock Det settings */ 704 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 705 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 706 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 707 708 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 709 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 710 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 711 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 712 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 713 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 714 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 715 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 716 }; 717 718 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 719 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 720 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 721 }; 722 723 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { 724 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 725 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 726 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 727 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 728 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 729 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 730 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 731 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 732 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 733 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 734 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 764 }; 765 766 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { 767 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 768 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), 769 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 770 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), 771 }; 772 773 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { 774 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 775 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 776 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), 777 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), 778 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), 779 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 780 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), 794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 810 }; 811 812 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { 813 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 814 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 815 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 816 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 817 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 818 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 819 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 820 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), 821 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 822 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 823 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 824 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 825 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 826 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 827 }; 828 829 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = { 830 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 831 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 832 }; 833 834 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 835 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 836 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 837 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 838 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 839 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 840 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 841 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 842 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 843 }; 844 845 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 846 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 847 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 848 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 849 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 850 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 851 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 852 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 853 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 854 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 855 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 856 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 857 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 858 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 859 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 860 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 861 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 862 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 863 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 864 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 865 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 866 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 867 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 868 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 869 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 870 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 871 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 872 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 873 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 874 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 875 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 876 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 877 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 878 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 879 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 880 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 881 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 882 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 883 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 884 }; 885 886 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 887 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 888 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 889 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 890 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 891 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 892 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 893 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 894 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 895 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 896 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 897 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 898 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 899 }; 900 901 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 902 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 903 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 904 }; 905 906 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { 907 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 908 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 909 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), 910 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 911 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 912 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 913 }; 914 915 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { 916 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 917 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), 918 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 919 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 920 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 921 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 922 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 923 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 924 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 925 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 926 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 927 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 928 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 929 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), 936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 937 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 938 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 939 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 942 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 943 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 944 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 945 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 946 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 947 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 948 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 949 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 950 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 951 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 952 }; 953 954 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { 955 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 956 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 957 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 958 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 959 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 960 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 961 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 962 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 963 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 964 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 965 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 966 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 967 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 968 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 969 }; 970 971 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = { 972 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 973 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 974 }; 975 976 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { 977 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 978 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 979 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), 980 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 981 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), 982 }; 983 984 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { 985 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), 986 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 987 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 988 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 989 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 990 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 991 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 992 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 993 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 994 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 995 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 996 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), 997 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 998 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), 999 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 1021 }; 1022 1023 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { 1024 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1025 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1026 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1027 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1028 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1029 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1030 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), 1031 }; 1032 1033 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { 1034 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 1035 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1036 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1037 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1038 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1039 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1040 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1041 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1042 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1043 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1044 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1045 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1046 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1047 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1048 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1049 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1050 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1051 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1052 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1053 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1054 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1055 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1056 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1057 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1058 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1059 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1060 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1061 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1062 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1063 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1064 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1065 }; 1066 1067 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 1068 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 1069 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 1070 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1071 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1072 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 1073 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1074 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 1075 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 1076 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 1077 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1078 }; 1079 1080 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 1081 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1082 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1083 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1084 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1085 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1086 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1087 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1088 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1089 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1090 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1091 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1092 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1093 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 1105 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 1106 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 1107 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 1108 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1118 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 1119 }; 1120 1121 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 1122 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1123 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1124 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1125 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1126 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1127 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1128 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1129 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1130 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1131 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1132 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1133 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1134 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1135 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1136 }; 1137 1138 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 1139 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1140 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1141 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1142 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1143 }; 1144 1145 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { 1146 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1148 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1149 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1153 }; 1154 1155 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { 1156 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), 1157 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1163 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1164 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1171 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1172 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1173 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1174 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1175 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1176 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1177 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1178 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1179 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1180 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1181 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1182 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1183 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1184 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1185 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1186 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1187 }; 1188 1189 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { 1190 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1191 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1192 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1193 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1194 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1195 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1196 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1197 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1198 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1199 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1200 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1201 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1202 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1203 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1204 }; 1205 1206 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = { 1207 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1208 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1209 }; 1210 1211 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { 1212 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 1213 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 1214 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 1215 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 1216 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), 1217 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), 1218 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 1219 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 1220 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 1221 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 1222 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 1223 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 1224 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 1225 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 1226 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 1227 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 1228 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 1229 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1230 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 1231 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 1232 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 1233 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 1234 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), 1235 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 1236 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 1237 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 1238 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 1239 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 1240 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 1241 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 1242 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 1243 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 1244 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 1245 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 1246 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 1247 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 1248 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), 1249 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), 1250 }; 1251 1252 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { 1253 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 1254 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 1255 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 1256 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 1257 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), 1258 }; 1259 1260 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { 1261 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 1262 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x00), 1263 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 1264 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 1265 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 1266 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 1267 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 1268 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 1269 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 1270 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 1271 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 1272 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1273 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), 1274 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 1275 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 1276 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 1277 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), 1278 }; 1279 1280 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { 1281 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 1282 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 1283 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 1284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 1285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 1286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 1287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 1288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 1289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 1290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 1291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 1292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 1293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 1294 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 1295 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 1296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 1297 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1298 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1299 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 1300 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 1301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 1302 }; 1303 1304 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = { 1305 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1306 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1307 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1308 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab), 1310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea), 1311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02), 1312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1322 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02), 1323 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24), 1324 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1325 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82), 1326 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1327 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea), 1328 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1329 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1330 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1331 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1332 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1333 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1334 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 1335 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 1336 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1337 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1338 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1339 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde), 1340 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07), 1341 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1342 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1343 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1344 }; 1345 1346 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = { 1347 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1348 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1349 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1350 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1351 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1352 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 1353 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1354 }; 1355 1356 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = { 1357 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), 1358 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1359 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1360 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1361 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1362 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1363 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1364 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1365 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1366 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1367 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1368 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1369 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1370 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1371 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1372 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1373 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1374 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1375 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a), 1376 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1377 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1378 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1379 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1380 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1381 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1382 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1383 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1384 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1385 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1386 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1387 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1388 }; 1389 1390 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = { 1391 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1392 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1393 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1394 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1395 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1396 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1397 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1398 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1399 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1400 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1401 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a), 1402 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1403 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1404 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1405 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1406 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1407 }; 1408 1409 struct qmp_usb_offsets { 1410 u16 serdes; 1411 u16 pcs; 1412 u16 pcs_usb; 1413 u16 tx; 1414 u16 rx; 1415 }; 1416 1417 /* struct qmp_phy_cfg - per-PHY initialization config */ 1418 struct qmp_phy_cfg { 1419 int lanes; 1420 1421 const struct qmp_usb_offsets *offsets; 1422 1423 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1424 const struct qmp_phy_init_tbl *serdes_tbl; 1425 int serdes_tbl_num; 1426 const struct qmp_phy_init_tbl *tx_tbl; 1427 int tx_tbl_num; 1428 const struct qmp_phy_init_tbl *rx_tbl; 1429 int rx_tbl_num; 1430 const struct qmp_phy_init_tbl *pcs_tbl; 1431 int pcs_tbl_num; 1432 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1433 int pcs_usb_tbl_num; 1434 1435 /* clock ids to be requested */ 1436 const char * const *clk_list; 1437 int num_clks; 1438 /* resets to be requested */ 1439 const char * const *reset_list; 1440 int num_resets; 1441 /* regulators to be requested */ 1442 const char * const *vreg_list; 1443 int num_vregs; 1444 1445 /* array of registers with different offsets */ 1446 const unsigned int *regs; 1447 1448 /* true, if PHY needs delay after POWER_DOWN */ 1449 bool has_pwrdn_delay; 1450 1451 /* true, if PHY has a separate DP_COM control block */ 1452 bool has_phy_dp_com_ctrl; 1453 1454 /* Offset from PCS to PCS_USB region */ 1455 unsigned int pcs_usb_offset; 1456 }; 1457 1458 struct qmp_usb { 1459 struct device *dev; 1460 1461 const struct qmp_phy_cfg *cfg; 1462 1463 void __iomem *serdes; 1464 void __iomem *pcs; 1465 void __iomem *pcs_misc; 1466 void __iomem *pcs_usb; 1467 void __iomem *tx; 1468 void __iomem *rx; 1469 void __iomem *tx2; 1470 void __iomem *rx2; 1471 1472 void __iomem *dp_com; 1473 1474 struct clk *pipe_clk; 1475 struct clk_bulk_data *clks; 1476 struct reset_control_bulk_data *resets; 1477 struct regulator_bulk_data *vregs; 1478 1479 enum phy_mode mode; 1480 1481 struct phy *phy; 1482 1483 struct clk_fixed_rate pipe_clk_fixed; 1484 }; 1485 1486 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1487 { 1488 u32 reg; 1489 1490 reg = readl(base + offset); 1491 reg |= val; 1492 writel(reg, base + offset); 1493 1494 /* ensure that above write is through */ 1495 readl(base + offset); 1496 } 1497 1498 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1499 { 1500 u32 reg; 1501 1502 reg = readl(base + offset); 1503 reg &= ~val; 1504 writel(reg, base + offset); 1505 1506 /* ensure that above write is through */ 1507 readl(base + offset); 1508 } 1509 1510 /* list of clocks required by phy */ 1511 static const char * const msm8996_phy_clk_l[] = { 1512 "aux", "cfg_ahb", "ref", 1513 }; 1514 1515 static const char * const qmp_v3_phy_clk_l[] = { 1516 "aux", "cfg_ahb", "ref", "com_aux", 1517 }; 1518 1519 static const char * const qmp_v4_phy_clk_l[] = { 1520 "aux", "ref", "com_aux", 1521 }; 1522 1523 static const char * const qmp_v4_ref_phy_clk_l[] = { 1524 "aux", "ref_clk_src", "ref", "com_aux", 1525 }; 1526 1527 /* the primary usb3 phy on sm8250 doesn't have a ref clock */ 1528 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { 1529 "aux", "ref_clk_src", "com_aux" 1530 }; 1531 1532 /* usb3 phy on sdx55 doesn't have com_aux clock */ 1533 static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { 1534 "aux", "cfg_ahb", "ref" 1535 }; 1536 1537 static const char * const qcm2290_usb3phy_clk_l[] = { 1538 "cfg_ahb", "ref", "com_aux", 1539 }; 1540 1541 /* list of resets */ 1542 static const char * const msm8996_usb3phy_reset_l[] = { 1543 "phy", "common", 1544 }; 1545 1546 static const char * const sc7180_usb3phy_reset_l[] = { 1547 "phy", 1548 }; 1549 1550 static const char * const qcm2290_usb3phy_reset_l[] = { 1551 "phy_phy", "phy", 1552 }; 1553 1554 /* list of regulators */ 1555 static const char * const qmp_phy_vreg_l[] = { 1556 "vdda-phy", "vdda-pll", 1557 }; 1558 1559 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { 1560 .serdes = 0, 1561 .pcs = 0x0200, 1562 .pcs_usb = 0x1200, 1563 .tx = 0x0e00, 1564 .rx = 0x1000, 1565 }; 1566 1567 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { 1568 .lanes = 1, 1569 1570 .serdes_tbl = ipq8074_usb3_serdes_tbl, 1571 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), 1572 .tx_tbl = msm8996_usb3_tx_tbl, 1573 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1574 .rx_tbl = ipq8074_usb3_rx_tbl, 1575 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), 1576 .pcs_tbl = ipq8074_usb3_pcs_tbl, 1577 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), 1578 .clk_list = msm8996_phy_clk_l, 1579 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1580 .reset_list = msm8996_usb3phy_reset_l, 1581 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1582 .vreg_list = qmp_phy_vreg_l, 1583 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1584 .regs = qmp_v3_usb3phy_regs_layout, 1585 }; 1586 1587 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { 1588 .lanes = 1, 1589 1590 .serdes_tbl = msm8996_usb3_serdes_tbl, 1591 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), 1592 .tx_tbl = msm8996_usb3_tx_tbl, 1593 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1594 .rx_tbl = msm8996_usb3_rx_tbl, 1595 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), 1596 .pcs_tbl = msm8996_usb3_pcs_tbl, 1597 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), 1598 .clk_list = msm8996_phy_clk_l, 1599 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1600 .reset_list = msm8996_usb3phy_reset_l, 1601 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1602 .vreg_list = qmp_phy_vreg_l, 1603 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1604 .regs = usb3phy_regs_layout, 1605 }; 1606 1607 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { 1608 .lanes = 2, 1609 1610 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1611 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1612 .tx_tbl = qmp_v3_usb3_tx_tbl, 1613 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1614 .rx_tbl = qmp_v3_usb3_rx_tbl, 1615 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1616 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1617 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1618 .clk_list = qmp_v3_phy_clk_l, 1619 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1620 .reset_list = msm8996_usb3phy_reset_l, 1621 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1622 .vreg_list = qmp_phy_vreg_l, 1623 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1624 .regs = qmp_v3_usb3phy_regs_layout, 1625 1626 .has_pwrdn_delay = true, 1627 .has_phy_dp_com_ctrl = true, 1628 }; 1629 1630 static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { 1631 .lanes = 2, 1632 1633 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1634 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1635 .tx_tbl = qmp_v3_usb3_tx_tbl, 1636 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1637 .rx_tbl = qmp_v3_usb3_rx_tbl, 1638 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1639 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1640 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1641 .clk_list = qmp_v3_phy_clk_l, 1642 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1643 .reset_list = sc7180_usb3phy_reset_l, 1644 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1645 .vreg_list = qmp_phy_vreg_l, 1646 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1647 .regs = qmp_v3_usb3phy_regs_layout, 1648 1649 .has_pwrdn_delay = true, 1650 .has_phy_dp_com_ctrl = true, 1651 }; 1652 1653 static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { 1654 .lanes = 1, 1655 1656 .offsets = &qmp_usb_offsets_v5, 1657 1658 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, 1659 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), 1660 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl, 1661 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl), 1662 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl, 1663 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl), 1664 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl, 1665 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl), 1666 .clk_list = qmp_v4_phy_clk_l, 1667 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1668 .reset_list = qcm2290_usb3phy_reset_l, 1669 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 1670 .vreg_list = qmp_phy_vreg_l, 1671 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1672 .regs = qmp_v4_usb3phy_regs_layout, 1673 }; 1674 1675 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { 1676 .lanes = 1, 1677 1678 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, 1679 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), 1680 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, 1681 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), 1682 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, 1683 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), 1684 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, 1685 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), 1686 .clk_list = qmp_v3_phy_clk_l, 1687 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1688 .reset_list = msm8996_usb3phy_reset_l, 1689 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1690 .vreg_list = qmp_phy_vreg_l, 1691 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1692 .regs = qmp_v3_usb3phy_regs_layout, 1693 1694 .has_pwrdn_delay = true, 1695 }; 1696 1697 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { 1698 .lanes = 2, 1699 1700 .serdes_tbl = msm8998_usb3_serdes_tbl, 1701 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), 1702 .tx_tbl = msm8998_usb3_tx_tbl, 1703 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), 1704 .rx_tbl = msm8998_usb3_rx_tbl, 1705 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), 1706 .pcs_tbl = msm8998_usb3_pcs_tbl, 1707 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), 1708 .clk_list = msm8996_phy_clk_l, 1709 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1710 .reset_list = msm8996_usb3phy_reset_l, 1711 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1712 .vreg_list = qmp_phy_vreg_l, 1713 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1714 .regs = qmp_v3_usb3phy_regs_layout, 1715 }; 1716 1717 static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { 1718 .lanes = 2, 1719 1720 .serdes_tbl = sm8150_usb3_serdes_tbl, 1721 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1722 .tx_tbl = sm8150_usb3_tx_tbl, 1723 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1724 .rx_tbl = sm8150_usb3_rx_tbl, 1725 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1726 .pcs_tbl = sm8150_usb3_pcs_tbl, 1727 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1728 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1729 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1730 .clk_list = qmp_v4_ref_phy_clk_l, 1731 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1732 .reset_list = msm8996_usb3phy_reset_l, 1733 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1734 .vreg_list = qmp_phy_vreg_l, 1735 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1736 .regs = qmp_v4_usb3phy_regs_layout, 1737 .pcs_usb_offset = 0x300, 1738 1739 .has_pwrdn_delay = true, 1740 .has_phy_dp_com_ctrl = true, 1741 }; 1742 1743 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { 1744 .lanes = 1, 1745 1746 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1747 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1748 .tx_tbl = sm8150_usb3_uniphy_tx_tbl, 1749 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), 1750 .rx_tbl = sm8150_usb3_uniphy_rx_tbl, 1751 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), 1752 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, 1753 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), 1754 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl, 1755 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl), 1756 .clk_list = qmp_v4_ref_phy_clk_l, 1757 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1758 .reset_list = msm8996_usb3phy_reset_l, 1759 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1760 .vreg_list = qmp_phy_vreg_l, 1761 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1762 .regs = qmp_v4_usb3phy_regs_layout, 1763 .pcs_usb_offset = 0x600, 1764 1765 .has_pwrdn_delay = true, 1766 }; 1767 1768 static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { 1769 .lanes = 2, 1770 1771 .serdes_tbl = sm8150_usb3_serdes_tbl, 1772 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1773 .tx_tbl = sm8250_usb3_tx_tbl, 1774 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1775 .rx_tbl = sm8250_usb3_rx_tbl, 1776 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1777 .pcs_tbl = sm8250_usb3_pcs_tbl, 1778 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1779 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1780 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1781 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1782 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1783 .reset_list = msm8996_usb3phy_reset_l, 1784 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1785 .vreg_list = qmp_phy_vreg_l, 1786 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1787 .regs = qmp_v4_usb3phy_regs_layout, 1788 .pcs_usb_offset = 0x300, 1789 1790 .has_pwrdn_delay = true, 1791 .has_phy_dp_com_ctrl = true, 1792 }; 1793 1794 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { 1795 .lanes = 1, 1796 1797 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1798 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1799 .tx_tbl = sm8250_usb3_uniphy_tx_tbl, 1800 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), 1801 .rx_tbl = sm8250_usb3_uniphy_rx_tbl, 1802 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), 1803 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1804 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1805 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, 1806 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), 1807 .clk_list = qmp_v4_ref_phy_clk_l, 1808 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1809 .reset_list = msm8996_usb3phy_reset_l, 1810 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1811 .vreg_list = qmp_phy_vreg_l, 1812 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1813 .regs = qmp_v4_usb3phy_regs_layout, 1814 .pcs_usb_offset = 0x600, 1815 1816 .has_pwrdn_delay = true, 1817 }; 1818 1819 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { 1820 .lanes = 1, 1821 1822 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1823 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1824 .tx_tbl = sdx55_usb3_uniphy_tx_tbl, 1825 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), 1826 .rx_tbl = sdx55_usb3_uniphy_rx_tbl, 1827 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), 1828 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1829 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1830 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, 1831 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), 1832 .clk_list = qmp_v4_sdx55_usbphy_clk_l, 1833 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), 1834 .reset_list = msm8996_usb3phy_reset_l, 1835 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1836 .vreg_list = qmp_phy_vreg_l, 1837 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1838 .regs = qmp_v4_usb3phy_regs_layout, 1839 .pcs_usb_offset = 0x600, 1840 1841 .has_pwrdn_delay = true, 1842 }; 1843 1844 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { 1845 .lanes = 1, 1846 1847 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1848 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1849 .tx_tbl = sdx65_usb3_uniphy_tx_tbl, 1850 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), 1851 .rx_tbl = sdx65_usb3_uniphy_rx_tbl, 1852 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), 1853 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 1854 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 1855 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, 1856 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), 1857 .clk_list = qmp_v4_sdx55_usbphy_clk_l, 1858 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), 1859 .reset_list = msm8996_usb3phy_reset_l, 1860 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1861 .vreg_list = qmp_phy_vreg_l, 1862 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1863 .regs = qmp_v4_usb3phy_regs_layout, 1864 .pcs_usb_offset = 0x1000, 1865 1866 .has_pwrdn_delay = true, 1867 }; 1868 1869 static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { 1870 .lanes = 2, 1871 1872 .serdes_tbl = sm8150_usb3_serdes_tbl, 1873 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1874 .tx_tbl = sm8350_usb3_tx_tbl, 1875 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 1876 .rx_tbl = sm8350_usb3_rx_tbl, 1877 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 1878 .pcs_tbl = sm8350_usb3_pcs_tbl, 1879 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 1880 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 1881 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 1882 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1883 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1884 .reset_list = msm8996_usb3phy_reset_l, 1885 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1886 .vreg_list = qmp_phy_vreg_l, 1887 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1888 .regs = qmp_v4_usb3phy_regs_layout, 1889 .pcs_usb_offset = 0x300, 1890 1891 .has_pwrdn_delay = true, 1892 .has_phy_dp_com_ctrl = true, 1893 }; 1894 1895 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { 1896 .lanes = 1, 1897 1898 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1899 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1900 .tx_tbl = sm8350_usb3_uniphy_tx_tbl, 1901 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), 1902 .rx_tbl = sm8350_usb3_uniphy_rx_tbl, 1903 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), 1904 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 1905 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 1906 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, 1907 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), 1908 .clk_list = qmp_v4_ref_phy_clk_l, 1909 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1910 .reset_list = msm8996_usb3phy_reset_l, 1911 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1912 .vreg_list = qmp_phy_vreg_l, 1913 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1914 .regs = qmp_v4_usb3phy_regs_layout, 1915 .pcs_usb_offset = 0x1000, 1916 1917 .has_pwrdn_delay = true, 1918 }; 1919 1920 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { 1921 .lanes = 2, 1922 1923 .serdes_tbl = qcm2290_usb3_serdes_tbl, 1924 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 1925 .tx_tbl = qcm2290_usb3_tx_tbl, 1926 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 1927 .rx_tbl = qcm2290_usb3_rx_tbl, 1928 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 1929 .pcs_tbl = qcm2290_usb3_pcs_tbl, 1930 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 1931 .clk_list = qcm2290_usb3phy_clk_l, 1932 .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), 1933 .reset_list = qcm2290_usb3phy_reset_l, 1934 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 1935 .vreg_list = qmp_phy_vreg_l, 1936 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1937 .regs = qcm2290_usb3phy_regs_layout, 1938 }; 1939 1940 static void qmp_usb_configure_lane(void __iomem *base, 1941 const struct qmp_phy_init_tbl tbl[], 1942 int num, 1943 u8 lane_mask) 1944 { 1945 int i; 1946 const struct qmp_phy_init_tbl *t = tbl; 1947 1948 if (!t) 1949 return; 1950 1951 for (i = 0; i < num; i++, t++) { 1952 if (!(t->lane_mask & lane_mask)) 1953 continue; 1954 1955 writel(t->val, base + t->offset); 1956 } 1957 } 1958 1959 static void qmp_usb_configure(void __iomem *base, 1960 const struct qmp_phy_init_tbl tbl[], 1961 int num) 1962 { 1963 qmp_usb_configure_lane(base, tbl, num, 0xff); 1964 } 1965 1966 static int qmp_usb_serdes_init(struct qmp_usb *qmp) 1967 { 1968 const struct qmp_phy_cfg *cfg = qmp->cfg; 1969 void __iomem *serdes = qmp->serdes; 1970 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1971 int serdes_tbl_num = cfg->serdes_tbl_num; 1972 1973 qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num); 1974 1975 return 0; 1976 } 1977 1978 static int qmp_usb_init(struct phy *phy) 1979 { 1980 struct qmp_usb *qmp = phy_get_drvdata(phy); 1981 const struct qmp_phy_cfg *cfg = qmp->cfg; 1982 void __iomem *pcs = qmp->pcs; 1983 void __iomem *dp_com = qmp->dp_com; 1984 int ret; 1985 1986 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1987 if (ret) { 1988 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1989 return ret; 1990 } 1991 1992 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1993 if (ret) { 1994 dev_err(qmp->dev, "reset assert failed\n"); 1995 goto err_disable_regulators; 1996 } 1997 1998 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 1999 if (ret) { 2000 dev_err(qmp->dev, "reset deassert failed\n"); 2001 goto err_disable_regulators; 2002 } 2003 2004 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2005 if (ret) 2006 goto err_assert_reset; 2007 2008 if (cfg->has_phy_dp_com_ctrl) { 2009 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, 2010 SW_PWRDN); 2011 /* override hardware control for reset of qmp phy */ 2012 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2013 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2014 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2015 2016 /* Default type-c orientation, i.e CC1 */ 2017 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 2018 2019 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, 2020 USB3_MODE | DP_MODE); 2021 2022 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 2023 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2024 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2025 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2026 2027 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 2028 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2029 } 2030 2031 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 2032 2033 return 0; 2034 2035 err_assert_reset: 2036 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2037 err_disable_regulators: 2038 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2039 2040 return ret; 2041 } 2042 2043 static int qmp_usb_exit(struct phy *phy) 2044 { 2045 struct qmp_usb *qmp = phy_get_drvdata(phy); 2046 const struct qmp_phy_cfg *cfg = qmp->cfg; 2047 2048 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2049 2050 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2051 2052 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2053 2054 return 0; 2055 } 2056 2057 static int qmp_usb_power_on(struct phy *phy) 2058 { 2059 struct qmp_usb *qmp = phy_get_drvdata(phy); 2060 const struct qmp_phy_cfg *cfg = qmp->cfg; 2061 void __iomem *tx = qmp->tx; 2062 void __iomem *rx = qmp->rx; 2063 void __iomem *pcs = qmp->pcs; 2064 void __iomem *status; 2065 unsigned int val; 2066 int ret; 2067 2068 qmp_usb_serdes_init(qmp); 2069 2070 ret = clk_prepare_enable(qmp->pipe_clk); 2071 if (ret) { 2072 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2073 return ret; 2074 } 2075 2076 /* Tx, Rx, and PCS configurations */ 2077 qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2078 qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2079 2080 if (cfg->lanes >= 2) { 2081 qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2082 qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2083 } 2084 2085 qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2086 2087 if (cfg->has_pwrdn_delay) 2088 usleep_range(10, 20); 2089 2090 /* Pull PHY out of reset state */ 2091 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2092 2093 /* start SerDes and Phy-Coding-Sublayer */ 2094 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2095 2096 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2097 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2098 PHY_INIT_COMPLETE_TIMEOUT); 2099 if (ret) { 2100 dev_err(qmp->dev, "phy initialization timed-out\n"); 2101 goto err_disable_pipe_clk; 2102 } 2103 2104 return 0; 2105 2106 err_disable_pipe_clk: 2107 clk_disable_unprepare(qmp->pipe_clk); 2108 2109 return ret; 2110 } 2111 2112 static int qmp_usb_power_off(struct phy *phy) 2113 { 2114 struct qmp_usb *qmp = phy_get_drvdata(phy); 2115 const struct qmp_phy_cfg *cfg = qmp->cfg; 2116 2117 clk_disable_unprepare(qmp->pipe_clk); 2118 2119 /* PHY reset */ 2120 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2121 2122 /* stop SerDes and Phy-Coding-Sublayer */ 2123 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2124 SERDES_START | PCS_START); 2125 2126 /* Put PHY into POWER DOWN state: active low */ 2127 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2128 SW_PWRDN); 2129 2130 return 0; 2131 } 2132 2133 static int qmp_usb_enable(struct phy *phy) 2134 { 2135 int ret; 2136 2137 ret = qmp_usb_init(phy); 2138 if (ret) 2139 return ret; 2140 2141 ret = qmp_usb_power_on(phy); 2142 if (ret) 2143 qmp_usb_exit(phy); 2144 2145 return ret; 2146 } 2147 2148 static int qmp_usb_disable(struct phy *phy) 2149 { 2150 int ret; 2151 2152 ret = qmp_usb_power_off(phy); 2153 if (ret) 2154 return ret; 2155 return qmp_usb_exit(phy); 2156 } 2157 2158 static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2159 { 2160 struct qmp_usb *qmp = phy_get_drvdata(phy); 2161 2162 qmp->mode = mode; 2163 2164 return 0; 2165 } 2166 2167 static const struct phy_ops qmp_usb_phy_ops = { 2168 .init = qmp_usb_enable, 2169 .exit = qmp_usb_disable, 2170 .set_mode = qmp_usb_set_mode, 2171 .owner = THIS_MODULE, 2172 }; 2173 2174 static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp) 2175 { 2176 const struct qmp_phy_cfg *cfg = qmp->cfg; 2177 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2178 void __iomem *pcs_misc = qmp->pcs_misc; 2179 u32 intr_mask; 2180 2181 if (qmp->mode == PHY_MODE_USB_HOST_SS || 2182 qmp->mode == PHY_MODE_USB_DEVICE_SS) 2183 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2184 else 2185 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2186 2187 /* Clear any pending interrupts status */ 2188 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2189 /* Writing 1 followed by 0 clears the interrupt */ 2190 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2191 2192 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2193 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2194 2195 /* Enable required PHY autonomous mode interrupts */ 2196 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2197 2198 /* Enable i/o clamp_n for autonomous mode */ 2199 if (pcs_misc) 2200 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2201 } 2202 2203 static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp) 2204 { 2205 const struct qmp_phy_cfg *cfg = qmp->cfg; 2206 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2207 void __iomem *pcs_misc = qmp->pcs_misc; 2208 2209 /* Disable i/o clamp_n on resume for normal mode */ 2210 if (pcs_misc) 2211 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2212 2213 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2214 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2215 2216 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2217 /* Writing 1 followed by 0 clears the interrupt */ 2218 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2219 } 2220 2221 static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev) 2222 { 2223 struct qmp_usb *qmp = dev_get_drvdata(dev); 2224 const struct qmp_phy_cfg *cfg = qmp->cfg; 2225 2226 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2227 2228 if (!qmp->phy->init_count) { 2229 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2230 return 0; 2231 } 2232 2233 qmp_usb_enable_autonomous_mode(qmp); 2234 2235 clk_disable_unprepare(qmp->pipe_clk); 2236 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2237 2238 return 0; 2239 } 2240 2241 static int __maybe_unused qmp_usb_runtime_resume(struct device *dev) 2242 { 2243 struct qmp_usb *qmp = dev_get_drvdata(dev); 2244 const struct qmp_phy_cfg *cfg = qmp->cfg; 2245 int ret = 0; 2246 2247 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2248 2249 if (!qmp->phy->init_count) { 2250 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2251 return 0; 2252 } 2253 2254 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2255 if (ret) 2256 return ret; 2257 2258 ret = clk_prepare_enable(qmp->pipe_clk); 2259 if (ret) { 2260 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2261 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2262 return ret; 2263 } 2264 2265 qmp_usb_disable_autonomous_mode(qmp); 2266 2267 return 0; 2268 } 2269 2270 static const struct dev_pm_ops qmp_usb_pm_ops = { 2271 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend, 2272 qmp_usb_runtime_resume, NULL) 2273 }; 2274 2275 static int qmp_usb_vreg_init(struct qmp_usb *qmp) 2276 { 2277 const struct qmp_phy_cfg *cfg = qmp->cfg; 2278 struct device *dev = qmp->dev; 2279 int num = cfg->num_vregs; 2280 int i; 2281 2282 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2283 if (!qmp->vregs) 2284 return -ENOMEM; 2285 2286 for (i = 0; i < num; i++) 2287 qmp->vregs[i].supply = cfg->vreg_list[i]; 2288 2289 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2290 } 2291 2292 static int qmp_usb_reset_init(struct qmp_usb *qmp) 2293 { 2294 const struct qmp_phy_cfg *cfg = qmp->cfg; 2295 struct device *dev = qmp->dev; 2296 int i; 2297 int ret; 2298 2299 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2300 sizeof(*qmp->resets), GFP_KERNEL); 2301 if (!qmp->resets) 2302 return -ENOMEM; 2303 2304 for (i = 0; i < cfg->num_resets; i++) 2305 qmp->resets[i].id = cfg->reset_list[i]; 2306 2307 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2308 if (ret) 2309 return dev_err_probe(dev, ret, "failed to get resets\n"); 2310 2311 return 0; 2312 } 2313 2314 static int qmp_usb_clk_init(struct qmp_usb *qmp) 2315 { 2316 const struct qmp_phy_cfg *cfg = qmp->cfg; 2317 struct device *dev = qmp->dev; 2318 int num = cfg->num_clks; 2319 int i; 2320 2321 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2322 if (!qmp->clks) 2323 return -ENOMEM; 2324 2325 for (i = 0; i < num; i++) 2326 qmp->clks[i].id = cfg->clk_list[i]; 2327 2328 return devm_clk_bulk_get(dev, num, qmp->clks); 2329 } 2330 2331 static void phy_clk_release_provider(void *res) 2332 { 2333 of_clk_del_provider(res); 2334 } 2335 2336 /* 2337 * Register a fixed rate pipe clock. 2338 * 2339 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2340 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2341 * by the PHY driver for its operations. 2342 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2343 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2344 * Below picture shows this relationship. 2345 * 2346 * +---------------+ 2347 * | PHY block |<<---------------------------------------+ 2348 * | | | 2349 * | +-------+ | +-----+ | 2350 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2351 * clk | +-------+ | +-----+ 2352 * +---------------+ 2353 */ 2354 static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np) 2355 { 2356 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2357 struct clk_init_data init = { }; 2358 int ret; 2359 2360 ret = of_property_read_string(np, "clock-output-names", &init.name); 2361 if (ret) { 2362 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2363 return ret; 2364 } 2365 2366 init.ops = &clk_fixed_rate_ops; 2367 2368 /* controllers using QMP phys use 125MHz pipe clock interface */ 2369 fixed->fixed_rate = 125000000; 2370 fixed->hw.init = &init; 2371 2372 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2373 if (ret) 2374 return ret; 2375 2376 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2377 if (ret) 2378 return ret; 2379 2380 /* 2381 * Roll a devm action because the clock provider is the child node, but 2382 * the child node is not actually a device. 2383 */ 2384 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2385 } 2386 2387 static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np, 2388 int index, bool exclusive) 2389 { 2390 struct resource res; 2391 2392 if (!exclusive) { 2393 if (of_address_to_resource(np, index, &res)) 2394 return IOMEM_ERR_PTR(-EINVAL); 2395 2396 return devm_ioremap(dev, res.start, resource_size(&res)); 2397 } 2398 2399 return devm_of_iomap(dev, np, index, NULL); 2400 } 2401 2402 static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np) 2403 { 2404 struct platform_device *pdev = to_platform_device(qmp->dev); 2405 const struct qmp_phy_cfg *cfg = qmp->cfg; 2406 struct device *dev = qmp->dev; 2407 bool exclusive = true; 2408 2409 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2410 if (IS_ERR(qmp->serdes)) 2411 return PTR_ERR(qmp->serdes); 2412 2413 if (cfg->has_phy_dp_com_ctrl) { 2414 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 2415 if (IS_ERR(qmp->dp_com)) 2416 return PTR_ERR(qmp->dp_com); 2417 } 2418 2419 /* 2420 * FIXME: These bindings should be fixed to not rely on overlapping 2421 * mappings for PCS. 2422 */ 2423 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy")) 2424 exclusive = false; 2425 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy")) 2426 exclusive = false; 2427 2428 /* 2429 * Get memory resources for the PHY: 2430 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2431 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2432 * For single lane PHYs: pcs_misc (optional) -> 3. 2433 */ 2434 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2435 if (IS_ERR(qmp->tx)) 2436 return PTR_ERR(qmp->tx); 2437 2438 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2439 if (IS_ERR(qmp->rx)) 2440 return PTR_ERR(qmp->rx); 2441 2442 qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive); 2443 if (IS_ERR(qmp->pcs)) 2444 return PTR_ERR(qmp->pcs); 2445 2446 if (cfg->pcs_usb_offset) 2447 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 2448 2449 if (cfg->lanes >= 2) { 2450 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2451 if (IS_ERR(qmp->tx2)) 2452 return PTR_ERR(qmp->tx2); 2453 2454 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2455 if (IS_ERR(qmp->rx2)) 2456 return PTR_ERR(qmp->rx2); 2457 2458 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2459 } else { 2460 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2461 } 2462 2463 if (IS_ERR(qmp->pcs_misc)) { 2464 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2465 qmp->pcs_misc = NULL; 2466 } 2467 2468 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2469 if (IS_ERR(qmp->pipe_clk)) { 2470 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2471 "failed to get pipe clock\n"); 2472 } 2473 2474 return 0; 2475 } 2476 2477 static int qmp_usb_parse_dt(struct qmp_usb *qmp) 2478 { 2479 struct platform_device *pdev = to_platform_device(qmp->dev); 2480 const struct qmp_phy_cfg *cfg = qmp->cfg; 2481 const struct qmp_usb_offsets *offs = cfg->offsets; 2482 struct device *dev = qmp->dev; 2483 void __iomem *base; 2484 2485 if (!offs) 2486 return -EINVAL; 2487 2488 base = devm_platform_ioremap_resource(pdev, 0); 2489 if (IS_ERR(base)) 2490 return PTR_ERR(base); 2491 2492 qmp->serdes = base + offs->serdes; 2493 qmp->pcs = base + offs->pcs; 2494 qmp->pcs_usb = base + offs->pcs_usb; 2495 qmp->tx = base + offs->tx; 2496 qmp->rx = base + offs->rx; 2497 2498 qmp->pipe_clk = devm_clk_get(dev, "pipe"); 2499 if (IS_ERR(qmp->pipe_clk)) { 2500 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2501 "failed to get pipe clock\n"); 2502 } 2503 2504 return 0; 2505 } 2506 2507 static int qmp_usb_probe(struct platform_device *pdev) 2508 { 2509 struct device *dev = &pdev->dev; 2510 struct phy_provider *phy_provider; 2511 struct device_node *np; 2512 struct qmp_usb *qmp; 2513 int ret; 2514 2515 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2516 if (!qmp) 2517 return -ENOMEM; 2518 2519 qmp->dev = dev; 2520 2521 qmp->cfg = of_device_get_match_data(dev); 2522 if (!qmp->cfg) 2523 return -EINVAL; 2524 2525 ret = qmp_usb_clk_init(qmp); 2526 if (ret) 2527 return ret; 2528 2529 ret = qmp_usb_reset_init(qmp); 2530 if (ret) 2531 return ret; 2532 2533 ret = qmp_usb_vreg_init(qmp); 2534 if (ret) 2535 return ret; 2536 2537 /* Check for legacy binding with child node. */ 2538 np = of_get_next_available_child(dev->of_node, NULL); 2539 if (np) { 2540 ret = qmp_usb_parse_dt_legacy(qmp, np); 2541 } else { 2542 np = of_node_get(dev->of_node); 2543 ret = qmp_usb_parse_dt(qmp); 2544 } 2545 if (ret) 2546 goto err_node_put; 2547 2548 pm_runtime_set_active(dev); 2549 ret = devm_pm_runtime_enable(dev); 2550 if (ret) 2551 goto err_node_put; 2552 /* 2553 * Prevent runtime pm from being ON by default. Users can enable 2554 * it using power/control in sysfs. 2555 */ 2556 pm_runtime_forbid(dev); 2557 2558 ret = phy_pipe_clk_register(qmp, np); 2559 if (ret) 2560 goto err_node_put; 2561 2562 qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops); 2563 if (IS_ERR(qmp->phy)) { 2564 ret = PTR_ERR(qmp->phy); 2565 dev_err(dev, "failed to create PHY: %d\n", ret); 2566 goto err_node_put; 2567 } 2568 2569 phy_set_drvdata(qmp->phy, qmp); 2570 2571 of_node_put(np); 2572 2573 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2574 2575 return PTR_ERR_OR_ZERO(phy_provider); 2576 2577 err_node_put: 2578 of_node_put(np); 2579 return ret; 2580 } 2581 2582 static const struct of_device_id qmp_usb_of_match_table[] = { 2583 { 2584 .compatible = "qcom,ipq6018-qmp-usb3-phy", 2585 .data = &ipq8074_usb3phy_cfg, 2586 }, { 2587 .compatible = "qcom,ipq8074-qmp-usb3-phy", 2588 .data = &ipq8074_usb3phy_cfg, 2589 }, { 2590 .compatible = "qcom,msm8996-qmp-usb3-phy", 2591 .data = &msm8996_usb3phy_cfg, 2592 }, { 2593 .compatible = "qcom,msm8998-qmp-usb3-phy", 2594 .data = &msm8998_usb3phy_cfg, 2595 }, { 2596 .compatible = "qcom,qcm2290-qmp-usb3-phy", 2597 .data = &qcm2290_usb3phy_cfg, 2598 }, { 2599 .compatible = "qcom,sc7180-qmp-usb3-phy", 2600 .data = &sc7180_usb3phy_cfg, 2601 }, { 2602 .compatible = "qcom,sc8180x-qmp-usb3-phy", 2603 .data = &sm8150_usb3phy_cfg, 2604 }, { 2605 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy", 2606 .data = &sc8280xp_usb3_uniphy_cfg, 2607 }, { 2608 .compatible = "qcom,sdm845-qmp-usb3-phy", 2609 .data = &qmp_v3_usb3phy_cfg, 2610 }, { 2611 .compatible = "qcom,sdm845-qmp-usb3-uni-phy", 2612 .data = &qmp_v3_usb3_uniphy_cfg, 2613 }, { 2614 .compatible = "qcom,sdx55-qmp-usb3-uni-phy", 2615 .data = &sdx55_usb3_uniphy_cfg, 2616 }, { 2617 .compatible = "qcom,sdx65-qmp-usb3-uni-phy", 2618 .data = &sdx65_usb3_uniphy_cfg, 2619 }, { 2620 .compatible = "qcom,sm8150-qmp-usb3-phy", 2621 .data = &sm8150_usb3phy_cfg, 2622 }, { 2623 .compatible = "qcom,sm8150-qmp-usb3-uni-phy", 2624 .data = &sm8150_usb3_uniphy_cfg, 2625 }, { 2626 .compatible = "qcom,sm8250-qmp-usb3-phy", 2627 .data = &sm8250_usb3phy_cfg, 2628 }, { 2629 .compatible = "qcom,sm8250-qmp-usb3-uni-phy", 2630 .data = &sm8250_usb3_uniphy_cfg, 2631 }, { 2632 .compatible = "qcom,sm8350-qmp-usb3-phy", 2633 .data = &sm8350_usb3phy_cfg, 2634 }, { 2635 .compatible = "qcom,sm8350-qmp-usb3-uni-phy", 2636 .data = &sm8350_usb3_uniphy_cfg, 2637 }, { 2638 .compatible = "qcom,sm8450-qmp-usb3-phy", 2639 .data = &sm8350_usb3phy_cfg, 2640 }, 2641 { }, 2642 }; 2643 MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table); 2644 2645 static struct platform_driver qmp_usb_driver = { 2646 .probe = qmp_usb_probe, 2647 .driver = { 2648 .name = "qcom-qmp-usb-phy", 2649 .pm = &qmp_usb_pm_ops, 2650 .of_match_table = qmp_usb_of_match_table, 2651 }, 2652 }; 2653 2654 module_platform_driver(qmp_usb_driver); 2655 2656 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2657 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver"); 2658 MODULE_LICENSE("GPL v2"); 2659