1 // SPDX-License-Identifier: GPL-2.0
2 /*
3  * Copyright (c) 2017, The Linux Foundation. All rights reserved.
4  */
5 
6 #include <linux/clk.h>
7 #include <linux/clk-provider.h>
8 #include <linux/delay.h>
9 #include <linux/err.h>
10 #include <linux/io.h>
11 #include <linux/iopoll.h>
12 #include <linux/kernel.h>
13 #include <linux/module.h>
14 #include <linux/of.h>
15 #include <linux/of_address.h>
16 #include <linux/phy/phy.h>
17 #include <linux/platform_device.h>
18 #include <linux/regulator/consumer.h>
19 #include <linux/reset.h>
20 #include <linux/slab.h>
21 
22 #include "phy-qcom-qmp.h"
23 #include "phy-qcom-qmp-pcs-misc-v3.h"
24 #include "phy-qcom-qmp-pcs-usb-v4.h"
25 #include "phy-qcom-qmp-pcs-usb-v5.h"
26 
27 /* QPHY_SW_RESET bit */
28 #define SW_RESET				BIT(0)
29 /* QPHY_POWER_DOWN_CONTROL */
30 #define SW_PWRDN				BIT(0)
31 /* QPHY_START_CONTROL bits */
32 #define SERDES_START				BIT(0)
33 #define PCS_START				BIT(1)
34 /* QPHY_PCS_STATUS bit */
35 #define PHYSTATUS				BIT(6)
36 
37 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */
38 /* DP PHY soft reset */
39 #define SW_DPPHY_RESET				BIT(0)
40 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */
41 #define SW_DPPHY_RESET_MUX			BIT(1)
42 /* USB3 PHY soft reset */
43 #define SW_USB3PHY_RESET			BIT(2)
44 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */
45 #define SW_USB3PHY_RESET_MUX			BIT(3)
46 
47 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */
48 #define USB3_MODE				BIT(0) /* enables USB3 mode */
49 #define DP_MODE					BIT(1) /* enables DP mode */
50 
51 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */
52 #define ARCVR_DTCT_EN				BIT(0)
53 #define ALFPS_DTCT_EN				BIT(1)
54 #define ARCVR_DTCT_EVENT_SEL			BIT(4)
55 
56 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */
57 #define IRQ_CLEAR				BIT(0)
58 
59 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */
60 #define CLAMP_EN				BIT(0) /* enables i/o clamp_n */
61 
62 #define PHY_INIT_COMPLETE_TIMEOUT		10000
63 
64 struct qmp_phy_init_tbl {
65 	unsigned int offset;
66 	unsigned int val;
67 	/*
68 	 * mask of lanes for which this register is written
69 	 * for cases when second lane needs different values
70 	 */
71 	u8 lane_mask;
72 };
73 
74 #define QMP_PHY_INIT_CFG(o, v)		\
75 	{				\
76 		.offset = o,		\
77 		.val = v,		\
78 		.lane_mask = 0xff,	\
79 	}
80 
81 #define QMP_PHY_INIT_CFG_LANE(o, v, l)	\
82 	{				\
83 		.offset = o,		\
84 		.val = v,		\
85 		.lane_mask = l,		\
86 	}
87 
88 /* set of registers with offsets different per-PHY */
89 enum qphy_reg_layout {
90 	/* PCS registers */
91 	QPHY_SW_RESET,
92 	QPHY_START_CTRL,
93 	QPHY_PCS_STATUS,
94 	QPHY_PCS_AUTONOMOUS_MODE_CTRL,
95 	QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR,
96 	QPHY_PCS_POWER_DOWN_CONTROL,
97 	/* Keep last to ensure regs_layout arrays are properly initialized */
98 	QPHY_LAYOUT_SIZE
99 };
100 
101 static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
102 	[QPHY_SW_RESET]			= QPHY_V2_PCS_SW_RESET,
103 	[QPHY_START_CTRL]		= QPHY_V2_PCS_START_CONTROL,
104 	[QPHY_PCS_STATUS]		= QPHY_V2_PCS_USB_PCS_STATUS,
105 	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL,
106 	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR,
107 	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V2_PCS_POWER_DOWN_CONTROL,
108 };
109 
110 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
111 	[QPHY_SW_RESET]			= QPHY_V3_PCS_SW_RESET,
112 	[QPHY_START_CTRL]		= QPHY_V3_PCS_START_CONTROL,
113 	[QPHY_PCS_STATUS]		= QPHY_V3_PCS_PCS_STATUS,
114 	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL,
115 	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR,
116 	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V3_PCS_POWER_DOWN_CONTROL,
117 };
118 
119 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
120 	[QPHY_SW_RESET]			= QPHY_V4_PCS_SW_RESET,
121 	[QPHY_START_CTRL]		= QPHY_V4_PCS_START_CONTROL,
122 	[QPHY_PCS_STATUS]		= QPHY_V4_PCS_PCS_STATUS1,
123 	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V4_PCS_POWER_DOWN_CONTROL,
124 
125 	/* In PCS_USB */
126 	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL,
127 	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
128 };
129 
130 static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = {
131 	[QPHY_SW_RESET]			= QPHY_V5_PCS_SW_RESET,
132 	[QPHY_START_CTRL]		= QPHY_V5_PCS_START_CONTROL,
133 	[QPHY_PCS_STATUS]		= QPHY_V5_PCS_PCS_STATUS1,
134 	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V5_PCS_POWER_DOWN_CONTROL,
135 
136 	/* In PCS_USB */
137 	[QPHY_PCS_AUTONOMOUS_MODE_CTRL]	= QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL,
138 	[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR,
139 };
140 
141 static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = {
142 	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
143 	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
144 	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
145 	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
146 	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
147 	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
148 	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
149 	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
150 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
151 	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
152 	/* PLL and Loop filter settings */
153 	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68),
154 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab),
155 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa),
156 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02),
157 	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09),
158 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
159 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
160 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0),
161 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa),
162 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29),
163 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
164 	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
165 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
166 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
167 	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
168 	/* SSC settings */
169 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
170 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d),
171 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
172 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
173 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
174 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a),
175 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05),
176 };
177 
178 static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = {
179 	QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
180 	QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
181 	QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
182 };
183 
184 static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = {
185 	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
186 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
187 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c),
188 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
189 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
190 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
191 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
192 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
193 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
194 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c),
195 };
196 
197 static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = {
198 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
199 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
200 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
201 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
202 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
203 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
204 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
205 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
206 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
207 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
208 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
209 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
210 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
211 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
212 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
213 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
214 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
215 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
216 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
217 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
218 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
219 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
220 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
221 };
222 
223 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = {
224 	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a),
225 	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
226 	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
227 	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
228 	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
229 	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
230 	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
231 	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
232 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
233 	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
234 	/* PLL and Loop filter settings */
235 	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
236 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
237 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
238 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
239 	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
240 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
241 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
242 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
243 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
244 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
245 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
246 	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
247 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
248 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
249 	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
250 	/* SSC settings */
251 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
252 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
253 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
254 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
255 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
256 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
257 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
258 };
259 
260 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = {
261 	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06),
262 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
263 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
264 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8),
265 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
266 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
267 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
268 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
269 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0),
270 };
271 
272 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = {
273 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
274 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e),
275 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
276 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
277 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
278 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
279 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
280 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
281 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
282 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
283 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
284 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
285 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
286 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
287 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
288 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
289 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
290 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
291 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
292 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
293 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
294 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
295 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
296 };
297 
298 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = {
299 	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
300 	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
301 	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
302 	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
303 	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
304 	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
305 	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
306 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
307 	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04),
308 	/* PLL and Loop filter settings */
309 	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
310 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
311 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
312 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
313 	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
314 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
315 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
316 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
317 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00),
318 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
319 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
320 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
321 	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
322 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
323 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
324 	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
325 	/* SSC settings */
326 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
327 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
328 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
329 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
330 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
331 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
332 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
333 };
334 
335 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = {
336 	QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45),
337 	QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12),
338 	QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06),
339 };
340 
341 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = {
342 	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
343 	QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04),
344 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
345 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c),
346 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb),
347 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
348 	QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
349 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03),
350 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18),
351 	QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
352 };
353 
354 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = {
355 	/* FLL settings */
356 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03),
357 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02),
358 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09),
359 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42),
360 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85),
361 
362 	/* Lock Det settings */
363 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1),
364 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f),
365 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47),
366 	QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08),
367 };
368 
369 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = {
370 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
371 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
372 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
373 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
374 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02),
375 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
376 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
377 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
378 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
379 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
380 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
381 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
382 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
383 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
384 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
385 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
386 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
387 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
388 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
389 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
390 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
391 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
392 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
393 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
394 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
395 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
396 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
397 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
398 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a),
399 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
400 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
401 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
402 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
403 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
404 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
405 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
406 };
407 
408 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = {
409 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
410 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
411 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
412 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06),
413 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06),
414 };
415 
416 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = {
417 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c),
418 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50),
419 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
420 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e),
421 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
422 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
423 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
424 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
425 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
426 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
427 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
428 };
429 
430 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = {
431 	/* FLL settings */
432 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
433 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
434 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
435 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
436 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
437 
438 	/* Lock Det settings */
439 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
440 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
441 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
442 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
443 
444 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba),
445 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
446 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
447 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5),
448 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c),
449 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64),
450 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a),
451 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
452 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
453 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
454 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
455 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
456 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
457 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
458 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d),
459 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
460 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
461 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
462 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
463 
464 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
465 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
466 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
467 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
468 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
469 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
470 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
471 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
472 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
473 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
474 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
475 
476 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21),
477 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60),
478 };
479 
480 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = {
481 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
482 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04),
483 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14),
484 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06),
485 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08),
486 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06),
487 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01),
488 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80),
489 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82),
490 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab),
491 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea),
492 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02),
493 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06),
494 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16),
495 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36),
496 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
497 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f),
498 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01),
499 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9),
500 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a),
501 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00),
502 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34),
503 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15),
504 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04),
505 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00),
506 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00),
507 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00),
508 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a),
509 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07),
510 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80),
511 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01),
512 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01),
513 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31),
514 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01),
515 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00),
516 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00),
517 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85),
518 	QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07),
519 };
520 
521 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = {
522 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
523 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
524 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16),
525 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
526 };
527 
528 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = {
529 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
530 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
531 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
532 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
533 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07),
534 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
535 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43),
536 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c),
537 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
538 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
539 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
540 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
541 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
542 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
543 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
544 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03),
545 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05),
546 };
547 
548 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = {
549 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
550 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
551 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
552 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40),
553 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
554 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
555 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
556 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
557 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b),
558 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
559 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f),
560 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7),
561 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e),
562 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65),
563 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b),
564 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15),
565 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d),
566 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15),
567 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d),
568 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15),
569 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d),
570 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15),
571 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d),
572 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15),
573 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d),
574 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15),
575 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d),
576 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02),
577 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
578 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
579 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
580 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
581 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
582 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
583 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a),
584 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
585 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
586 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
587 };
588 
589 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = {
590 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a),
591 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
592 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01),
593 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82),
594 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab),
595 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea),
596 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02),
597 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
598 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
599 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06),
600 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16),
601 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36),
602 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24),
603 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34),
604 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14),
605 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04),
606 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a),
607 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02),
608 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24),
609 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08),
610 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82),
611 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab),
612 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea),
613 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02),
614 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82),
615 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34),
616 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06),
617 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16),
618 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36),
619 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
620 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
621 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20),
622 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01),
623 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31),
624 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01),
625 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde),
626 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07),
627 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde),
628 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07),
629 	QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02),
630 };
631 
632 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = {
633 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
634 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95),
635 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
636 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05),
637 };
638 
639 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = {
640 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
641 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
642 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37),
643 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f),
644 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef),
645 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3),
646 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b),
647 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
648 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
649 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
650 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
651 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
652 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
653 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
654 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
655 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
656 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
657 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
658 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
659 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08),
660 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
661 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
662 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
663 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
664 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
665 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
666 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
667 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
668 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
669 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
670 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
671 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
672 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
673 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20),
674 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04),
675 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
676 };
677 
678 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = {
679 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
680 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
681 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
682 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
683 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
684 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
685 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
686 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f),
687 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
688 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
689 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
690 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
691 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
692 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
693 };
694 
695 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = {
696 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
697 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
698 };
699 
700 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = {
701 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
702 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
703 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82),
704 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40),
705 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11),
706 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02),
707 };
708 
709 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = {
710 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8),
711 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff),
712 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
713 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
714 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
715 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
716 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
717 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
718 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
719 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
720 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
721 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04),
722 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
723 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05),
724 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05),
725 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
726 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
727 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
728 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
729 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a),
730 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
731 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
732 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
733 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
734 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
735 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
736 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
737 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
738 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
739 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
740 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
741 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
742 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
743 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06),
744 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
745 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
746 };
747 
748 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = {
749 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
750 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
751 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
752 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
753 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
754 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
755 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9),
756 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
757 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
758 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
759 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
760 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
761 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
762 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
763 };
764 
765 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = {
766 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
767 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
768 };
769 
770 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = {
771 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12),
772 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5),
773 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80),
774 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20),
775 	QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08),
776 };
777 
778 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = {
779 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26),
780 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f),
781 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf),
782 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f),
783 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f),
784 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4),
785 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b),
786 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c),
787 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc),
788 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc),
789 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99),
790 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048),
791 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08),
792 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00),
793 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04),
794 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
795 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
796 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
797 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f),
798 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09),
799 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54),
800 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c),
801 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
802 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a),
803 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
804 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04),
805 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
806 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
807 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04),
808 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
809 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00),
810 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0),
811 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
812 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05),
813 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c),
814 	QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f),
815 };
816 
817 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = {
818 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
819 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
820 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
821 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
822 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
823 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f),
824 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b),
825 };
826 
827 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = {
828 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb),
829 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
830 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
831 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
832 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
833 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
834 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
835 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
836 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
837 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
838 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
839 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
840 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
841 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
842 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
843 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
844 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
845 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
846 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
847 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
848 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
849 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
850 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
851 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
852 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
853 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
854 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
855 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
856 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
857 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
858 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
859 };
860 
861 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = {
862 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
863 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
864 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
865 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
866 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
867 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
868 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
869 };
870 
871 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = {
872 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
873 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
874 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
875 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
876 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
877 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
878 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
879 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
880 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
881 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
882 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
883 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
884 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
885 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
886 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
887 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
888 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
889 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
890 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a),
891 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
892 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
893 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
894 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
895 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
896 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
897 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
898 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
899 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
900 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
901 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
902 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
903 };
904 
905 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = {
906 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0),
907 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07),
908 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20),
909 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13),
910 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
911 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
912 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa),
913 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c),
914 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a),
915 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88),
916 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13),
917 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b),
918 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10),
919 	QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21),
920 };
921 
922 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = {
923 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
924 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
925 };
926 
927 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = {
928 	QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14),
929 	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08),
930 	QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30),
931 	QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06),
932 	QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00),
933 	QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08),
934 	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f),
935 	QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01),
936 	QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00),
937 	QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82),
938 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55),
939 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55),
940 	QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03),
941 	QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b),
942 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16),
943 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28),
944 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80),
945 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00),
946 	QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a),
947 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15),
948 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34),
949 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00),
950 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00),
951 	QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00),
952 	QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00),
953 	QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00),
954 	QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a),
955 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01),
956 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31),
957 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01),
958 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00),
959 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00),
960 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde),
961 	QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07),
962 	QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f),
963 	QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06),
964 	QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80),
965 	QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01),
966 };
967 
968 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = {
969 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10),
970 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12),
971 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6),
972 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00),
973 	QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00),
974 };
975 
976 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = {
977 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b),
978 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80),
979 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00),
980 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00),
981 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a),
982 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06),
983 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75),
984 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02),
985 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e),
986 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18),
987 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77),
988 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
989 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a),
990 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03),
991 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16),
992 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00),
993 	QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00),
994 };
995 
996 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = {
997 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f),
998 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17),
999 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f),
1000 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83),
1001 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02),
1002 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09),
1003 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2),
1004 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85),
1005 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1),
1006 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f),
1007 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47),
1008 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75),
1009 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13),
1010 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86),
1011 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04),
1012 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44),
1013 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1014 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1015 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40),
1016 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00),
1017 	QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88),
1018 };
1019 
1020 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = {
1021 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a),
1022 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11),
1023 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01),
1024 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82),
1025 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab),
1026 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea),
1027 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02),
1028 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca),
1029 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e),
1030 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06),
1031 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16),
1032 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36),
1033 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24),
1034 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34),
1035 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14),
1036 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04),
1037 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a),
1038 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02),
1039 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24),
1040 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08),
1041 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82),
1042 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab),
1043 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea),
1044 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02),
1045 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82),
1046 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34),
1047 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06),
1048 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16),
1049 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36),
1050 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca),
1051 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e),
1052 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01),
1053 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31),
1054 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01),
1055 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde),
1056 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07),
1057 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde),
1058 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07),
1059 	QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02),
1060 };
1061 
1062 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = {
1063 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5),
1064 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82),
1065 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f),
1066 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f),
1067 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21),
1068 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10),
1069 	QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e),
1070 };
1071 
1072 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = {
1073 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc),
1074 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd),
1075 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff),
1076 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f),
1077 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff),
1078 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9),
1079 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b),
1080 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4),
1081 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24),
1082 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64),
1083 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99),
1084 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08),
1085 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08),
1086 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00),
1087 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04),
1088 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f),
1089 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff),
1090 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f),
1091 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a),
1092 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54),
1093 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f),
1094 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f),
1095 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a),
1096 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47),
1097 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80),
1098 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04),
1099 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e),
1100 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38),
1101 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05),
1102 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00),
1103 	QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00),
1104 };
1105 
1106 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = {
1107 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0),
1108 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07),
1109 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1110 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1111 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1112 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1113 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1114 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1115 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1116 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1117 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1118 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1119 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1120 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1121 };
1122 
1123 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_usb_tbl[] = {
1124 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1125 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1126 };
1127 
1128 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = {
1129 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4),
1130 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89),
1131 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20),
1132 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13),
1133 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7),
1134 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03),
1135 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa),
1136 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c),
1137 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a),
1138 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88),
1139 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13),
1140 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b),
1141 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10),
1142 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21),
1143 };
1144 
1145 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_usb_tbl[] = {
1146 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07),
1147 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8),
1148 	QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f),
1149 };
1150 
1151 struct qmp_usb_offsets {
1152 	u16 serdes;
1153 	u16 pcs;
1154 	u16 pcs_misc;
1155 	u16 pcs_usb;
1156 	u16 tx;
1157 	u16 rx;
1158 	/* for PHYs with >= 2 lanes */
1159 	u16 tx2;
1160 	u16 rx2;
1161 };
1162 
1163 /* struct qmp_phy_cfg - per-PHY initialization config */
1164 struct qmp_phy_cfg {
1165 	int lanes;
1166 
1167 	const struct qmp_usb_offsets *offsets;
1168 
1169 	/* Init sequence for PHY blocks - serdes, tx, rx, pcs */
1170 	const struct qmp_phy_init_tbl *serdes_tbl;
1171 	int serdes_tbl_num;
1172 	const struct qmp_phy_init_tbl *tx_tbl;
1173 	int tx_tbl_num;
1174 	const struct qmp_phy_init_tbl *rx_tbl;
1175 	int rx_tbl_num;
1176 	const struct qmp_phy_init_tbl *pcs_tbl;
1177 	int pcs_tbl_num;
1178 	const struct qmp_phy_init_tbl *pcs_usb_tbl;
1179 	int pcs_usb_tbl_num;
1180 
1181 	/* clock ids to be requested */
1182 	const char * const *clk_list;
1183 	int num_clks;
1184 	/* resets to be requested */
1185 	const char * const *reset_list;
1186 	int num_resets;
1187 	/* regulators to be requested */
1188 	const char * const *vreg_list;
1189 	int num_vregs;
1190 
1191 	/* array of registers with different offsets */
1192 	const unsigned int *regs;
1193 
1194 	/* true, if PHY needs delay after POWER_DOWN */
1195 	bool has_pwrdn_delay;
1196 
1197 	/* Offset from PCS to PCS_USB region */
1198 	unsigned int pcs_usb_offset;
1199 };
1200 
1201 struct qmp_usb {
1202 	struct device *dev;
1203 
1204 	const struct qmp_phy_cfg *cfg;
1205 
1206 	void __iomem *serdes;
1207 	void __iomem *pcs;
1208 	void __iomem *pcs_misc;
1209 	void __iomem *pcs_usb;
1210 	void __iomem *tx;
1211 	void __iomem *rx;
1212 	void __iomem *tx2;
1213 	void __iomem *rx2;
1214 
1215 	struct clk *pipe_clk;
1216 	struct clk_bulk_data *clks;
1217 	struct reset_control_bulk_data *resets;
1218 	struct regulator_bulk_data *vregs;
1219 
1220 	enum phy_mode mode;
1221 
1222 	struct phy *phy;
1223 
1224 	struct clk_fixed_rate pipe_clk_fixed;
1225 };
1226 
1227 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val)
1228 {
1229 	u32 reg;
1230 
1231 	reg = readl(base + offset);
1232 	reg |= val;
1233 	writel(reg, base + offset);
1234 
1235 	/* ensure that above write is through */
1236 	readl(base + offset);
1237 }
1238 
1239 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val)
1240 {
1241 	u32 reg;
1242 
1243 	reg = readl(base + offset);
1244 	reg &= ~val;
1245 	writel(reg, base + offset);
1246 
1247 	/* ensure that above write is through */
1248 	readl(base + offset);
1249 }
1250 
1251 /* list of clocks required by phy */
1252 static const char * const msm8996_phy_clk_l[] = {
1253 	"aux", "cfg_ahb", "ref",
1254 };
1255 
1256 static const char * const qmp_v3_phy_clk_l[] = {
1257 	"aux", "cfg_ahb", "ref", "com_aux",
1258 };
1259 
1260 static const char * const qmp_v4_phy_clk_l[] = {
1261 	"aux", "ref", "com_aux",
1262 };
1263 
1264 static const char * const qmp_v4_ref_phy_clk_l[] = {
1265 	"aux", "ref_clk_src", "ref", "com_aux",
1266 };
1267 
1268 /* usb3 phy on sdx55 doesn't have com_aux clock */
1269 static const char * const qmp_v4_sdx55_usbphy_clk_l[] = {
1270 	"aux", "cfg_ahb", "ref"
1271 };
1272 
1273 static const char * const qcm2290_usb3phy_clk_l[] = {
1274 	"cfg_ahb", "ref", "com_aux",
1275 };
1276 
1277 /* list of resets */
1278 static const char * const msm8996_usb3phy_reset_l[] = {
1279 	"phy", "common",
1280 };
1281 
1282 static const char * const qcm2290_usb3phy_reset_l[] = {
1283 	"phy_phy", "phy",
1284 };
1285 
1286 /* list of regulators */
1287 static const char * const qmp_phy_vreg_l[] = {
1288 	"vdda-phy", "vdda-pll",
1289 };
1290 
1291 static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = {
1292 	.serdes		= 0,
1293 	.pcs		= 0x800,
1294 	.pcs_usb	= 0x800,
1295 	.tx		= 0x200,
1296 	.rx		= 0x400,
1297 };
1298 
1299 static const struct qmp_usb_offsets qmp_usb_offsets_v3 = {
1300 	.serdes		= 0,
1301 	.pcs		= 0xc00,
1302 	.pcs_misc	= 0xa00,
1303 	.tx		= 0x200,
1304 	.rx		= 0x400,
1305 	.tx2		= 0x600,
1306 	.rx2		= 0x800,
1307 };
1308 
1309 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = {
1310 	.serdes		= 0,
1311 	.pcs		= 0x0200,
1312 	.pcs_usb	= 0x1200,
1313 	.tx		= 0x0e00,
1314 	.rx		= 0x1000,
1315 };
1316 
1317 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = {
1318 	.lanes			= 1,
1319 
1320 	.serdes_tbl		= ipq8074_usb3_serdes_tbl,
1321 	.serdes_tbl_num		= ARRAY_SIZE(ipq8074_usb3_serdes_tbl),
1322 	.tx_tbl			= msm8996_usb3_tx_tbl,
1323 	.tx_tbl_num		= ARRAY_SIZE(msm8996_usb3_tx_tbl),
1324 	.rx_tbl			= ipq8074_usb3_rx_tbl,
1325 	.rx_tbl_num		= ARRAY_SIZE(ipq8074_usb3_rx_tbl),
1326 	.pcs_tbl		= ipq8074_usb3_pcs_tbl,
1327 	.pcs_tbl_num		= ARRAY_SIZE(ipq8074_usb3_pcs_tbl),
1328 	.clk_list		= msm8996_phy_clk_l,
1329 	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),
1330 	.reset_list		= msm8996_usb3phy_reset_l,
1331 	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
1332 	.vreg_list		= qmp_phy_vreg_l,
1333 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1334 	.regs			= qmp_v3_usb3phy_regs_layout,
1335 };
1336 
1337 static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = {
1338 	.lanes			= 1,
1339 
1340 	.offsets		= &qmp_usb_offsets_ipq9574,
1341 
1342 	.serdes_tbl		= ipq9574_usb3_serdes_tbl,
1343 	.serdes_tbl_num		= ARRAY_SIZE(ipq9574_usb3_serdes_tbl),
1344 	.tx_tbl			= ipq9574_usb3_tx_tbl,
1345 	.tx_tbl_num		= ARRAY_SIZE(ipq9574_usb3_tx_tbl),
1346 	.rx_tbl			= ipq9574_usb3_rx_tbl,
1347 	.rx_tbl_num		= ARRAY_SIZE(ipq9574_usb3_rx_tbl),
1348 	.pcs_tbl		= ipq9574_usb3_pcs_tbl,
1349 	.pcs_tbl_num		= ARRAY_SIZE(ipq9574_usb3_pcs_tbl),
1350 	.clk_list		= msm8996_phy_clk_l,
1351 	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),
1352 	.reset_list		= qcm2290_usb3phy_reset_l,
1353 	.num_resets		= ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1354 	.vreg_list		= qmp_phy_vreg_l,
1355 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1356 	.regs			= qmp_v3_usb3phy_regs_layout,
1357 };
1358 
1359 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = {
1360 	.lanes			= 1,
1361 
1362 	.serdes_tbl		= msm8996_usb3_serdes_tbl,
1363 	.serdes_tbl_num		= ARRAY_SIZE(msm8996_usb3_serdes_tbl),
1364 	.tx_tbl			= msm8996_usb3_tx_tbl,
1365 	.tx_tbl_num		= ARRAY_SIZE(msm8996_usb3_tx_tbl),
1366 	.rx_tbl			= msm8996_usb3_rx_tbl,
1367 	.rx_tbl_num		= ARRAY_SIZE(msm8996_usb3_rx_tbl),
1368 	.pcs_tbl		= msm8996_usb3_pcs_tbl,
1369 	.pcs_tbl_num		= ARRAY_SIZE(msm8996_usb3_pcs_tbl),
1370 	.clk_list		= msm8996_phy_clk_l,
1371 	.num_clks		= ARRAY_SIZE(msm8996_phy_clk_l),
1372 	.reset_list		= msm8996_usb3phy_reset_l,
1373 	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
1374 	.vreg_list		= qmp_phy_vreg_l,
1375 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1376 	.regs			= qmp_v2_usb3phy_regs_layout,
1377 };
1378 
1379 static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = {
1380 	.lanes			= 1,
1381 
1382 	.offsets		= &qmp_usb_offsets_v5,
1383 
1384 	.serdes_tbl		= sc8280xp_usb3_uniphy_serdes_tbl,
1385 	.serdes_tbl_num		= ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1386 	.tx_tbl			= sc8280xp_usb3_uniphy_tx_tbl,
1387 	.tx_tbl_num		= ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1388 	.rx_tbl			= sc8280xp_usb3_uniphy_rx_tbl,
1389 	.rx_tbl_num		= ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1390 	.pcs_tbl		= sa8775p_usb3_uniphy_pcs_tbl,
1391 	.pcs_tbl_num		= ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl),
1392 	.pcs_usb_tbl		= sa8775p_usb3_uniphy_pcs_usb_tbl,
1393 	.pcs_usb_tbl_num	= ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_usb_tbl),
1394 	.clk_list		= qmp_v4_phy_clk_l,
1395 	.num_clks		= ARRAY_SIZE(qmp_v4_phy_clk_l),
1396 	.reset_list		= qcm2290_usb3phy_reset_l,
1397 	.num_resets		= ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1398 	.vreg_list		= qmp_phy_vreg_l,
1399 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1400 	.regs			= qmp_v5_usb3phy_regs_layout,
1401 };
1402 
1403 static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = {
1404 	.lanes			= 1,
1405 
1406 	.offsets		= &qmp_usb_offsets_v5,
1407 
1408 	.serdes_tbl		= sc8280xp_usb3_uniphy_serdes_tbl,
1409 	.serdes_tbl_num		= ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl),
1410 	.tx_tbl			= sc8280xp_usb3_uniphy_tx_tbl,
1411 	.tx_tbl_num		= ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl),
1412 	.rx_tbl			= sc8280xp_usb3_uniphy_rx_tbl,
1413 	.rx_tbl_num		= ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl),
1414 	.pcs_tbl		= sc8280xp_usb3_uniphy_pcs_tbl,
1415 	.pcs_tbl_num		= ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl),
1416 	.pcs_usb_tbl		= sc8280xp_usb3_uniphy_pcs_usb_tbl,
1417 	.pcs_usb_tbl_num	= ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_usb_tbl),
1418 	.clk_list		= qmp_v4_phy_clk_l,
1419 	.num_clks		= ARRAY_SIZE(qmp_v4_phy_clk_l),
1420 	.reset_list		= qcm2290_usb3phy_reset_l,
1421 	.num_resets		= ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1422 	.vreg_list		= qmp_phy_vreg_l,
1423 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1424 	.regs			= qmp_v5_usb3phy_regs_layout,
1425 };
1426 
1427 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = {
1428 	.lanes			= 1,
1429 
1430 	.serdes_tbl		= qmp_v3_usb3_uniphy_serdes_tbl,
1431 	.serdes_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl),
1432 	.tx_tbl			= qmp_v3_usb3_uniphy_tx_tbl,
1433 	.tx_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl),
1434 	.rx_tbl			= qmp_v3_usb3_uniphy_rx_tbl,
1435 	.rx_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl),
1436 	.pcs_tbl		= qmp_v3_usb3_uniphy_pcs_tbl,
1437 	.pcs_tbl_num		= ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl),
1438 	.clk_list		= qmp_v3_phy_clk_l,
1439 	.num_clks		= ARRAY_SIZE(qmp_v3_phy_clk_l),
1440 	.reset_list		= msm8996_usb3phy_reset_l,
1441 	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
1442 	.vreg_list		= qmp_phy_vreg_l,
1443 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1444 	.regs			= qmp_v3_usb3phy_regs_layout,
1445 
1446 	.has_pwrdn_delay	= true,
1447 };
1448 
1449 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = {
1450 	.lanes			= 2,
1451 
1452 	.serdes_tbl             = msm8998_usb3_serdes_tbl,
1453 	.serdes_tbl_num         = ARRAY_SIZE(msm8998_usb3_serdes_tbl),
1454 	.tx_tbl                 = msm8998_usb3_tx_tbl,
1455 	.tx_tbl_num             = ARRAY_SIZE(msm8998_usb3_tx_tbl),
1456 	.rx_tbl                 = msm8998_usb3_rx_tbl,
1457 	.rx_tbl_num             = ARRAY_SIZE(msm8998_usb3_rx_tbl),
1458 	.pcs_tbl                = msm8998_usb3_pcs_tbl,
1459 	.pcs_tbl_num            = ARRAY_SIZE(msm8998_usb3_pcs_tbl),
1460 	.clk_list               = msm8996_phy_clk_l,
1461 	.num_clks               = ARRAY_SIZE(msm8996_phy_clk_l),
1462 	.reset_list             = msm8996_usb3phy_reset_l,
1463 	.num_resets             = ARRAY_SIZE(msm8996_usb3phy_reset_l),
1464 	.vreg_list              = qmp_phy_vreg_l,
1465 	.num_vregs              = ARRAY_SIZE(qmp_phy_vreg_l),
1466 	.regs                   = qmp_v3_usb3phy_regs_layout,
1467 };
1468 
1469 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = {
1470 	.lanes			= 1,
1471 
1472 	.serdes_tbl		= sm8150_usb3_uniphy_serdes_tbl,
1473 	.serdes_tbl_num		= ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1474 	.tx_tbl			= sm8150_usb3_uniphy_tx_tbl,
1475 	.tx_tbl_num		= ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl),
1476 	.rx_tbl			= sm8150_usb3_uniphy_rx_tbl,
1477 	.rx_tbl_num		= ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl),
1478 	.pcs_tbl		= sm8150_usb3_uniphy_pcs_tbl,
1479 	.pcs_tbl_num		= ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl),
1480 	.pcs_usb_tbl		= sm8150_usb3_uniphy_pcs_usb_tbl,
1481 	.pcs_usb_tbl_num	= ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl),
1482 	.clk_list		= qmp_v4_ref_phy_clk_l,
1483 	.num_clks		= ARRAY_SIZE(qmp_v4_ref_phy_clk_l),
1484 	.reset_list		= msm8996_usb3phy_reset_l,
1485 	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
1486 	.vreg_list		= qmp_phy_vreg_l,
1487 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1488 	.regs			= qmp_v4_usb3phy_regs_layout,
1489 	.pcs_usb_offset		= 0x600,
1490 
1491 	.has_pwrdn_delay	= true,
1492 };
1493 
1494 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = {
1495 	.lanes			= 1,
1496 
1497 	.serdes_tbl		= sm8150_usb3_uniphy_serdes_tbl,
1498 	.serdes_tbl_num		= ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1499 	.tx_tbl			= sm8250_usb3_uniphy_tx_tbl,
1500 	.tx_tbl_num		= ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl),
1501 	.rx_tbl			= sm8250_usb3_uniphy_rx_tbl,
1502 	.rx_tbl_num		= ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl),
1503 	.pcs_tbl		= sm8250_usb3_uniphy_pcs_tbl,
1504 	.pcs_tbl_num		= ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1505 	.pcs_usb_tbl		= sm8250_usb3_uniphy_pcs_usb_tbl,
1506 	.pcs_usb_tbl_num	= ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1507 	.clk_list		= qmp_v4_ref_phy_clk_l,
1508 	.num_clks		= ARRAY_SIZE(qmp_v4_ref_phy_clk_l),
1509 	.reset_list		= msm8996_usb3phy_reset_l,
1510 	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
1511 	.vreg_list		= qmp_phy_vreg_l,
1512 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1513 	.regs			= qmp_v4_usb3phy_regs_layout,
1514 	.pcs_usb_offset		= 0x600,
1515 
1516 	.has_pwrdn_delay	= true,
1517 };
1518 
1519 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = {
1520 	.lanes			= 1,
1521 
1522 	.serdes_tbl		= sm8150_usb3_uniphy_serdes_tbl,
1523 	.serdes_tbl_num		= ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1524 	.tx_tbl			= sdx55_usb3_uniphy_tx_tbl,
1525 	.tx_tbl_num		= ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl),
1526 	.rx_tbl			= sdx55_usb3_uniphy_rx_tbl,
1527 	.rx_tbl_num		= ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl),
1528 	.pcs_tbl		= sm8250_usb3_uniphy_pcs_tbl,
1529 	.pcs_tbl_num		= ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl),
1530 	.pcs_usb_tbl		= sm8250_usb3_uniphy_pcs_usb_tbl,
1531 	.pcs_usb_tbl_num	= ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl),
1532 	.clk_list		= qmp_v4_sdx55_usbphy_clk_l,
1533 	.num_clks		= ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
1534 	.reset_list		= msm8996_usb3phy_reset_l,
1535 	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
1536 	.vreg_list		= qmp_phy_vreg_l,
1537 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1538 	.regs			= qmp_v4_usb3phy_regs_layout,
1539 	.pcs_usb_offset		= 0x600,
1540 
1541 	.has_pwrdn_delay	= true,
1542 };
1543 
1544 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = {
1545 	.lanes			= 1,
1546 
1547 	.serdes_tbl		= sm8150_usb3_uniphy_serdes_tbl,
1548 	.serdes_tbl_num		= ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1549 	.tx_tbl			= sdx65_usb3_uniphy_tx_tbl,
1550 	.tx_tbl_num		= ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl),
1551 	.rx_tbl			= sdx65_usb3_uniphy_rx_tbl,
1552 	.rx_tbl_num		= ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl),
1553 	.pcs_tbl		= sm8350_usb3_uniphy_pcs_tbl,
1554 	.pcs_tbl_num		= ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1555 	.pcs_usb_tbl		= sm8350_usb3_uniphy_pcs_usb_tbl,
1556 	.pcs_usb_tbl_num	= ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1557 	.clk_list		= qmp_v4_sdx55_usbphy_clk_l,
1558 	.num_clks		= ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l),
1559 	.reset_list		= msm8996_usb3phy_reset_l,
1560 	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
1561 	.vreg_list		= qmp_phy_vreg_l,
1562 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1563 	.regs			= qmp_v5_usb3phy_regs_layout,
1564 	.pcs_usb_offset		= 0x1000,
1565 
1566 	.has_pwrdn_delay	= true,
1567 };
1568 
1569 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = {
1570 	.lanes			= 1,
1571 
1572 	.serdes_tbl		= sm8150_usb3_uniphy_serdes_tbl,
1573 	.serdes_tbl_num		= ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl),
1574 	.tx_tbl			= sm8350_usb3_uniphy_tx_tbl,
1575 	.tx_tbl_num		= ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl),
1576 	.rx_tbl			= sm8350_usb3_uniphy_rx_tbl,
1577 	.rx_tbl_num		= ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl),
1578 	.pcs_tbl		= sm8350_usb3_uniphy_pcs_tbl,
1579 	.pcs_tbl_num		= ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl),
1580 	.pcs_usb_tbl		= sm8350_usb3_uniphy_pcs_usb_tbl,
1581 	.pcs_usb_tbl_num	= ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl),
1582 	.clk_list		= qmp_v4_ref_phy_clk_l,
1583 	.num_clks		= ARRAY_SIZE(qmp_v4_ref_phy_clk_l),
1584 	.reset_list		= msm8996_usb3phy_reset_l,
1585 	.num_resets		= ARRAY_SIZE(msm8996_usb3phy_reset_l),
1586 	.vreg_list		= qmp_phy_vreg_l,
1587 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1588 	.regs			= qmp_v5_usb3phy_regs_layout,
1589 	.pcs_usb_offset		= 0x1000,
1590 
1591 	.has_pwrdn_delay	= true,
1592 };
1593 
1594 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = {
1595 	.lanes			= 2,
1596 
1597 	.offsets		= &qmp_usb_offsets_v3,
1598 
1599 	.serdes_tbl		= qcm2290_usb3_serdes_tbl,
1600 	.serdes_tbl_num		= ARRAY_SIZE(qcm2290_usb3_serdes_tbl),
1601 	.tx_tbl			= qcm2290_usb3_tx_tbl,
1602 	.tx_tbl_num		= ARRAY_SIZE(qcm2290_usb3_tx_tbl),
1603 	.rx_tbl			= qcm2290_usb3_rx_tbl,
1604 	.rx_tbl_num		= ARRAY_SIZE(qcm2290_usb3_rx_tbl),
1605 	.pcs_tbl		= qcm2290_usb3_pcs_tbl,
1606 	.pcs_tbl_num		= ARRAY_SIZE(qcm2290_usb3_pcs_tbl),
1607 	.clk_list		= qcm2290_usb3phy_clk_l,
1608 	.num_clks		= ARRAY_SIZE(qcm2290_usb3phy_clk_l),
1609 	.reset_list		= qcm2290_usb3phy_reset_l,
1610 	.num_resets		= ARRAY_SIZE(qcm2290_usb3phy_reset_l),
1611 	.vreg_list		= qmp_phy_vreg_l,
1612 	.num_vregs		= ARRAY_SIZE(qmp_phy_vreg_l),
1613 	.regs			= qmp_v3_usb3phy_regs_layout,
1614 };
1615 
1616 static void qmp_usb_configure_lane(void __iomem *base,
1617 					const struct qmp_phy_init_tbl tbl[],
1618 					int num,
1619 					u8 lane_mask)
1620 {
1621 	int i;
1622 	const struct qmp_phy_init_tbl *t = tbl;
1623 
1624 	if (!t)
1625 		return;
1626 
1627 	for (i = 0; i < num; i++, t++) {
1628 		if (!(t->lane_mask & lane_mask))
1629 			continue;
1630 
1631 		writel(t->val, base + t->offset);
1632 	}
1633 }
1634 
1635 static void qmp_usb_configure(void __iomem *base,
1636 				   const struct qmp_phy_init_tbl tbl[],
1637 				   int num)
1638 {
1639 	qmp_usb_configure_lane(base, tbl, num, 0xff);
1640 }
1641 
1642 static int qmp_usb_serdes_init(struct qmp_usb *qmp)
1643 {
1644 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1645 	void __iomem *serdes = qmp->serdes;
1646 	const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl;
1647 	int serdes_tbl_num = cfg->serdes_tbl_num;
1648 
1649 	qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num);
1650 
1651 	return 0;
1652 }
1653 
1654 static int qmp_usb_init(struct phy *phy)
1655 {
1656 	struct qmp_usb *qmp = phy_get_drvdata(phy);
1657 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1658 	void __iomem *pcs = qmp->pcs;
1659 	int ret;
1660 
1661 	ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs);
1662 	if (ret) {
1663 		dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret);
1664 		return ret;
1665 	}
1666 
1667 	ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets);
1668 	if (ret) {
1669 		dev_err(qmp->dev, "reset assert failed\n");
1670 		goto err_disable_regulators;
1671 	}
1672 
1673 	ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets);
1674 	if (ret) {
1675 		dev_err(qmp->dev, "reset deassert failed\n");
1676 		goto err_disable_regulators;
1677 	}
1678 
1679 	ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1680 	if (ret)
1681 		goto err_assert_reset;
1682 
1683 	qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN);
1684 
1685 	return 0;
1686 
1687 err_assert_reset:
1688 	reset_control_bulk_assert(cfg->num_resets, qmp->resets);
1689 err_disable_regulators:
1690 	regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1691 
1692 	return ret;
1693 }
1694 
1695 static int qmp_usb_exit(struct phy *phy)
1696 {
1697 	struct qmp_usb *qmp = phy_get_drvdata(phy);
1698 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1699 
1700 	reset_control_bulk_assert(cfg->num_resets, qmp->resets);
1701 
1702 	clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1703 
1704 	regulator_bulk_disable(cfg->num_vregs, qmp->vregs);
1705 
1706 	return 0;
1707 }
1708 
1709 static int qmp_usb_power_on(struct phy *phy)
1710 {
1711 	struct qmp_usb *qmp = phy_get_drvdata(phy);
1712 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1713 	void __iomem *tx = qmp->tx;
1714 	void __iomem *rx = qmp->rx;
1715 	void __iomem *pcs = qmp->pcs;
1716 	void __iomem *pcs_usb = qmp->pcs_usb;
1717 	void __iomem *status;
1718 	unsigned int val;
1719 	int ret;
1720 
1721 	qmp_usb_serdes_init(qmp);
1722 
1723 	ret = clk_prepare_enable(qmp->pipe_clk);
1724 	if (ret) {
1725 		dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret);
1726 		return ret;
1727 	}
1728 
1729 	/* Tx, Rx, and PCS configurations */
1730 	qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1);
1731 	qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1);
1732 
1733 	if (cfg->lanes >= 2) {
1734 		qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2);
1735 		qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2);
1736 	}
1737 
1738 	qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num);
1739 
1740 	if (pcs_usb)
1741 		qmp_usb_configure(pcs_usb, cfg->pcs_usb_tbl, cfg->pcs_usb_tbl_num);
1742 
1743 	if (cfg->has_pwrdn_delay)
1744 		usleep_range(10, 20);
1745 
1746 	/* Pull PHY out of reset state */
1747 	qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1748 
1749 	/* start SerDes and Phy-Coding-Sublayer */
1750 	qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START);
1751 
1752 	status = pcs + cfg->regs[QPHY_PCS_STATUS];
1753 	ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200,
1754 				 PHY_INIT_COMPLETE_TIMEOUT);
1755 	if (ret) {
1756 		dev_err(qmp->dev, "phy initialization timed-out\n");
1757 		goto err_disable_pipe_clk;
1758 	}
1759 
1760 	return 0;
1761 
1762 err_disable_pipe_clk:
1763 	clk_disable_unprepare(qmp->pipe_clk);
1764 
1765 	return ret;
1766 }
1767 
1768 static int qmp_usb_power_off(struct phy *phy)
1769 {
1770 	struct qmp_usb *qmp = phy_get_drvdata(phy);
1771 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1772 
1773 	clk_disable_unprepare(qmp->pipe_clk);
1774 
1775 	/* PHY reset */
1776 	qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET);
1777 
1778 	/* stop SerDes and Phy-Coding-Sublayer */
1779 	qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL],
1780 			SERDES_START | PCS_START);
1781 
1782 	/* Put PHY into POWER DOWN state: active low */
1783 	qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL],
1784 			SW_PWRDN);
1785 
1786 	return 0;
1787 }
1788 
1789 static int qmp_usb_enable(struct phy *phy)
1790 {
1791 	int ret;
1792 
1793 	ret = qmp_usb_init(phy);
1794 	if (ret)
1795 		return ret;
1796 
1797 	ret = qmp_usb_power_on(phy);
1798 	if (ret)
1799 		qmp_usb_exit(phy);
1800 
1801 	return ret;
1802 }
1803 
1804 static int qmp_usb_disable(struct phy *phy)
1805 {
1806 	int ret;
1807 
1808 	ret = qmp_usb_power_off(phy);
1809 	if (ret)
1810 		return ret;
1811 	return qmp_usb_exit(phy);
1812 }
1813 
1814 static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode)
1815 {
1816 	struct qmp_usb *qmp = phy_get_drvdata(phy);
1817 
1818 	qmp->mode = mode;
1819 
1820 	return 0;
1821 }
1822 
1823 static const struct phy_ops qmp_usb_phy_ops = {
1824 	.init		= qmp_usb_enable,
1825 	.exit		= qmp_usb_disable,
1826 	.set_mode	= qmp_usb_set_mode,
1827 	.owner		= THIS_MODULE,
1828 };
1829 
1830 static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp)
1831 {
1832 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1833 	void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1834 	void __iomem *pcs_misc = qmp->pcs_misc;
1835 	u32 intr_mask;
1836 
1837 	if (qmp->mode == PHY_MODE_USB_HOST_SS ||
1838 	    qmp->mode == PHY_MODE_USB_DEVICE_SS)
1839 		intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN;
1840 	else
1841 		intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL;
1842 
1843 	/* Clear any pending interrupts status */
1844 	qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1845 	/* Writing 1 followed by 0 clears the interrupt */
1846 	qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1847 
1848 	qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1849 		     ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL);
1850 
1851 	/* Enable required PHY autonomous mode interrupts */
1852 	qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask);
1853 
1854 	/* Enable i/o clamp_n for autonomous mode */
1855 	if (pcs_misc)
1856 		qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1857 }
1858 
1859 static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp)
1860 {
1861 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1862 	void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs;
1863 	void __iomem *pcs_misc = qmp->pcs_misc;
1864 
1865 	/* Disable i/o clamp_n on resume for normal mode */
1866 	if (pcs_misc)
1867 		qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN);
1868 
1869 	qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL],
1870 		     ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN);
1871 
1872 	qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1873 	/* Writing 1 followed by 0 clears the interrupt */
1874 	qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR);
1875 }
1876 
1877 static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev)
1878 {
1879 	struct qmp_usb *qmp = dev_get_drvdata(dev);
1880 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1881 
1882 	dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode);
1883 
1884 	if (!qmp->phy->init_count) {
1885 		dev_vdbg(dev, "PHY not initialized, bailing out\n");
1886 		return 0;
1887 	}
1888 
1889 	qmp_usb_enable_autonomous_mode(qmp);
1890 
1891 	clk_disable_unprepare(qmp->pipe_clk);
1892 	clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1893 
1894 	return 0;
1895 }
1896 
1897 static int __maybe_unused qmp_usb_runtime_resume(struct device *dev)
1898 {
1899 	struct qmp_usb *qmp = dev_get_drvdata(dev);
1900 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1901 	int ret = 0;
1902 
1903 	dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode);
1904 
1905 	if (!qmp->phy->init_count) {
1906 		dev_vdbg(dev, "PHY not initialized, bailing out\n");
1907 		return 0;
1908 	}
1909 
1910 	ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks);
1911 	if (ret)
1912 		return ret;
1913 
1914 	ret = clk_prepare_enable(qmp->pipe_clk);
1915 	if (ret) {
1916 		dev_err(dev, "pipe_clk enable failed, err=%d\n", ret);
1917 		clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks);
1918 		return ret;
1919 	}
1920 
1921 	qmp_usb_disable_autonomous_mode(qmp);
1922 
1923 	return 0;
1924 }
1925 
1926 static const struct dev_pm_ops qmp_usb_pm_ops = {
1927 	SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend,
1928 			   qmp_usb_runtime_resume, NULL)
1929 };
1930 
1931 static int qmp_usb_vreg_init(struct qmp_usb *qmp)
1932 {
1933 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1934 	struct device *dev = qmp->dev;
1935 	int num = cfg->num_vregs;
1936 	int i;
1937 
1938 	qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL);
1939 	if (!qmp->vregs)
1940 		return -ENOMEM;
1941 
1942 	for (i = 0; i < num; i++)
1943 		qmp->vregs[i].supply = cfg->vreg_list[i];
1944 
1945 	return devm_regulator_bulk_get(dev, num, qmp->vregs);
1946 }
1947 
1948 static int qmp_usb_reset_init(struct qmp_usb *qmp)
1949 {
1950 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1951 	struct device *dev = qmp->dev;
1952 	int i;
1953 	int ret;
1954 
1955 	qmp->resets = devm_kcalloc(dev, cfg->num_resets,
1956 				   sizeof(*qmp->resets), GFP_KERNEL);
1957 	if (!qmp->resets)
1958 		return -ENOMEM;
1959 
1960 	for (i = 0; i < cfg->num_resets; i++)
1961 		qmp->resets[i].id = cfg->reset_list[i];
1962 
1963 	ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets);
1964 	if (ret)
1965 		return dev_err_probe(dev, ret, "failed to get resets\n");
1966 
1967 	return 0;
1968 }
1969 
1970 static int qmp_usb_clk_init(struct qmp_usb *qmp)
1971 {
1972 	const struct qmp_phy_cfg *cfg = qmp->cfg;
1973 	struct device *dev = qmp->dev;
1974 	int num = cfg->num_clks;
1975 	int i;
1976 
1977 	qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL);
1978 	if (!qmp->clks)
1979 		return -ENOMEM;
1980 
1981 	for (i = 0; i < num; i++)
1982 		qmp->clks[i].id = cfg->clk_list[i];
1983 
1984 	return devm_clk_bulk_get(dev, num, qmp->clks);
1985 }
1986 
1987 static void phy_clk_release_provider(void *res)
1988 {
1989 	of_clk_del_provider(res);
1990 }
1991 
1992 /*
1993  * Register a fixed rate pipe clock.
1994  *
1995  * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate
1996  * controls it. The <s>_pipe_clk coming out of the GCC is requested
1997  * by the PHY driver for its operations.
1998  * We register the <s>_pipe_clksrc here. The gcc driver takes care
1999  * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk.
2000  * Below picture shows this relationship.
2001  *
2002  *         +---------------+
2003  *         |   PHY block   |<<---------------------------------------+
2004  *         |               |                                         |
2005  *         |   +-------+   |                   +-----+               |
2006  *   I/P---^-->|  PLL  |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+
2007  *    clk  |   +-------+   |                   +-----+
2008  *         +---------------+
2009  */
2010 static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np)
2011 {
2012 	struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed;
2013 	struct clk_init_data init = { };
2014 	int ret;
2015 
2016 	ret = of_property_read_string(np, "clock-output-names", &init.name);
2017 	if (ret) {
2018 		dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np);
2019 		return ret;
2020 	}
2021 
2022 	init.ops = &clk_fixed_rate_ops;
2023 
2024 	/* controllers using QMP phys use 125MHz pipe clock interface */
2025 	fixed->fixed_rate = 125000000;
2026 	fixed->hw.init = &init;
2027 
2028 	ret = devm_clk_hw_register(qmp->dev, &fixed->hw);
2029 	if (ret)
2030 		return ret;
2031 
2032 	ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw);
2033 	if (ret)
2034 		return ret;
2035 
2036 	/*
2037 	 * Roll a devm action because the clock provider is the child node, but
2038 	 * the child node is not actually a device.
2039 	 */
2040 	return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np);
2041 }
2042 
2043 static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np,
2044 					int index, bool exclusive)
2045 {
2046 	struct resource res;
2047 
2048 	if (!exclusive) {
2049 		if (of_address_to_resource(np, index, &res))
2050 			return IOMEM_ERR_PTR(-EINVAL);
2051 
2052 		return devm_ioremap(dev, res.start, resource_size(&res));
2053 	}
2054 
2055 	return devm_of_iomap(dev, np, index, NULL);
2056 }
2057 
2058 static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np)
2059 {
2060 	struct platform_device *pdev = to_platform_device(qmp->dev);
2061 	const struct qmp_phy_cfg *cfg = qmp->cfg;
2062 	struct device *dev = qmp->dev;
2063 	bool exclusive = true;
2064 
2065 	qmp->serdes = devm_platform_ioremap_resource(pdev, 0);
2066 	if (IS_ERR(qmp->serdes))
2067 		return PTR_ERR(qmp->serdes);
2068 
2069 	/*
2070 	 * FIXME: These bindings should be fixed to not rely on overlapping
2071 	 *        mappings for PCS.
2072 	 */
2073 	if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy"))
2074 		exclusive = false;
2075 	if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy"))
2076 		exclusive = false;
2077 
2078 	/*
2079 	 * Get memory resources for the PHY:
2080 	 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2.
2081 	 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5
2082 	 * For single lane PHYs: pcs_misc (optional) -> 3.
2083 	 */
2084 	qmp->tx = devm_of_iomap(dev, np, 0, NULL);
2085 	if (IS_ERR(qmp->tx))
2086 		return PTR_ERR(qmp->tx);
2087 
2088 	qmp->rx = devm_of_iomap(dev, np, 1, NULL);
2089 	if (IS_ERR(qmp->rx))
2090 		return PTR_ERR(qmp->rx);
2091 
2092 	qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive);
2093 	if (IS_ERR(qmp->pcs))
2094 		return PTR_ERR(qmp->pcs);
2095 
2096 	if (cfg->pcs_usb_offset)
2097 		qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset;
2098 
2099 	if (cfg->lanes >= 2) {
2100 		qmp->tx2 = devm_of_iomap(dev, np, 3, NULL);
2101 		if (IS_ERR(qmp->tx2))
2102 			return PTR_ERR(qmp->tx2);
2103 
2104 		qmp->rx2 = devm_of_iomap(dev, np, 4, NULL);
2105 		if (IS_ERR(qmp->rx2))
2106 			return PTR_ERR(qmp->rx2);
2107 
2108 		qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL);
2109 	} else {
2110 		qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL);
2111 	}
2112 
2113 	if (IS_ERR(qmp->pcs_misc)) {
2114 		dev_vdbg(dev, "PHY pcs_misc-reg not used\n");
2115 		qmp->pcs_misc = NULL;
2116 	}
2117 
2118 	qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL);
2119 	if (IS_ERR(qmp->pipe_clk)) {
2120 		return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2121 				     "failed to get pipe clock\n");
2122 	}
2123 
2124 	return 0;
2125 }
2126 
2127 static int qmp_usb_parse_dt(struct qmp_usb *qmp)
2128 {
2129 	struct platform_device *pdev = to_platform_device(qmp->dev);
2130 	const struct qmp_phy_cfg *cfg = qmp->cfg;
2131 	const struct qmp_usb_offsets *offs = cfg->offsets;
2132 	struct device *dev = qmp->dev;
2133 	void __iomem *base;
2134 
2135 	if (!offs)
2136 		return -EINVAL;
2137 
2138 	base = devm_platform_ioremap_resource(pdev, 0);
2139 	if (IS_ERR(base))
2140 		return PTR_ERR(base);
2141 
2142 	qmp->serdes = base + offs->serdes;
2143 	qmp->pcs = base + offs->pcs;
2144 	qmp->pcs_misc = base + offs->pcs_misc;
2145 	qmp->pcs_usb = base + offs->pcs_usb;
2146 	qmp->tx = base + offs->tx;
2147 	qmp->rx = base + offs->rx;
2148 
2149 	if (cfg->lanes >= 2) {
2150 		qmp->tx2 = base + offs->tx2;
2151 		qmp->rx2 = base + offs->rx2;
2152 	}
2153 
2154 	qmp->pipe_clk = devm_clk_get(dev, "pipe");
2155 	if (IS_ERR(qmp->pipe_clk)) {
2156 		return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk),
2157 				     "failed to get pipe clock\n");
2158 	}
2159 
2160 	return 0;
2161 }
2162 
2163 static int qmp_usb_probe(struct platform_device *pdev)
2164 {
2165 	struct device *dev = &pdev->dev;
2166 	struct phy_provider *phy_provider;
2167 	struct device_node *np;
2168 	struct qmp_usb *qmp;
2169 	int ret;
2170 
2171 	qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL);
2172 	if (!qmp)
2173 		return -ENOMEM;
2174 
2175 	qmp->dev = dev;
2176 
2177 	qmp->cfg = of_device_get_match_data(dev);
2178 	if (!qmp->cfg)
2179 		return -EINVAL;
2180 
2181 	ret = qmp_usb_clk_init(qmp);
2182 	if (ret)
2183 		return ret;
2184 
2185 	ret = qmp_usb_reset_init(qmp);
2186 	if (ret)
2187 		return ret;
2188 
2189 	ret = qmp_usb_vreg_init(qmp);
2190 	if (ret)
2191 		return ret;
2192 
2193 	/* Check for legacy binding with child node. */
2194 	np = of_get_next_available_child(dev->of_node, NULL);
2195 	if (np) {
2196 		ret = qmp_usb_parse_dt_legacy(qmp, np);
2197 	} else {
2198 		np = of_node_get(dev->of_node);
2199 		ret = qmp_usb_parse_dt(qmp);
2200 	}
2201 	if (ret)
2202 		goto err_node_put;
2203 
2204 	pm_runtime_set_active(dev);
2205 	ret = devm_pm_runtime_enable(dev);
2206 	if (ret)
2207 		goto err_node_put;
2208 	/*
2209 	 * Prevent runtime pm from being ON by default. Users can enable
2210 	 * it using power/control in sysfs.
2211 	 */
2212 	pm_runtime_forbid(dev);
2213 
2214 	ret = phy_pipe_clk_register(qmp, np);
2215 	if (ret)
2216 		goto err_node_put;
2217 
2218 	qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops);
2219 	if (IS_ERR(qmp->phy)) {
2220 		ret = PTR_ERR(qmp->phy);
2221 		dev_err(dev, "failed to create PHY: %d\n", ret);
2222 		goto err_node_put;
2223 	}
2224 
2225 	phy_set_drvdata(qmp->phy, qmp);
2226 
2227 	of_node_put(np);
2228 
2229 	phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate);
2230 
2231 	return PTR_ERR_OR_ZERO(phy_provider);
2232 
2233 err_node_put:
2234 	of_node_put(np);
2235 	return ret;
2236 }
2237 
2238 static const struct of_device_id qmp_usb_of_match_table[] = {
2239 	{
2240 		.compatible = "qcom,ipq6018-qmp-usb3-phy",
2241 		.data = &ipq8074_usb3phy_cfg,
2242 	}, {
2243 		.compatible = "qcom,ipq8074-qmp-usb3-phy",
2244 		.data = &ipq8074_usb3phy_cfg,
2245 	}, {
2246 		.compatible = "qcom,ipq9574-qmp-usb3-phy",
2247 		.data = &ipq9574_usb3phy_cfg,
2248 	}, {
2249 		.compatible = "qcom,msm8996-qmp-usb3-phy",
2250 		.data = &msm8996_usb3phy_cfg,
2251 	}, {
2252 		.compatible = "qcom,msm8998-qmp-usb3-phy",
2253 		.data = &msm8998_usb3phy_cfg,
2254 	}, {
2255 		.compatible = "qcom,qcm2290-qmp-usb3-phy",
2256 		.data = &qcm2290_usb3phy_cfg,
2257 	}, {
2258 		.compatible = "qcom,sa8775p-qmp-usb3-uni-phy",
2259 		.data = &sa8775p_usb3_uniphy_cfg,
2260 	}, {
2261 		.compatible = "qcom,sc8280xp-qmp-usb3-uni-phy",
2262 		.data = &sc8280xp_usb3_uniphy_cfg,
2263 	}, {
2264 		.compatible = "qcom,sdm845-qmp-usb3-uni-phy",
2265 		.data = &qmp_v3_usb3_uniphy_cfg,
2266 	}, {
2267 		.compatible = "qcom,sdx55-qmp-usb3-uni-phy",
2268 		.data = &sdx55_usb3_uniphy_cfg,
2269 	}, {
2270 		.compatible = "qcom,sdx65-qmp-usb3-uni-phy",
2271 		.data = &sdx65_usb3_uniphy_cfg,
2272 	}, {
2273 		.compatible = "qcom,sm6115-qmp-usb3-phy",
2274 		.data = &qcm2290_usb3phy_cfg,
2275 	}, {
2276 		.compatible = "qcom,sm8150-qmp-usb3-uni-phy",
2277 		.data = &sm8150_usb3_uniphy_cfg,
2278 	}, {
2279 		.compatible = "qcom,sm8250-qmp-usb3-uni-phy",
2280 		.data = &sm8250_usb3_uniphy_cfg,
2281 	}, {
2282 		.compatible = "qcom,sm8350-qmp-usb3-uni-phy",
2283 		.data = &sm8350_usb3_uniphy_cfg,
2284 	},
2285 	{ },
2286 };
2287 MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table);
2288 
2289 static struct platform_driver qmp_usb_driver = {
2290 	.probe		= qmp_usb_probe,
2291 	.driver = {
2292 		.name	= "qcom-qmp-usb-phy",
2293 		.pm	= &qmp_usb_pm_ops,
2294 		.of_match_table = qmp_usb_of_match_table,
2295 	},
2296 };
2297 
2298 module_platform_driver(qmp_usb_driver);
2299 
2300 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>");
2301 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver");
2302 MODULE_LICENSE("GPL v2");
2303