1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include "phy-qcom-qmp.h" 24 #include "phy-qcom-qmp-pcs-misc-v3.h" 25 #include "phy-qcom-qmp-pcs-usb-v4.h" 26 #include "phy-qcom-qmp-pcs-usb-v5.h" 27 28 /* QPHY_SW_RESET bit */ 29 #define SW_RESET BIT(0) 30 /* QPHY_POWER_DOWN_CONTROL */ 31 #define SW_PWRDN BIT(0) 32 /* QPHY_START_CONTROL bits */ 33 #define SERDES_START BIT(0) 34 #define PCS_START BIT(1) 35 /* QPHY_PCS_STATUS bit */ 36 #define PHYSTATUS BIT(6) 37 38 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 39 /* DP PHY soft reset */ 40 #define SW_DPPHY_RESET BIT(0) 41 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 42 #define SW_DPPHY_RESET_MUX BIT(1) 43 /* USB3 PHY soft reset */ 44 #define SW_USB3PHY_RESET BIT(2) 45 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 46 #define SW_USB3PHY_RESET_MUX BIT(3) 47 48 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 49 #define USB3_MODE BIT(0) /* enables USB3 mode */ 50 #define DP_MODE BIT(1) /* enables DP mode */ 51 52 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 53 #define ARCVR_DTCT_EN BIT(0) 54 #define ALFPS_DTCT_EN BIT(1) 55 #define ARCVR_DTCT_EVENT_SEL BIT(4) 56 57 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 58 #define IRQ_CLEAR BIT(0) 59 60 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 61 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 62 63 #define PHY_INIT_COMPLETE_TIMEOUT 10000 64 65 struct qmp_phy_init_tbl { 66 unsigned int offset; 67 unsigned int val; 68 /* 69 * mask of lanes for which this register is written 70 * for cases when second lane needs different values 71 */ 72 u8 lane_mask; 73 }; 74 75 #define QMP_PHY_INIT_CFG(o, v) \ 76 { \ 77 .offset = o, \ 78 .val = v, \ 79 .lane_mask = 0xff, \ 80 } 81 82 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 83 { \ 84 .offset = o, \ 85 .val = v, \ 86 .lane_mask = l, \ 87 } 88 89 /* set of registers with offsets different per-PHY */ 90 enum qphy_reg_layout { 91 /* PCS registers */ 92 QPHY_SW_RESET, 93 QPHY_START_CTRL, 94 QPHY_PCS_STATUS, 95 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 96 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 97 QPHY_PCS_POWER_DOWN_CONTROL, 98 /* Keep last to ensure regs_layout arrays are properly initialized */ 99 QPHY_LAYOUT_SIZE 100 }; 101 102 static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 103 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 104 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 105 [QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS, 106 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL, 107 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR, 108 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, 109 }; 110 111 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 112 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 113 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 114 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 115 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 116 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 117 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 118 }; 119 120 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 121 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 122 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 123 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 124 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 125 126 /* In PCS_USB */ 127 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 128 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 129 }; 130 131 static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 132 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 133 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 134 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 135 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 136 137 /* In PCS_USB */ 138 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 139 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 140 }; 141 142 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { 143 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), 144 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 145 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 146 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 147 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 148 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 149 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 150 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 151 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 152 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 153 /* PLL and Loop filter settings */ 154 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 155 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 156 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 157 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 158 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 159 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 160 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 161 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 162 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 163 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 164 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 165 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 166 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 167 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 168 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 169 /* SSC settings */ 170 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 171 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 172 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 173 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 174 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 175 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 176 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 177 }; 178 179 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { 180 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), 181 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 182 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 183 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), 184 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 185 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 186 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 187 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 188 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), 189 }; 190 191 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { 192 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 193 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 194 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 195 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 196 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 197 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 198 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 207 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 210 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 211 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 212 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 213 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 214 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 215 }; 216 217 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { 218 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 219 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 220 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 221 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 222 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 223 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 224 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 225 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 226 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), 227 /* PLL and Loop filter settings */ 228 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 229 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 230 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 231 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 232 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 233 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 234 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 235 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 236 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 237 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 238 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 239 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 240 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 241 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 242 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 243 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 244 /* SSC settings */ 245 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 246 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 247 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 248 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 249 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 250 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 251 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 252 }; 253 254 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { 255 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 256 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 257 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 258 }; 259 260 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { 261 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 262 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 263 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 264 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 265 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), 266 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 267 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 268 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 269 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), 270 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 271 }; 272 273 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { 274 /* FLL settings */ 275 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03), 276 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02), 277 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09), 278 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42), 279 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85), 280 281 /* Lock Det settings */ 282 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1), 283 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f), 284 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47), 285 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08), 286 }; 287 288 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 289 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 290 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 291 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 292 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 293 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 294 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 295 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 296 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 297 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 298 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 299 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 300 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 301 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 302 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 303 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 304 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 305 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 306 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 307 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 308 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 309 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 310 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 311 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 312 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 313 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 314 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 315 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 316 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 317 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 318 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 319 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 320 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 321 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 322 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 323 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 324 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 325 }; 326 327 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 328 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 329 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 330 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 331 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 332 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 333 }; 334 335 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 336 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 337 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 338 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 339 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 340 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 341 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 342 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 343 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 344 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 345 }; 346 347 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 348 /* FLL settings */ 349 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 350 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 351 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 352 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 353 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 354 355 /* Lock Det settings */ 356 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 357 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 358 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 359 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 360 361 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 362 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 363 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 364 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 369 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 374 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 379 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 380 381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 386 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 387 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 388 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 389 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 390 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 391 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 392 }; 393 394 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { 395 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 396 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 397 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 400 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 407 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 408 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 409 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 410 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 411 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 412 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 413 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 414 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 415 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 416 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 417 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 418 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 419 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 420 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 421 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 422 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 423 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 424 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 425 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 426 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 427 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 428 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 429 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 430 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 431 }; 432 433 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { 434 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 435 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 436 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 437 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 438 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 439 }; 440 441 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { 442 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), 443 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), 444 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 445 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 446 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 447 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 448 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 449 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 450 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 451 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 452 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 453 }; 454 455 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { 456 /* FLL settings */ 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 459 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 462 463 /* Lock Det settings */ 464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 468 469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), 473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), 474 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), 475 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), 476 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 477 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 478 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 479 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 480 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 481 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 482 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 483 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 484 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 485 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 486 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 487 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 488 489 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 490 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 491 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 492 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 493 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 494 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 495 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 496 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 497 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 498 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 499 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 500 501 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 502 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 503 }; 504 505 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { 506 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), 510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 513 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 514 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 515 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 516 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 517 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 518 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 519 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 520 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 521 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 522 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 523 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 524 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 525 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 526 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 527 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 528 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 529 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 530 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 531 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 532 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 533 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 534 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 535 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), 536 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 537 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 538 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 539 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 540 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 541 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 542 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 543 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 544 }; 545 546 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { 547 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 548 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 549 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 550 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 551 }; 552 553 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { 554 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 555 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 556 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 557 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 558 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), 559 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 560 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), 561 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 562 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 563 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 564 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 565 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 566 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 567 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 568 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 569 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), 570 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 571 }; 572 573 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { 574 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 575 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 576 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 577 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 582 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 585 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 586 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 587 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 588 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 589 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 590 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 591 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 592 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 593 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 594 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 595 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 596 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), 597 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 598 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 599 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 600 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 601 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 602 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 603 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 604 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 605 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 606 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 607 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 608 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), 609 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 610 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 611 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 612 }; 613 614 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 615 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 616 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 617 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 618 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 619 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 620 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 621 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 622 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 623 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 624 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 625 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 626 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 627 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 628 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 629 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 630 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 631 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 632 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 633 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 634 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 635 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 636 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 637 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 638 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 639 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 640 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 641 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 642 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 643 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 644 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 645 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 646 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 647 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 648 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 649 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 650 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 651 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 652 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 653 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 654 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 655 }; 656 657 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 658 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 659 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 660 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 661 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 662 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 663 }; 664 665 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 666 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 667 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 668 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 669 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 670 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 671 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 672 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 673 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 674 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 675 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 676 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 677 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 678 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 679 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 680 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 681 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 682 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 683 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 684 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 685 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 686 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 687 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 688 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 689 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 690 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 691 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 692 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 693 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 694 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 695 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 696 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 697 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 698 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 699 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 700 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 701 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 702 }; 703 704 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 705 /* Lock Det settings */ 706 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 707 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 708 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 709 710 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 711 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 712 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 713 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 714 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 715 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 716 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 717 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 718 }; 719 720 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 721 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 722 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 723 }; 724 725 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { 726 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 727 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 728 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 729 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 730 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 731 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 732 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 733 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 734 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 737 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 738 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 739 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 740 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 741 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 742 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 743 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 744 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 745 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 746 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 747 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 748 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 749 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 750 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 751 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 752 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 753 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 754 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 755 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 756 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 757 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 758 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 759 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 760 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 761 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 762 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 763 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 764 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 765 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 766 }; 767 768 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { 769 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 770 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), 771 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 772 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), 773 }; 774 775 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { 776 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 777 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 778 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), 779 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), 780 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), 781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 784 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 785 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 786 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 787 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 788 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 789 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 790 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 791 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 792 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 793 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 794 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 795 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), 796 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 797 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 798 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 799 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 800 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 801 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 802 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 803 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 804 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 805 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 806 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 807 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 808 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 809 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), 810 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 811 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 812 }; 813 814 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { 815 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 816 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 817 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 818 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 819 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 820 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 821 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 822 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), 823 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 824 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 825 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 826 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 827 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 828 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 829 }; 830 831 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = { 832 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 833 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 834 }; 835 836 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 837 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 838 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 839 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 840 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 841 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 842 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 843 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 844 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 845 }; 846 847 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 848 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 849 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 850 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 851 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 852 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 853 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 854 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 855 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 856 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 857 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 858 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 859 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 860 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 861 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 862 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 863 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 864 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 865 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 866 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 867 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 868 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 869 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 870 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 871 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 872 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 873 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 874 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 875 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 876 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 877 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 878 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 879 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 880 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 881 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 882 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 883 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 884 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 885 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 886 }; 887 888 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 889 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 890 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 891 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 892 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 893 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 894 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 895 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 896 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 897 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 898 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 899 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 900 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 901 }; 902 903 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 904 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 905 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 906 }; 907 908 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { 909 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 910 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 911 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), 912 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 913 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 914 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 915 }; 916 917 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { 918 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 919 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), 920 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 921 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 922 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 923 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 924 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 925 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 926 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 927 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 928 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 929 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 937 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), 938 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 939 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 942 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 943 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 944 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 945 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 946 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 947 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 948 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 949 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 950 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 951 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 952 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 953 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 954 }; 955 956 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { 957 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 958 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 959 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 960 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 961 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 962 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 963 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 964 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 965 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 966 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 967 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 968 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 969 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 970 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 971 }; 972 973 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = { 974 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 975 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 976 }; 977 978 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { 979 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 980 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 981 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), 982 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 983 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), 984 }; 985 986 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { 987 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), 988 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 989 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 990 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 991 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 992 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 993 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 994 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 995 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 996 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 997 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 998 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), 999 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 1000 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1022 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 1023 }; 1024 1025 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { 1026 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1027 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1028 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1029 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1030 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1031 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1032 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), 1033 }; 1034 1035 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { 1036 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 1037 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1038 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1039 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1040 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1041 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1042 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1043 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1044 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1045 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1046 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1047 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1048 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1049 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1050 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1051 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1052 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1053 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1054 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1055 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1056 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1057 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1058 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1059 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1060 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1061 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1062 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1063 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1064 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1065 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1066 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1067 }; 1068 1069 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 1070 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 1071 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 1072 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1073 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1074 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 1075 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1076 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 1077 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 1078 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 1079 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1080 }; 1081 1082 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 1083 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1084 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1085 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1086 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1087 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1088 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1089 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1090 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1091 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1092 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1093 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1094 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1095 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1096 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1097 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1098 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1099 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1100 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1101 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1102 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1103 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1104 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 1105 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 1106 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 1107 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 1108 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1115 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 1116 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1117 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1118 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 1119 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1120 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 1121 }; 1122 1123 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 1124 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1125 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1126 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1127 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1128 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1129 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1130 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1131 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1132 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1133 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1134 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1135 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1136 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1137 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1138 }; 1139 1140 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 1141 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1142 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1143 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1144 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1145 }; 1146 1147 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { 1148 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1149 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1150 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1151 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1152 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1155 }; 1156 1157 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { 1158 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1162 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1163 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1164 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1165 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1171 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1172 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1173 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1174 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1175 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1176 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1177 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1178 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1179 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1180 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1181 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1182 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1183 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1184 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1185 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1186 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1187 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1188 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1189 }; 1190 1191 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { 1192 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1193 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1194 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1195 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1196 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1197 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1198 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1199 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1200 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1201 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1202 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1203 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1204 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1205 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1206 }; 1207 1208 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = { 1209 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1210 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1211 }; 1212 1213 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { 1214 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 1215 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 1216 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 1217 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 1218 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), 1219 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), 1220 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 1221 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 1222 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 1223 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 1224 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 1225 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 1226 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 1227 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 1228 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 1229 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 1230 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 1231 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1232 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 1233 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 1234 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 1235 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 1236 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), 1237 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 1238 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 1239 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 1240 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 1241 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 1242 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 1243 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 1244 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 1245 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 1246 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 1247 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 1248 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 1249 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 1250 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), 1251 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), 1252 }; 1253 1254 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { 1255 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 1256 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 1257 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 1258 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 1259 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), 1260 }; 1261 1262 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { 1263 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 1264 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 1265 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 1266 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 1267 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 1268 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 1269 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 1270 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 1271 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 1272 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 1273 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 1274 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1275 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), 1276 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 1277 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 1278 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 1279 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), 1280 }; 1281 1282 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { 1283 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 1284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 1285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 1286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 1287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 1288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 1289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 1290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 1291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 1292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 1293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 1294 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 1295 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 1296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 1297 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 1298 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 1299 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1300 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1301 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 1302 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 1303 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 1304 }; 1305 1306 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = { 1307 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1308 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1309 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1310 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1311 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab), 1312 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea), 1313 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02), 1314 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1315 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1316 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1317 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1318 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1319 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1320 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1321 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1322 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1323 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1324 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02), 1325 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24), 1326 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1327 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82), 1328 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1329 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea), 1330 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1331 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1332 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1333 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1334 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1335 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1336 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 1337 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 1338 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1339 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1340 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1341 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde), 1342 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07), 1343 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1344 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1345 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1346 }; 1347 1348 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = { 1349 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1350 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1351 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1352 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1353 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1354 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 1355 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1356 }; 1357 1358 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = { 1359 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), 1360 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1361 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1362 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1363 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1364 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1365 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1366 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1367 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1368 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1369 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1370 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1371 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1372 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1373 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1374 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1375 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1376 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1377 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a), 1378 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1379 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1380 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1381 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1382 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1383 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1384 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1385 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1386 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1387 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1388 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1389 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1390 }; 1391 1392 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = { 1393 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1394 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1395 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1396 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1397 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1398 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1399 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1400 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1401 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1402 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1403 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a), 1404 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1405 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1406 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1407 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1408 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1409 }; 1410 1411 struct qmp_usb_offsets { 1412 u16 serdes; 1413 u16 pcs; 1414 u16 pcs_usb; 1415 u16 tx; 1416 u16 rx; 1417 }; 1418 1419 /* struct qmp_phy_cfg - per-PHY initialization config */ 1420 struct qmp_phy_cfg { 1421 int lanes; 1422 1423 const struct qmp_usb_offsets *offsets; 1424 1425 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1426 const struct qmp_phy_init_tbl *serdes_tbl; 1427 int serdes_tbl_num; 1428 const struct qmp_phy_init_tbl *tx_tbl; 1429 int tx_tbl_num; 1430 const struct qmp_phy_init_tbl *rx_tbl; 1431 int rx_tbl_num; 1432 const struct qmp_phy_init_tbl *pcs_tbl; 1433 int pcs_tbl_num; 1434 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1435 int pcs_usb_tbl_num; 1436 1437 /* clock ids to be requested */ 1438 const char * const *clk_list; 1439 int num_clks; 1440 /* resets to be requested */ 1441 const char * const *reset_list; 1442 int num_resets; 1443 /* regulators to be requested */ 1444 const char * const *vreg_list; 1445 int num_vregs; 1446 1447 /* array of registers with different offsets */ 1448 const unsigned int *regs; 1449 1450 /* true, if PHY needs delay after POWER_DOWN */ 1451 bool has_pwrdn_delay; 1452 1453 /* true, if PHY has a separate DP_COM control block */ 1454 bool has_phy_dp_com_ctrl; 1455 1456 /* Offset from PCS to PCS_USB region */ 1457 unsigned int pcs_usb_offset; 1458 }; 1459 1460 struct qmp_usb { 1461 struct device *dev; 1462 1463 const struct qmp_phy_cfg *cfg; 1464 1465 void __iomem *serdes; 1466 void __iomem *pcs; 1467 void __iomem *pcs_misc; 1468 void __iomem *pcs_usb; 1469 void __iomem *tx; 1470 void __iomem *rx; 1471 void __iomem *tx2; 1472 void __iomem *rx2; 1473 1474 void __iomem *dp_com; 1475 1476 struct clk *pipe_clk; 1477 struct clk_bulk_data *clks; 1478 struct reset_control_bulk_data *resets; 1479 struct regulator_bulk_data *vregs; 1480 1481 enum phy_mode mode; 1482 1483 struct phy *phy; 1484 1485 struct clk_fixed_rate pipe_clk_fixed; 1486 }; 1487 1488 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1489 { 1490 u32 reg; 1491 1492 reg = readl(base + offset); 1493 reg |= val; 1494 writel(reg, base + offset); 1495 1496 /* ensure that above write is through */ 1497 readl(base + offset); 1498 } 1499 1500 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1501 { 1502 u32 reg; 1503 1504 reg = readl(base + offset); 1505 reg &= ~val; 1506 writel(reg, base + offset); 1507 1508 /* ensure that above write is through */ 1509 readl(base + offset); 1510 } 1511 1512 /* list of clocks required by phy */ 1513 static const char * const msm8996_phy_clk_l[] = { 1514 "aux", "cfg_ahb", "ref", 1515 }; 1516 1517 static const char * const qmp_v3_phy_clk_l[] = { 1518 "aux", "cfg_ahb", "ref", "com_aux", 1519 }; 1520 1521 static const char * const qmp_v4_phy_clk_l[] = { 1522 "aux", "ref", "com_aux", 1523 }; 1524 1525 static const char * const qmp_v4_ref_phy_clk_l[] = { 1526 "aux", "ref_clk_src", "ref", "com_aux", 1527 }; 1528 1529 /* the primary usb3 phy on sm8250 doesn't have a ref clock */ 1530 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { 1531 "aux", "ref_clk_src", "com_aux" 1532 }; 1533 1534 /* usb3 phy on sdx55 doesn't have com_aux clock */ 1535 static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { 1536 "aux", "cfg_ahb", "ref" 1537 }; 1538 1539 static const char * const qcm2290_usb3phy_clk_l[] = { 1540 "cfg_ahb", "ref", "com_aux", 1541 }; 1542 1543 /* list of resets */ 1544 static const char * const msm8996_usb3phy_reset_l[] = { 1545 "phy", "common", 1546 }; 1547 1548 static const char * const sc7180_usb3phy_reset_l[] = { 1549 "phy", 1550 }; 1551 1552 static const char * const qcm2290_usb3phy_reset_l[] = { 1553 "phy_phy", "phy", 1554 }; 1555 1556 /* list of regulators */ 1557 static const char * const qmp_phy_vreg_l[] = { 1558 "vdda-phy", "vdda-pll", 1559 }; 1560 1561 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { 1562 .serdes = 0, 1563 .pcs = 0x0200, 1564 .pcs_usb = 0x1200, 1565 .tx = 0x0e00, 1566 .rx = 0x1000, 1567 }; 1568 1569 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { 1570 .lanes = 1, 1571 1572 .serdes_tbl = ipq8074_usb3_serdes_tbl, 1573 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), 1574 .tx_tbl = msm8996_usb3_tx_tbl, 1575 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1576 .rx_tbl = ipq8074_usb3_rx_tbl, 1577 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), 1578 .pcs_tbl = ipq8074_usb3_pcs_tbl, 1579 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), 1580 .clk_list = msm8996_phy_clk_l, 1581 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1582 .reset_list = msm8996_usb3phy_reset_l, 1583 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1584 .vreg_list = qmp_phy_vreg_l, 1585 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1586 .regs = qmp_v3_usb3phy_regs_layout, 1587 }; 1588 1589 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { 1590 .lanes = 1, 1591 1592 .serdes_tbl = msm8996_usb3_serdes_tbl, 1593 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), 1594 .tx_tbl = msm8996_usb3_tx_tbl, 1595 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1596 .rx_tbl = msm8996_usb3_rx_tbl, 1597 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), 1598 .pcs_tbl = msm8996_usb3_pcs_tbl, 1599 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), 1600 .clk_list = msm8996_phy_clk_l, 1601 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1602 .reset_list = msm8996_usb3phy_reset_l, 1603 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1604 .vreg_list = qmp_phy_vreg_l, 1605 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1606 .regs = qmp_v2_usb3phy_regs_layout, 1607 }; 1608 1609 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { 1610 .lanes = 2, 1611 1612 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1613 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1614 .tx_tbl = qmp_v3_usb3_tx_tbl, 1615 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1616 .rx_tbl = qmp_v3_usb3_rx_tbl, 1617 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1618 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1619 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1620 .clk_list = qmp_v3_phy_clk_l, 1621 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1622 .reset_list = msm8996_usb3phy_reset_l, 1623 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1624 .vreg_list = qmp_phy_vreg_l, 1625 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1626 .regs = qmp_v3_usb3phy_regs_layout, 1627 1628 .has_pwrdn_delay = true, 1629 .has_phy_dp_com_ctrl = true, 1630 }; 1631 1632 static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { 1633 .lanes = 2, 1634 1635 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1636 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1637 .tx_tbl = qmp_v3_usb3_tx_tbl, 1638 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1639 .rx_tbl = qmp_v3_usb3_rx_tbl, 1640 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1641 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1642 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1643 .clk_list = qmp_v3_phy_clk_l, 1644 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1645 .reset_list = sc7180_usb3phy_reset_l, 1646 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1647 .vreg_list = qmp_phy_vreg_l, 1648 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1649 .regs = qmp_v3_usb3phy_regs_layout, 1650 1651 .has_pwrdn_delay = true, 1652 .has_phy_dp_com_ctrl = true, 1653 }; 1654 1655 static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { 1656 .lanes = 1, 1657 1658 .offsets = &qmp_usb_offsets_v5, 1659 1660 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, 1661 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), 1662 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl, 1663 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl), 1664 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl, 1665 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl), 1666 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl, 1667 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl), 1668 .clk_list = qmp_v4_phy_clk_l, 1669 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1670 .reset_list = qcm2290_usb3phy_reset_l, 1671 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 1672 .vreg_list = qmp_phy_vreg_l, 1673 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1674 .regs = qmp_v5_usb3phy_regs_layout, 1675 }; 1676 1677 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { 1678 .lanes = 1, 1679 1680 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, 1681 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), 1682 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, 1683 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), 1684 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, 1685 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), 1686 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, 1687 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), 1688 .clk_list = qmp_v3_phy_clk_l, 1689 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1690 .reset_list = msm8996_usb3phy_reset_l, 1691 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1692 .vreg_list = qmp_phy_vreg_l, 1693 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1694 .regs = qmp_v3_usb3phy_regs_layout, 1695 1696 .has_pwrdn_delay = true, 1697 }; 1698 1699 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { 1700 .lanes = 2, 1701 1702 .serdes_tbl = msm8998_usb3_serdes_tbl, 1703 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), 1704 .tx_tbl = msm8998_usb3_tx_tbl, 1705 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), 1706 .rx_tbl = msm8998_usb3_rx_tbl, 1707 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), 1708 .pcs_tbl = msm8998_usb3_pcs_tbl, 1709 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), 1710 .clk_list = msm8996_phy_clk_l, 1711 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1712 .reset_list = msm8996_usb3phy_reset_l, 1713 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1714 .vreg_list = qmp_phy_vreg_l, 1715 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1716 .regs = qmp_v3_usb3phy_regs_layout, 1717 }; 1718 1719 static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { 1720 .lanes = 2, 1721 1722 .serdes_tbl = sm8150_usb3_serdes_tbl, 1723 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1724 .tx_tbl = sm8150_usb3_tx_tbl, 1725 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1726 .rx_tbl = sm8150_usb3_rx_tbl, 1727 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1728 .pcs_tbl = sm8150_usb3_pcs_tbl, 1729 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1730 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1731 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1732 .clk_list = qmp_v4_ref_phy_clk_l, 1733 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1734 .reset_list = msm8996_usb3phy_reset_l, 1735 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1736 .vreg_list = qmp_phy_vreg_l, 1737 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1738 .regs = qmp_v4_usb3phy_regs_layout, 1739 .pcs_usb_offset = 0x300, 1740 1741 .has_pwrdn_delay = true, 1742 .has_phy_dp_com_ctrl = true, 1743 }; 1744 1745 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { 1746 .lanes = 1, 1747 1748 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1749 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1750 .tx_tbl = sm8150_usb3_uniphy_tx_tbl, 1751 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), 1752 .rx_tbl = sm8150_usb3_uniphy_rx_tbl, 1753 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), 1754 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, 1755 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), 1756 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl, 1757 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl), 1758 .clk_list = qmp_v4_ref_phy_clk_l, 1759 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1760 .reset_list = msm8996_usb3phy_reset_l, 1761 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1762 .vreg_list = qmp_phy_vreg_l, 1763 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1764 .regs = qmp_v4_usb3phy_regs_layout, 1765 .pcs_usb_offset = 0x600, 1766 1767 .has_pwrdn_delay = true, 1768 }; 1769 1770 static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { 1771 .lanes = 2, 1772 1773 .serdes_tbl = sm8150_usb3_serdes_tbl, 1774 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1775 .tx_tbl = sm8250_usb3_tx_tbl, 1776 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1777 .rx_tbl = sm8250_usb3_rx_tbl, 1778 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1779 .pcs_tbl = sm8250_usb3_pcs_tbl, 1780 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1781 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1782 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1783 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1784 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1785 .reset_list = msm8996_usb3phy_reset_l, 1786 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1787 .vreg_list = qmp_phy_vreg_l, 1788 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1789 .regs = qmp_v4_usb3phy_regs_layout, 1790 .pcs_usb_offset = 0x300, 1791 1792 .has_pwrdn_delay = true, 1793 .has_phy_dp_com_ctrl = true, 1794 }; 1795 1796 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { 1797 .lanes = 1, 1798 1799 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1800 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1801 .tx_tbl = sm8250_usb3_uniphy_tx_tbl, 1802 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), 1803 .rx_tbl = sm8250_usb3_uniphy_rx_tbl, 1804 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), 1805 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1806 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1807 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, 1808 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), 1809 .clk_list = qmp_v4_ref_phy_clk_l, 1810 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1811 .reset_list = msm8996_usb3phy_reset_l, 1812 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1813 .vreg_list = qmp_phy_vreg_l, 1814 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1815 .regs = qmp_v4_usb3phy_regs_layout, 1816 .pcs_usb_offset = 0x600, 1817 1818 .has_pwrdn_delay = true, 1819 }; 1820 1821 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { 1822 .lanes = 1, 1823 1824 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1825 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1826 .tx_tbl = sdx55_usb3_uniphy_tx_tbl, 1827 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), 1828 .rx_tbl = sdx55_usb3_uniphy_rx_tbl, 1829 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), 1830 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1831 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1832 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, 1833 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), 1834 .clk_list = qmp_v4_sdx55_usbphy_clk_l, 1835 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), 1836 .reset_list = msm8996_usb3phy_reset_l, 1837 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1838 .vreg_list = qmp_phy_vreg_l, 1839 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1840 .regs = qmp_v4_usb3phy_regs_layout, 1841 .pcs_usb_offset = 0x600, 1842 1843 .has_pwrdn_delay = true, 1844 }; 1845 1846 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { 1847 .lanes = 1, 1848 1849 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1850 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1851 .tx_tbl = sdx65_usb3_uniphy_tx_tbl, 1852 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), 1853 .rx_tbl = sdx65_usb3_uniphy_rx_tbl, 1854 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), 1855 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 1856 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 1857 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, 1858 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), 1859 .clk_list = qmp_v4_sdx55_usbphy_clk_l, 1860 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), 1861 .reset_list = msm8996_usb3phy_reset_l, 1862 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1863 .vreg_list = qmp_phy_vreg_l, 1864 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1865 .regs = qmp_v5_usb3phy_regs_layout, 1866 .pcs_usb_offset = 0x1000, 1867 1868 .has_pwrdn_delay = true, 1869 }; 1870 1871 static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { 1872 .lanes = 2, 1873 1874 .serdes_tbl = sm8150_usb3_serdes_tbl, 1875 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1876 .tx_tbl = sm8350_usb3_tx_tbl, 1877 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 1878 .rx_tbl = sm8350_usb3_rx_tbl, 1879 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 1880 .pcs_tbl = sm8350_usb3_pcs_tbl, 1881 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 1882 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 1883 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 1884 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1885 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1886 .reset_list = msm8996_usb3phy_reset_l, 1887 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1888 .vreg_list = qmp_phy_vreg_l, 1889 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1890 .regs = qmp_v5_usb3phy_regs_layout, 1891 .pcs_usb_offset = 0x300, 1892 1893 .has_pwrdn_delay = true, 1894 .has_phy_dp_com_ctrl = true, 1895 }; 1896 1897 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { 1898 .lanes = 1, 1899 1900 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1901 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1902 .tx_tbl = sm8350_usb3_uniphy_tx_tbl, 1903 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), 1904 .rx_tbl = sm8350_usb3_uniphy_rx_tbl, 1905 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), 1906 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 1907 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 1908 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, 1909 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), 1910 .clk_list = qmp_v4_ref_phy_clk_l, 1911 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1912 .reset_list = msm8996_usb3phy_reset_l, 1913 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1914 .vreg_list = qmp_phy_vreg_l, 1915 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1916 .regs = qmp_v5_usb3phy_regs_layout, 1917 .pcs_usb_offset = 0x1000, 1918 1919 .has_pwrdn_delay = true, 1920 }; 1921 1922 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { 1923 .lanes = 2, 1924 1925 .serdes_tbl = qcm2290_usb3_serdes_tbl, 1926 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 1927 .tx_tbl = qcm2290_usb3_tx_tbl, 1928 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 1929 .rx_tbl = qcm2290_usb3_rx_tbl, 1930 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 1931 .pcs_tbl = qcm2290_usb3_pcs_tbl, 1932 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 1933 .clk_list = qcm2290_usb3phy_clk_l, 1934 .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), 1935 .reset_list = qcm2290_usb3phy_reset_l, 1936 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 1937 .vreg_list = qmp_phy_vreg_l, 1938 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1939 .regs = qmp_v3_usb3phy_regs_layout, 1940 }; 1941 1942 static void qmp_usb_configure_lane(void __iomem *base, 1943 const struct qmp_phy_init_tbl tbl[], 1944 int num, 1945 u8 lane_mask) 1946 { 1947 int i; 1948 const struct qmp_phy_init_tbl *t = tbl; 1949 1950 if (!t) 1951 return; 1952 1953 for (i = 0; i < num; i++, t++) { 1954 if (!(t->lane_mask & lane_mask)) 1955 continue; 1956 1957 writel(t->val, base + t->offset); 1958 } 1959 } 1960 1961 static void qmp_usb_configure(void __iomem *base, 1962 const struct qmp_phy_init_tbl tbl[], 1963 int num) 1964 { 1965 qmp_usb_configure_lane(base, tbl, num, 0xff); 1966 } 1967 1968 static int qmp_usb_serdes_init(struct qmp_usb *qmp) 1969 { 1970 const struct qmp_phy_cfg *cfg = qmp->cfg; 1971 void __iomem *serdes = qmp->serdes; 1972 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 1973 int serdes_tbl_num = cfg->serdes_tbl_num; 1974 1975 qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num); 1976 1977 return 0; 1978 } 1979 1980 static int qmp_usb_init(struct phy *phy) 1981 { 1982 struct qmp_usb *qmp = phy_get_drvdata(phy); 1983 const struct qmp_phy_cfg *cfg = qmp->cfg; 1984 void __iomem *pcs = qmp->pcs; 1985 void __iomem *dp_com = qmp->dp_com; 1986 int ret; 1987 1988 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 1989 if (ret) { 1990 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 1991 return ret; 1992 } 1993 1994 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 1995 if (ret) { 1996 dev_err(qmp->dev, "reset assert failed\n"); 1997 goto err_disable_regulators; 1998 } 1999 2000 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2001 if (ret) { 2002 dev_err(qmp->dev, "reset deassert failed\n"); 2003 goto err_disable_regulators; 2004 } 2005 2006 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2007 if (ret) 2008 goto err_assert_reset; 2009 2010 if (cfg->has_phy_dp_com_ctrl) { 2011 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, 2012 SW_PWRDN); 2013 /* override hardware control for reset of qmp phy */ 2014 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2015 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2016 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2017 2018 /* Default type-c orientation, i.e CC1 */ 2019 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 2020 2021 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, 2022 USB3_MODE | DP_MODE); 2023 2024 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 2025 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2026 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2027 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2028 2029 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 2030 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2031 } 2032 2033 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 2034 2035 return 0; 2036 2037 err_assert_reset: 2038 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2039 err_disable_regulators: 2040 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2041 2042 return ret; 2043 } 2044 2045 static int qmp_usb_exit(struct phy *phy) 2046 { 2047 struct qmp_usb *qmp = phy_get_drvdata(phy); 2048 const struct qmp_phy_cfg *cfg = qmp->cfg; 2049 2050 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2051 2052 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2053 2054 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2055 2056 return 0; 2057 } 2058 2059 static int qmp_usb_power_on(struct phy *phy) 2060 { 2061 struct qmp_usb *qmp = phy_get_drvdata(phy); 2062 const struct qmp_phy_cfg *cfg = qmp->cfg; 2063 void __iomem *tx = qmp->tx; 2064 void __iomem *rx = qmp->rx; 2065 void __iomem *pcs = qmp->pcs; 2066 void __iomem *status; 2067 unsigned int val; 2068 int ret; 2069 2070 qmp_usb_serdes_init(qmp); 2071 2072 ret = clk_prepare_enable(qmp->pipe_clk); 2073 if (ret) { 2074 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2075 return ret; 2076 } 2077 2078 /* Tx, Rx, and PCS configurations */ 2079 qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2080 qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2081 2082 if (cfg->lanes >= 2) { 2083 qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2084 qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2085 } 2086 2087 qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2088 2089 if (cfg->has_pwrdn_delay) 2090 usleep_range(10, 20); 2091 2092 /* Pull PHY out of reset state */ 2093 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2094 2095 /* start SerDes and Phy-Coding-Sublayer */ 2096 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2097 2098 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2099 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2100 PHY_INIT_COMPLETE_TIMEOUT); 2101 if (ret) { 2102 dev_err(qmp->dev, "phy initialization timed-out\n"); 2103 goto err_disable_pipe_clk; 2104 } 2105 2106 return 0; 2107 2108 err_disable_pipe_clk: 2109 clk_disable_unprepare(qmp->pipe_clk); 2110 2111 return ret; 2112 } 2113 2114 static int qmp_usb_power_off(struct phy *phy) 2115 { 2116 struct qmp_usb *qmp = phy_get_drvdata(phy); 2117 const struct qmp_phy_cfg *cfg = qmp->cfg; 2118 2119 clk_disable_unprepare(qmp->pipe_clk); 2120 2121 /* PHY reset */ 2122 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2123 2124 /* stop SerDes and Phy-Coding-Sublayer */ 2125 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2126 SERDES_START | PCS_START); 2127 2128 /* Put PHY into POWER DOWN state: active low */ 2129 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2130 SW_PWRDN); 2131 2132 return 0; 2133 } 2134 2135 static int qmp_usb_enable(struct phy *phy) 2136 { 2137 int ret; 2138 2139 ret = qmp_usb_init(phy); 2140 if (ret) 2141 return ret; 2142 2143 ret = qmp_usb_power_on(phy); 2144 if (ret) 2145 qmp_usb_exit(phy); 2146 2147 return ret; 2148 } 2149 2150 static int qmp_usb_disable(struct phy *phy) 2151 { 2152 int ret; 2153 2154 ret = qmp_usb_power_off(phy); 2155 if (ret) 2156 return ret; 2157 return qmp_usb_exit(phy); 2158 } 2159 2160 static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2161 { 2162 struct qmp_usb *qmp = phy_get_drvdata(phy); 2163 2164 qmp->mode = mode; 2165 2166 return 0; 2167 } 2168 2169 static const struct phy_ops qmp_usb_phy_ops = { 2170 .init = qmp_usb_enable, 2171 .exit = qmp_usb_disable, 2172 .set_mode = qmp_usb_set_mode, 2173 .owner = THIS_MODULE, 2174 }; 2175 2176 static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp) 2177 { 2178 const struct qmp_phy_cfg *cfg = qmp->cfg; 2179 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2180 void __iomem *pcs_misc = qmp->pcs_misc; 2181 u32 intr_mask; 2182 2183 if (qmp->mode == PHY_MODE_USB_HOST_SS || 2184 qmp->mode == PHY_MODE_USB_DEVICE_SS) 2185 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2186 else 2187 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2188 2189 /* Clear any pending interrupts status */ 2190 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2191 /* Writing 1 followed by 0 clears the interrupt */ 2192 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2193 2194 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2195 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2196 2197 /* Enable required PHY autonomous mode interrupts */ 2198 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2199 2200 /* Enable i/o clamp_n for autonomous mode */ 2201 if (pcs_misc) 2202 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2203 } 2204 2205 static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp) 2206 { 2207 const struct qmp_phy_cfg *cfg = qmp->cfg; 2208 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2209 void __iomem *pcs_misc = qmp->pcs_misc; 2210 2211 /* Disable i/o clamp_n on resume for normal mode */ 2212 if (pcs_misc) 2213 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2214 2215 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2216 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2217 2218 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2219 /* Writing 1 followed by 0 clears the interrupt */ 2220 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2221 } 2222 2223 static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev) 2224 { 2225 struct qmp_usb *qmp = dev_get_drvdata(dev); 2226 const struct qmp_phy_cfg *cfg = qmp->cfg; 2227 2228 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2229 2230 if (!qmp->phy->init_count) { 2231 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2232 return 0; 2233 } 2234 2235 qmp_usb_enable_autonomous_mode(qmp); 2236 2237 clk_disable_unprepare(qmp->pipe_clk); 2238 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2239 2240 return 0; 2241 } 2242 2243 static int __maybe_unused qmp_usb_runtime_resume(struct device *dev) 2244 { 2245 struct qmp_usb *qmp = dev_get_drvdata(dev); 2246 const struct qmp_phy_cfg *cfg = qmp->cfg; 2247 int ret = 0; 2248 2249 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2250 2251 if (!qmp->phy->init_count) { 2252 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2253 return 0; 2254 } 2255 2256 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2257 if (ret) 2258 return ret; 2259 2260 ret = clk_prepare_enable(qmp->pipe_clk); 2261 if (ret) { 2262 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2263 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2264 return ret; 2265 } 2266 2267 qmp_usb_disable_autonomous_mode(qmp); 2268 2269 return 0; 2270 } 2271 2272 static const struct dev_pm_ops qmp_usb_pm_ops = { 2273 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend, 2274 qmp_usb_runtime_resume, NULL) 2275 }; 2276 2277 static int qmp_usb_vreg_init(struct qmp_usb *qmp) 2278 { 2279 const struct qmp_phy_cfg *cfg = qmp->cfg; 2280 struct device *dev = qmp->dev; 2281 int num = cfg->num_vregs; 2282 int i; 2283 2284 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2285 if (!qmp->vregs) 2286 return -ENOMEM; 2287 2288 for (i = 0; i < num; i++) 2289 qmp->vregs[i].supply = cfg->vreg_list[i]; 2290 2291 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2292 } 2293 2294 static int qmp_usb_reset_init(struct qmp_usb *qmp) 2295 { 2296 const struct qmp_phy_cfg *cfg = qmp->cfg; 2297 struct device *dev = qmp->dev; 2298 int i; 2299 int ret; 2300 2301 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2302 sizeof(*qmp->resets), GFP_KERNEL); 2303 if (!qmp->resets) 2304 return -ENOMEM; 2305 2306 for (i = 0; i < cfg->num_resets; i++) 2307 qmp->resets[i].id = cfg->reset_list[i]; 2308 2309 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2310 if (ret) 2311 return dev_err_probe(dev, ret, "failed to get resets\n"); 2312 2313 return 0; 2314 } 2315 2316 static int qmp_usb_clk_init(struct qmp_usb *qmp) 2317 { 2318 const struct qmp_phy_cfg *cfg = qmp->cfg; 2319 struct device *dev = qmp->dev; 2320 int num = cfg->num_clks; 2321 int i; 2322 2323 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2324 if (!qmp->clks) 2325 return -ENOMEM; 2326 2327 for (i = 0; i < num; i++) 2328 qmp->clks[i].id = cfg->clk_list[i]; 2329 2330 return devm_clk_bulk_get(dev, num, qmp->clks); 2331 } 2332 2333 static void phy_clk_release_provider(void *res) 2334 { 2335 of_clk_del_provider(res); 2336 } 2337 2338 /* 2339 * Register a fixed rate pipe clock. 2340 * 2341 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2342 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2343 * by the PHY driver for its operations. 2344 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2345 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2346 * Below picture shows this relationship. 2347 * 2348 * +---------------+ 2349 * | PHY block |<<---------------------------------------+ 2350 * | | | 2351 * | +-------+ | +-----+ | 2352 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2353 * clk | +-------+ | +-----+ 2354 * +---------------+ 2355 */ 2356 static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np) 2357 { 2358 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2359 struct clk_init_data init = { }; 2360 int ret; 2361 2362 ret = of_property_read_string(np, "clock-output-names", &init.name); 2363 if (ret) { 2364 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2365 return ret; 2366 } 2367 2368 init.ops = &clk_fixed_rate_ops; 2369 2370 /* controllers using QMP phys use 125MHz pipe clock interface */ 2371 fixed->fixed_rate = 125000000; 2372 fixed->hw.init = &init; 2373 2374 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2375 if (ret) 2376 return ret; 2377 2378 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2379 if (ret) 2380 return ret; 2381 2382 /* 2383 * Roll a devm action because the clock provider is the child node, but 2384 * the child node is not actually a device. 2385 */ 2386 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2387 } 2388 2389 static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np, 2390 int index, bool exclusive) 2391 { 2392 struct resource res; 2393 2394 if (!exclusive) { 2395 if (of_address_to_resource(np, index, &res)) 2396 return IOMEM_ERR_PTR(-EINVAL); 2397 2398 return devm_ioremap(dev, res.start, resource_size(&res)); 2399 } 2400 2401 return devm_of_iomap(dev, np, index, NULL); 2402 } 2403 2404 static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np) 2405 { 2406 struct platform_device *pdev = to_platform_device(qmp->dev); 2407 const struct qmp_phy_cfg *cfg = qmp->cfg; 2408 struct device *dev = qmp->dev; 2409 bool exclusive = true; 2410 2411 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2412 if (IS_ERR(qmp->serdes)) 2413 return PTR_ERR(qmp->serdes); 2414 2415 if (cfg->has_phy_dp_com_ctrl) { 2416 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 2417 if (IS_ERR(qmp->dp_com)) 2418 return PTR_ERR(qmp->dp_com); 2419 } 2420 2421 /* 2422 * FIXME: These bindings should be fixed to not rely on overlapping 2423 * mappings for PCS. 2424 */ 2425 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy")) 2426 exclusive = false; 2427 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy")) 2428 exclusive = false; 2429 2430 /* 2431 * Get memory resources for the PHY: 2432 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2433 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2434 * For single lane PHYs: pcs_misc (optional) -> 3. 2435 */ 2436 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2437 if (IS_ERR(qmp->tx)) 2438 return PTR_ERR(qmp->tx); 2439 2440 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2441 if (IS_ERR(qmp->rx)) 2442 return PTR_ERR(qmp->rx); 2443 2444 qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive); 2445 if (IS_ERR(qmp->pcs)) 2446 return PTR_ERR(qmp->pcs); 2447 2448 if (cfg->pcs_usb_offset) 2449 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 2450 2451 if (cfg->lanes >= 2) { 2452 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2453 if (IS_ERR(qmp->tx2)) 2454 return PTR_ERR(qmp->tx2); 2455 2456 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2457 if (IS_ERR(qmp->rx2)) 2458 return PTR_ERR(qmp->rx2); 2459 2460 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2461 } else { 2462 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2463 } 2464 2465 if (IS_ERR(qmp->pcs_misc)) { 2466 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2467 qmp->pcs_misc = NULL; 2468 } 2469 2470 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2471 if (IS_ERR(qmp->pipe_clk)) { 2472 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2473 "failed to get pipe clock\n"); 2474 } 2475 2476 return 0; 2477 } 2478 2479 static int qmp_usb_parse_dt(struct qmp_usb *qmp) 2480 { 2481 struct platform_device *pdev = to_platform_device(qmp->dev); 2482 const struct qmp_phy_cfg *cfg = qmp->cfg; 2483 const struct qmp_usb_offsets *offs = cfg->offsets; 2484 struct device *dev = qmp->dev; 2485 void __iomem *base; 2486 2487 if (!offs) 2488 return -EINVAL; 2489 2490 base = devm_platform_ioremap_resource(pdev, 0); 2491 if (IS_ERR(base)) 2492 return PTR_ERR(base); 2493 2494 qmp->serdes = base + offs->serdes; 2495 qmp->pcs = base + offs->pcs; 2496 qmp->pcs_usb = base + offs->pcs_usb; 2497 qmp->tx = base + offs->tx; 2498 qmp->rx = base + offs->rx; 2499 2500 qmp->pipe_clk = devm_clk_get(dev, "pipe"); 2501 if (IS_ERR(qmp->pipe_clk)) { 2502 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2503 "failed to get pipe clock\n"); 2504 } 2505 2506 return 0; 2507 } 2508 2509 static int qmp_usb_probe(struct platform_device *pdev) 2510 { 2511 struct device *dev = &pdev->dev; 2512 struct phy_provider *phy_provider; 2513 struct device_node *np; 2514 struct qmp_usb *qmp; 2515 int ret; 2516 2517 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2518 if (!qmp) 2519 return -ENOMEM; 2520 2521 qmp->dev = dev; 2522 2523 qmp->cfg = of_device_get_match_data(dev); 2524 if (!qmp->cfg) 2525 return -EINVAL; 2526 2527 ret = qmp_usb_clk_init(qmp); 2528 if (ret) 2529 return ret; 2530 2531 ret = qmp_usb_reset_init(qmp); 2532 if (ret) 2533 return ret; 2534 2535 ret = qmp_usb_vreg_init(qmp); 2536 if (ret) 2537 return ret; 2538 2539 /* Check for legacy binding with child node. */ 2540 np = of_get_next_available_child(dev->of_node, NULL); 2541 if (np) { 2542 ret = qmp_usb_parse_dt_legacy(qmp, np); 2543 } else { 2544 np = of_node_get(dev->of_node); 2545 ret = qmp_usb_parse_dt(qmp); 2546 } 2547 if (ret) 2548 goto err_node_put; 2549 2550 pm_runtime_set_active(dev); 2551 ret = devm_pm_runtime_enable(dev); 2552 if (ret) 2553 goto err_node_put; 2554 /* 2555 * Prevent runtime pm from being ON by default. Users can enable 2556 * it using power/control in sysfs. 2557 */ 2558 pm_runtime_forbid(dev); 2559 2560 ret = phy_pipe_clk_register(qmp, np); 2561 if (ret) 2562 goto err_node_put; 2563 2564 qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops); 2565 if (IS_ERR(qmp->phy)) { 2566 ret = PTR_ERR(qmp->phy); 2567 dev_err(dev, "failed to create PHY: %d\n", ret); 2568 goto err_node_put; 2569 } 2570 2571 phy_set_drvdata(qmp->phy, qmp); 2572 2573 of_node_put(np); 2574 2575 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2576 2577 return PTR_ERR_OR_ZERO(phy_provider); 2578 2579 err_node_put: 2580 of_node_put(np); 2581 return ret; 2582 } 2583 2584 static const struct of_device_id qmp_usb_of_match_table[] = { 2585 { 2586 .compatible = "qcom,ipq6018-qmp-usb3-phy", 2587 .data = &ipq8074_usb3phy_cfg, 2588 }, { 2589 .compatible = "qcom,ipq8074-qmp-usb3-phy", 2590 .data = &ipq8074_usb3phy_cfg, 2591 }, { 2592 .compatible = "qcom,msm8996-qmp-usb3-phy", 2593 .data = &msm8996_usb3phy_cfg, 2594 }, { 2595 .compatible = "qcom,msm8998-qmp-usb3-phy", 2596 .data = &msm8998_usb3phy_cfg, 2597 }, { 2598 .compatible = "qcom,qcm2290-qmp-usb3-phy", 2599 .data = &qcm2290_usb3phy_cfg, 2600 }, { 2601 .compatible = "qcom,sc7180-qmp-usb3-phy", 2602 .data = &sc7180_usb3phy_cfg, 2603 }, { 2604 .compatible = "qcom,sc8180x-qmp-usb3-phy", 2605 .data = &sm8150_usb3phy_cfg, 2606 }, { 2607 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy", 2608 .data = &sc8280xp_usb3_uniphy_cfg, 2609 }, { 2610 .compatible = "qcom,sdm845-qmp-usb3-phy", 2611 .data = &qmp_v3_usb3phy_cfg, 2612 }, { 2613 .compatible = "qcom,sdm845-qmp-usb3-uni-phy", 2614 .data = &qmp_v3_usb3_uniphy_cfg, 2615 }, { 2616 .compatible = "qcom,sdx55-qmp-usb3-uni-phy", 2617 .data = &sdx55_usb3_uniphy_cfg, 2618 }, { 2619 .compatible = "qcom,sdx65-qmp-usb3-uni-phy", 2620 .data = &sdx65_usb3_uniphy_cfg, 2621 }, { 2622 .compatible = "qcom,sm6115-qmp-usb3-phy", 2623 .data = &qcm2290_usb3phy_cfg, 2624 }, { 2625 .compatible = "qcom,sm8150-qmp-usb3-phy", 2626 .data = &sm8150_usb3phy_cfg, 2627 }, { 2628 .compatible = "qcom,sm8150-qmp-usb3-uni-phy", 2629 .data = &sm8150_usb3_uniphy_cfg, 2630 }, { 2631 .compatible = "qcom,sm8250-qmp-usb3-phy", 2632 .data = &sm8250_usb3phy_cfg, 2633 }, { 2634 .compatible = "qcom,sm8250-qmp-usb3-uni-phy", 2635 .data = &sm8250_usb3_uniphy_cfg, 2636 }, { 2637 .compatible = "qcom,sm8350-qmp-usb3-phy", 2638 .data = &sm8350_usb3phy_cfg, 2639 }, { 2640 .compatible = "qcom,sm8350-qmp-usb3-uni-phy", 2641 .data = &sm8350_usb3_uniphy_cfg, 2642 }, { 2643 .compatible = "qcom,sm8450-qmp-usb3-phy", 2644 .data = &sm8350_usb3phy_cfg, 2645 }, 2646 { }, 2647 }; 2648 MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table); 2649 2650 static struct platform_driver qmp_usb_driver = { 2651 .probe = qmp_usb_probe, 2652 .driver = { 2653 .name = "qcom-qmp-usb-phy", 2654 .pm = &qmp_usb_pm_ops, 2655 .of_match_table = qmp_usb_of_match_table, 2656 }, 2657 }; 2658 2659 module_platform_driver(qmp_usb_driver); 2660 2661 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2662 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver"); 2663 MODULE_LICENSE("GPL v2"); 2664