1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #include <linux/clk.h> 7 #include <linux/clk-provider.h> 8 #include <linux/delay.h> 9 #include <linux/err.h> 10 #include <linux/io.h> 11 #include <linux/iopoll.h> 12 #include <linux/kernel.h> 13 #include <linux/module.h> 14 #include <linux/of.h> 15 #include <linux/of_device.h> 16 #include <linux/of_address.h> 17 #include <linux/phy/phy.h> 18 #include <linux/platform_device.h> 19 #include <linux/regulator/consumer.h> 20 #include <linux/reset.h> 21 #include <linux/slab.h> 22 23 #include "phy-qcom-qmp.h" 24 #include "phy-qcom-qmp-pcs-misc-v3.h" 25 #include "phy-qcom-qmp-pcs-usb-v4.h" 26 #include "phy-qcom-qmp-pcs-usb-v5.h" 27 28 /* QPHY_SW_RESET bit */ 29 #define SW_RESET BIT(0) 30 /* QPHY_POWER_DOWN_CONTROL */ 31 #define SW_PWRDN BIT(0) 32 /* QPHY_START_CONTROL bits */ 33 #define SERDES_START BIT(0) 34 #define PCS_START BIT(1) 35 /* QPHY_PCS_STATUS bit */ 36 #define PHYSTATUS BIT(6) 37 38 /* QPHY_V3_DP_COM_RESET_OVRD_CTRL register bits */ 39 /* DP PHY soft reset */ 40 #define SW_DPPHY_RESET BIT(0) 41 /* mux to select DP PHY reset control, 0:HW control, 1: software reset */ 42 #define SW_DPPHY_RESET_MUX BIT(1) 43 /* USB3 PHY soft reset */ 44 #define SW_USB3PHY_RESET BIT(2) 45 /* mux to select USB3 PHY reset control, 0:HW control, 1: software reset */ 46 #define SW_USB3PHY_RESET_MUX BIT(3) 47 48 /* QPHY_V3_DP_COM_PHY_MODE_CTRL register bits */ 49 #define USB3_MODE BIT(0) /* enables USB3 mode */ 50 #define DP_MODE BIT(1) /* enables DP mode */ 51 52 /* QPHY_PCS_AUTONOMOUS_MODE_CTRL register bits */ 53 #define ARCVR_DTCT_EN BIT(0) 54 #define ALFPS_DTCT_EN BIT(1) 55 #define ARCVR_DTCT_EVENT_SEL BIT(4) 56 57 /* QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR register bits */ 58 #define IRQ_CLEAR BIT(0) 59 60 /* QPHY_V3_PCS_MISC_CLAMP_ENABLE register bits */ 61 #define CLAMP_EN BIT(0) /* enables i/o clamp_n */ 62 63 #define PHY_INIT_COMPLETE_TIMEOUT 10000 64 65 struct qmp_phy_init_tbl { 66 unsigned int offset; 67 unsigned int val; 68 /* 69 * mask of lanes for which this register is written 70 * for cases when second lane needs different values 71 */ 72 u8 lane_mask; 73 }; 74 75 #define QMP_PHY_INIT_CFG(o, v) \ 76 { \ 77 .offset = o, \ 78 .val = v, \ 79 .lane_mask = 0xff, \ 80 } 81 82 #define QMP_PHY_INIT_CFG_LANE(o, v, l) \ 83 { \ 84 .offset = o, \ 85 .val = v, \ 86 .lane_mask = l, \ 87 } 88 89 /* set of registers with offsets different per-PHY */ 90 enum qphy_reg_layout { 91 /* PCS registers */ 92 QPHY_SW_RESET, 93 QPHY_START_CTRL, 94 QPHY_PCS_STATUS, 95 QPHY_PCS_AUTONOMOUS_MODE_CTRL, 96 QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR, 97 QPHY_PCS_POWER_DOWN_CONTROL, 98 /* Keep last to ensure regs_layout arrays are properly initialized */ 99 QPHY_LAYOUT_SIZE 100 }; 101 102 static const unsigned int qmp_v2_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 103 [QPHY_SW_RESET] = QPHY_V2_PCS_SW_RESET, 104 [QPHY_START_CTRL] = QPHY_V2_PCS_START_CONTROL, 105 [QPHY_PCS_STATUS] = QPHY_V2_PCS_USB_PCS_STATUS, 106 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V2_PCS_AUTONOMOUS_MODE_CTRL, 107 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V2_PCS_LFPS_RXTERM_IRQ_CLEAR, 108 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V2_PCS_POWER_DOWN_CONTROL, 109 }; 110 111 static const unsigned int qmp_v3_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 112 [QPHY_SW_RESET] = QPHY_V3_PCS_SW_RESET, 113 [QPHY_START_CTRL] = QPHY_V3_PCS_START_CONTROL, 114 [QPHY_PCS_STATUS] = QPHY_V3_PCS_PCS_STATUS, 115 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V3_PCS_AUTONOMOUS_MODE_CTRL, 116 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V3_PCS_LFPS_RXTERM_IRQ_CLEAR, 117 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V3_PCS_POWER_DOWN_CONTROL, 118 }; 119 120 static const unsigned int qmp_v4_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 121 [QPHY_SW_RESET] = QPHY_V4_PCS_SW_RESET, 122 [QPHY_START_CTRL] = QPHY_V4_PCS_START_CONTROL, 123 [QPHY_PCS_STATUS] = QPHY_V4_PCS_PCS_STATUS1, 124 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V4_PCS_POWER_DOWN_CONTROL, 125 126 /* In PCS_USB */ 127 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V4_PCS_USB3_AUTONOMOUS_MODE_CTRL, 128 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V4_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 129 }; 130 131 static const unsigned int qmp_v5_usb3phy_regs_layout[QPHY_LAYOUT_SIZE] = { 132 [QPHY_SW_RESET] = QPHY_V5_PCS_SW_RESET, 133 [QPHY_START_CTRL] = QPHY_V5_PCS_START_CONTROL, 134 [QPHY_PCS_STATUS] = QPHY_V5_PCS_PCS_STATUS1, 135 [QPHY_PCS_POWER_DOWN_CONTROL] = QPHY_V5_PCS_POWER_DOWN_CONTROL, 136 137 /* In PCS_USB */ 138 [QPHY_PCS_AUTONOMOUS_MODE_CTRL] = QPHY_V5_PCS_USB3_AUTONOMOUS_MODE_CTRL, 139 [QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR] = QPHY_V5_PCS_USB3_LFPS_RXTERM_IRQ_CLEAR, 140 }; 141 142 static const struct qmp_phy_init_tbl ipq9574_usb3_serdes_tbl[] = { 143 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), 144 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 145 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 146 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 147 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 148 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 149 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 150 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 151 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 152 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 153 /* PLL and Loop filter settings */ 154 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x68), 155 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0xab), 156 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0xaa), 157 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x02), 158 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x09), 159 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 160 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 161 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0xa0), 162 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0xaa), 163 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x29), 164 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 165 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 166 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 167 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 168 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 169 /* SSC settings */ 170 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 171 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x7d), 172 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 173 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 174 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 175 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0x0a), 176 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x05), 177 }; 178 179 static const struct qmp_phy_init_tbl ipq9574_usb3_tx_tbl[] = { 180 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 181 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 182 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 183 }; 184 185 static const struct qmp_phy_init_tbl ipq9574_usb3_rx_tbl[] = { 186 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), 187 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 188 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x6c), 189 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 190 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), 191 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 192 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 193 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 194 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 195 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0c), 196 }; 197 198 static const struct qmp_phy_init_tbl ipq9574_usb3_pcs_tbl[] = { 199 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 200 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 201 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 202 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 203 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 204 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 205 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 206 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 207 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 208 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 209 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 210 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 211 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 212 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 213 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 214 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 215 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 216 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 217 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 218 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 219 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 220 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 221 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 222 }; 223 224 static const struct qmp_phy_init_tbl ipq8074_usb3_serdes_tbl[] = { 225 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x1a), 226 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 227 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 228 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 229 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 230 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 231 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 232 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 233 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 234 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 235 /* PLL and Loop filter settings */ 236 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 237 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 238 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 239 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 240 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 241 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 242 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 243 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 244 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 245 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 246 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 247 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 248 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 249 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 250 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 251 /* SSC settings */ 252 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 253 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 254 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 255 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 256 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 257 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 258 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 259 }; 260 261 static const struct qmp_phy_init_tbl ipq8074_usb3_rx_tbl[] = { 262 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x06), 263 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 264 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 265 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xb8), 266 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 267 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 268 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 269 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 270 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_ENABLES, 0x0), 271 }; 272 273 static const struct qmp_phy_init_tbl ipq8074_usb3_pcs_tbl[] = { 274 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 275 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0e), 276 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 277 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 278 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 279 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 280 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 281 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 282 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 283 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 284 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 285 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 286 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 287 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 288 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 289 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 290 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 291 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 292 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 293 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 294 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 295 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 296 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 297 }; 298 299 static const struct qmp_phy_init_tbl msm8996_usb3_serdes_tbl[] = { 300 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 301 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 302 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 303 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 304 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 305 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 306 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 307 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 308 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x04), 309 /* PLL and Loop filter settings */ 310 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 311 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 312 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 313 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 314 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 315 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 316 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 317 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 318 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_CTRL, 0x00), 319 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 320 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 321 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 322 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 323 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 324 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 325 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 326 /* SSC settings */ 327 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 328 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 329 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 330 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 331 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 332 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 333 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 334 }; 335 336 static const struct qmp_phy_init_tbl msm8996_usb3_tx_tbl[] = { 337 QMP_PHY_INIT_CFG(QSERDES_TX_HIGHZ_TRANSCEIVEREN_BIAS_DRVR_EN, 0x45), 338 QMP_PHY_INIT_CFG(QSERDES_TX_RCV_DETECT_LVL_2, 0x12), 339 QMP_PHY_INIT_CFG(QSERDES_TX_LANE_MODE, 0x06), 340 }; 341 342 static const struct qmp_phy_init_tbl msm8996_usb3_rx_tbl[] = { 343 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 344 QMP_PHY_INIT_CFG(QSERDES_RX_UCDR_SO_GAIN, 0x04), 345 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 346 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4c), 347 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQU_ADAPTOR_CNTRL4, 0xbb), 348 QMP_PHY_INIT_CFG(QSERDES_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 349 QMP_PHY_INIT_CFG(QSERDES_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 350 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_CNTRL, 0x03), 351 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_LVL, 0x18), 352 QMP_PHY_INIT_CFG(QSERDES_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 353 }; 354 355 static const struct qmp_phy_init_tbl msm8996_usb3_pcs_tbl[] = { 356 /* FLL settings */ 357 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL2, 0x03), 358 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNTRL1, 0x02), 359 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_L, 0x09), 360 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_CNT_VAL_H_TOL, 0x42), 361 QMP_PHY_INIT_CFG(QPHY_V2_PCS_FLL_MAN_CODE, 0x85), 362 363 /* Lock Det settings */ 364 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG1, 0xd1), 365 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG2, 0x1f), 366 QMP_PHY_INIT_CFG(QPHY_V2_PCS_LOCK_DETECT_CONFIG3, 0x47), 367 QMP_PHY_INIT_CFG(QPHY_V2_PCS_POWER_STATE_CONFIG2, 0x08), 368 }; 369 370 static const struct qmp_phy_init_tbl qmp_v3_usb3_serdes_tbl[] = { 371 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 372 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 373 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 374 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 375 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 376 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 377 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x16), 378 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 379 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 380 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 381 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 382 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 383 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 384 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 385 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 386 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 387 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 388 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 389 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 390 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 391 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 392 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 393 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 394 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 395 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 396 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 397 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 398 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 399 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 400 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 401 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 402 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 403 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 404 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 405 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 406 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 407 }; 408 409 static const struct qmp_phy_init_tbl qmp_v3_usb3_tx_tbl[] = { 410 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 411 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 412 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 413 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x09), 414 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 415 }; 416 417 static const struct qmp_phy_init_tbl qmp_v3_usb3_rx_tbl[] = { 418 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 419 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 420 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 421 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 422 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 423 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 424 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 425 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 426 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 427 }; 428 429 static const struct qmp_phy_init_tbl qmp_v3_usb3_pcs_tbl[] = { 430 /* FLL settings */ 431 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 432 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 433 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 434 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 435 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 436 437 /* Lock Det settings */ 438 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 439 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 440 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 441 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 442 443 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 444 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 445 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 446 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 447 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 448 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 449 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 450 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 451 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 452 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 453 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 454 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 455 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 456 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 457 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 458 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 459 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 460 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 461 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 462 463 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 464 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 465 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 466 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 467 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 468 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 469 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 470 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 471 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 472 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 473 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 474 }; 475 476 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_serdes_tbl[] = { 477 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 478 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 479 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 480 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 481 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x02), 482 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 483 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 484 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 485 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 486 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 487 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 488 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 489 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 490 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 491 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 492 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 493 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 494 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 495 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 496 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 497 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 498 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 499 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 500 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 501 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 502 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 503 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 504 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 505 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_BUF_ENABLE, 0x0a), 506 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 507 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 508 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 509 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 510 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 511 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 512 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 513 }; 514 515 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_tx_tbl[] = { 516 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 517 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 518 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 519 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x06), 520 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x06), 521 }; 522 523 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_rx_tbl[] = { 524 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0c), 525 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x50), 526 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 527 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0e), 528 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 529 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 530 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 531 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 532 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 533 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 534 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 535 }; 536 537 static const struct qmp_phy_init_tbl qmp_v3_usb3_uniphy_pcs_tbl[] = { 538 /* FLL settings */ 539 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 540 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 541 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 542 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 543 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 544 545 /* Lock Det settings */ 546 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 547 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 548 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 549 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 550 551 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0xba), 552 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 553 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 554 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb5), 555 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4c), 556 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x64), 557 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6a), 558 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 559 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 560 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 561 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 562 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 563 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 564 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 565 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x1d), 566 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 567 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 568 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 569 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 570 571 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 572 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 573 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 574 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 575 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 576 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 577 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 578 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 579 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 580 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 581 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 582 583 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG1, 0x21), 584 QMP_PHY_INIT_CFG(QPHY_V3_PCS_REFGEN_REQ_CONFIG2, 0x60), 585 }; 586 587 static const struct qmp_phy_init_tbl msm8998_usb3_serdes_tbl[] = { 588 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30), 589 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x04), 590 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYSCLK_EN_SEL, 0x14), 591 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SYS_CLK_CTRL, 0x06), 592 QMP_PHY_INIT_CFG(QSERDES_V3_COM_RESETSM_CNTRL2, 0x08), 593 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_CONFIG, 0x06), 594 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SVS_MODE_CLK_SEL, 0x01), 595 QMP_PHY_INIT_CFG(QSERDES_V3_COM_HSCLK_SEL, 0x80), 596 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DEC_START_MODE0, 0x82), 597 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START1_MODE0, 0xab), 598 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START2_MODE0, 0xea), 599 QMP_PHY_INIT_CFG(QSERDES_V3_COM_DIV_FRAC_START3_MODE0, 0x02), 600 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CP_CTRL_MODE0, 0x06), 601 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_RCTRL_MODE0, 0x16), 602 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_CCTRL_MODE0, 0x36), 603 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 604 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_GAIN0_MODE0, 0x3f), 605 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE2_MODE0, 0x01), 606 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE1_MODE0, 0xc9), 607 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORECLK_DIV_MODE0, 0x0a), 608 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP3_MODE0, 0x00), 609 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP2_MODE0, 0x34), 610 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP1_MODE0, 0x15), 611 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_EN, 0x04), 612 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CORE_CLK_EN, 0x00), 613 QMP_PHY_INIT_CFG(QSERDES_V3_COM_LOCK_CMP_CFG, 0x00), 614 QMP_PHY_INIT_CFG(QSERDES_V3_COM_VCO_TUNE_MAP, 0x00), 615 QMP_PHY_INIT_CFG(QSERDES_V3_COM_BG_TIMER, 0x0a), 616 QMP_PHY_INIT_CFG(QSERDES_V3_COM_PLL_IVCO, 0x07), 617 QMP_PHY_INIT_CFG(QSERDES_V3_COM_INTEGLOOP_INITVAL, 0x80), 618 QMP_PHY_INIT_CFG(QSERDES_V3_COM_CMN_MODE, 0x01), 619 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_EN_CENTER, 0x01), 620 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER1, 0x31), 621 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_PER2, 0x01), 622 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER1, 0x00), 623 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_ADJ_PER2, 0x00), 624 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE1, 0x85), 625 QMP_PHY_INIT_CFG(QSERDES_V3_COM_SSC_STEP_SIZE2, 0x07), 626 }; 627 628 static const struct qmp_phy_init_tbl msm8998_usb3_tx_tbl[] = { 629 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 630 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 631 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0x16), 632 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 633 }; 634 635 static const struct qmp_phy_init_tbl msm8998_usb3_rx_tbl[] = { 636 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 637 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 638 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 639 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 640 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x07), 641 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 642 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x43), 643 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x1c), 644 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 645 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 646 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 647 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 648 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 649 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 650 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 651 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x03), 652 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x05), 653 }; 654 655 static const struct qmp_phy_init_tbl msm8998_usb3_pcs_tbl[] = { 656 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 657 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 658 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 659 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x40), 660 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 661 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 662 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 663 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 664 QMP_PHY_INIT_CFG(QPHY_V3_PCS_POWER_STATE_CONFIG2, 0x1b), 665 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 666 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V1, 0x9f), 667 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V2, 0xb7), 668 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V3, 0x4e), 669 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V4, 0x65), 670 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_LS, 0x6b), 671 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x15), 672 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0d), 673 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V1, 0x15), 674 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V1, 0x0d), 675 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V2, 0x15), 676 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V2, 0x0d), 677 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V3, 0x15), 678 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V3, 0x0d), 679 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V4, 0x15), 680 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V4, 0x0d), 681 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_LS, 0x15), 682 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_LS, 0x0d), 683 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RATE_SLEW_CNTRL, 0x02), 684 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 685 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 686 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 687 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 688 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 689 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 690 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x8a), 691 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 692 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 693 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 694 }; 695 696 static const struct qmp_phy_init_tbl sm8150_usb3_serdes_tbl[] = { 697 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 698 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 699 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 700 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 701 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 702 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 703 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 704 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 705 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 706 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 707 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 708 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 709 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 710 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 711 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 712 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 713 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 714 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 715 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 716 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 717 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 718 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 719 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 720 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 721 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 722 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 723 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 724 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 725 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 726 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 727 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 728 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 729 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 730 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 731 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 732 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 733 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 734 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 735 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 736 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 737 }; 738 739 static const struct qmp_phy_init_tbl sm8150_usb3_tx_tbl[] = { 740 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x00), 741 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x00), 742 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 743 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 744 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 745 }; 746 747 static const struct qmp_phy_init_tbl sm8150_usb3_rx_tbl[] = { 748 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 749 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 750 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 751 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 752 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 753 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 754 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 755 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 756 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 757 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 758 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 759 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0e), 760 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 761 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 762 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 763 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 764 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 765 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 766 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 767 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 768 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xbf), 769 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xbf), 770 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x3f), 771 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 772 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x94), 773 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 774 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 775 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 776 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 777 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 778 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 779 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 780 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 781 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 782 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 783 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 784 }; 785 786 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_tbl[] = { 787 /* Lock Det settings */ 788 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 789 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 790 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 791 792 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 793 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 794 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 795 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 796 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 797 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 798 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 799 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 800 }; 801 802 static const struct qmp_phy_init_tbl sm8150_usb3_pcs_usb_tbl[] = { 803 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 804 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 805 }; 806 807 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_serdes_tbl[] = { 808 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_EN_SEL, 0x1a), 809 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 810 QMP_PHY_INIT_CFG(QSERDES_V4_COM_HSCLK_SEL, 0x01), 811 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE0, 0x82), 812 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE0, 0xab), 813 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE0, 0xea), 814 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE0, 0x02), 815 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 816 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 817 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE0, 0x06), 818 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE0, 0x16), 819 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE0, 0x36), 820 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE0, 0x24), 821 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE0, 0x34), 822 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE0, 0x14), 823 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP_EN, 0x04), 824 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SYSCLK_BUF_ENABLE, 0x0a), 825 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE2_MODE1, 0x02), 826 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE1_MODE1, 0x24), 827 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CORECLK_DIV_MODE1, 0x08), 828 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DEC_START_MODE1, 0x82), 829 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START1_MODE1, 0xab), 830 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START2_MODE1, 0xea), 831 QMP_PHY_INIT_CFG(QSERDES_V4_COM_DIV_FRAC_START3_MODE1, 0x02), 832 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP2_MODE1, 0x82), 833 QMP_PHY_INIT_CFG(QSERDES_V4_COM_LOCK_CMP1_MODE1, 0x34), 834 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CP_CTRL_MODE1, 0x06), 835 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_RCTRL_MODE1, 0x16), 836 QMP_PHY_INIT_CFG(QSERDES_V4_COM_PLL_CCTRL_MODE1, 0x36), 837 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 838 QMP_PHY_INIT_CFG(QSERDES_V4_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 839 QMP_PHY_INIT_CFG(QSERDES_V4_COM_CMN_IPTRIM, 0x20), 840 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_EN_CENTER, 0x01), 841 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER1, 0x31), 842 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_PER2, 0x01), 843 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE1, 0xde), 844 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE1, 0x07), 845 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE1_MODE0, 0xde), 846 QMP_PHY_INIT_CFG(QSERDES_V4_COM_SSC_STEP_SIZE2_MODE0, 0x07), 847 QMP_PHY_INIT_CFG(QSERDES_V4_COM_VCO_TUNE_MAP, 0x02), 848 }; 849 850 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_tx_tbl[] = { 851 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 852 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0x95), 853 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 854 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x05), 855 }; 856 857 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_rx_tbl[] = { 858 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 859 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 860 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x37), 861 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x2f), 862 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0xef), 863 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb3), 864 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x0b), 865 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 866 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 867 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 868 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 869 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 870 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 871 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 872 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 873 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 874 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 875 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 876 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 877 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x08), 878 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 879 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 880 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 881 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 882 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 883 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 884 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 885 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 886 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 887 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 888 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 889 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 890 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 891 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x20), 892 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x04), 893 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 894 }; 895 896 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_tbl[] = { 897 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 898 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 899 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 900 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 901 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 902 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 903 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 904 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0f), 905 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 906 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 907 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 908 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 909 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 910 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 911 }; 912 913 static const struct qmp_phy_init_tbl sm8150_usb3_uniphy_pcs_usb_tbl[] = { 914 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 915 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 916 }; 917 918 static const struct qmp_phy_init_tbl sm8250_usb3_tx_tbl[] = { 919 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_TX, 0x60), 920 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_RX, 0x60), 921 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 922 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 923 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 924 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 925 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x40, 1), 926 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_TX_PI_QEC_CTRL, 0x54, 2), 927 }; 928 929 static const struct qmp_phy_init_tbl sm8250_usb3_rx_tbl[] = { 930 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 931 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 932 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 933 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 934 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 935 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 936 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 937 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 938 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 939 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 940 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 941 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 942 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 943 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 944 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 945 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 946 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 947 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 948 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 949 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 950 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0xff, 1), 951 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f, 2), 952 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f, 1), 953 QMP_PHY_INIT_CFG_LANE(QSERDES_V4_RX_RX_MODE_00_HIGH, 0xff, 2), 954 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0x7f), 955 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 956 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x97), 957 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 958 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 959 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 960 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 961 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 962 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 963 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 964 QMP_PHY_INIT_CFG(QSERDES_V4_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 965 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 966 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 967 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VTH_CODE, 0x10), 968 }; 969 970 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_tbl[] = { 971 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 972 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 973 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 974 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 975 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 976 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 977 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 978 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 979 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 980 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 981 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 982 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 983 }; 984 985 static const struct qmp_phy_init_tbl sm8250_usb3_pcs_usb_tbl[] = { 986 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 987 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 988 }; 989 990 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_tx_tbl[] = { 991 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 992 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 993 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x82), 994 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x40), 995 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x11), 996 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_RX, 0x02), 997 }; 998 999 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_rx_tbl[] = { 1000 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0xb8), 1001 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0xff), 1002 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 1003 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 1004 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 1005 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 1006 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 1007 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 1008 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 1009 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 1010 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 1011 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x04), 1012 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 1013 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x05), 1014 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x05), 1015 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1016 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1017 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1018 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1019 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x0a), 1020 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 1021 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 1022 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1023 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1024 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1025 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1026 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1027 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1028 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 1029 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1030 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1031 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1032 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1033 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x06), 1034 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1035 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 1036 }; 1037 1038 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_tbl[] = { 1039 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1040 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1041 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1042 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1043 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1044 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1045 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xa9), 1046 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1047 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1048 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1049 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1050 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1051 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1052 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1053 }; 1054 1055 static const struct qmp_phy_init_tbl sm8250_usb3_uniphy_pcs_usb_tbl[] = { 1056 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1057 QMP_PHY_INIT_CFG(QPHY_V4_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1058 }; 1059 1060 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_tx_tbl[] = { 1061 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RCV_DETECT_LVL_2, 0x12), 1062 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_1, 0xd5), 1063 QMP_PHY_INIT_CFG(QSERDES_V4_TX_LANE_MODE_2, 0x80), 1064 QMP_PHY_INIT_CFG(QSERDES_V4_TX_PI_QEC_CTRL, 0x20), 1065 QMP_PHY_INIT_CFG(QSERDES_V4_TX_RES_CODE_LANE_OFFSET_TX, 0x08), 1066 }; 1067 1068 static const struct qmp_phy_init_tbl sdx55_usb3_uniphy_rx_tbl[] = { 1069 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH4, 0x26), 1070 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH3, 0x7f), 1071 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH2, 0xbf), 1072 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_HIGH, 0x7f), 1073 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_00_LOW, 0x7f), 1074 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH4, 0xb4), 1075 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH3, 0x7b), 1076 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH2, 0x5c), 1077 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_HIGH, 0xdc), 1078 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_MODE_01_LOW, 0xdc), 1079 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_PI_CONTROLS, 0x99), 1080 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH1, 0x048), 1081 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_THRESH2, 0x08), 1082 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN1, 0x00), 1083 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SB2_GAIN2, 0x04), 1084 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1085 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1086 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1087 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1088 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_FO_GAIN, 0x09), 1089 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL1, 0x54), 1090 QMP_PHY_INIT_CFG(QSERDES_V4_RX_VGA_CAL_CNTRL2, 0x0c), 1091 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1092 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1093 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1094 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_EN_TIMER, 0x04), 1095 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1096 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1097 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_CNTRL, 0x04), 1098 QMP_PHY_INIT_CFG(QSERDES_V4_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1099 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1100 QMP_PHY_INIT_CFG(QSERDES_V4_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1101 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1102 QMP_PHY_INIT_CFG(QSERDES_V4_RX_UCDR_SO_GAIN, 0x05), 1103 QMP_PHY_INIT_CFG(QSERDES_V4_RX_DCC_CTRL1, 0x0c), 1104 QMP_PHY_INIT_CFG(QSERDES_V4_RX_GM_CAL, 0x1f), 1105 }; 1106 1107 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_tx_tbl[] = { 1108 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1109 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1110 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1111 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1112 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1113 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x1f), 1114 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0b), 1115 }; 1116 1117 static const struct qmp_phy_init_tbl sdx65_usb3_uniphy_rx_tbl[] = { 1118 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 1119 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1120 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1121 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1122 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1123 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1124 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1125 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1126 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1127 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1128 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1129 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1130 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1131 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1132 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1133 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1134 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1135 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1136 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1137 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1138 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1139 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1140 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1141 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1142 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1143 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1144 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1145 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1146 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1147 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1148 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1149 }; 1150 1151 static const struct qmp_phy_init_tbl sm8350_usb3_tx_tbl[] = { 1152 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_TX, 0x00), 1153 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_RX, 0x00), 1154 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x16), 1155 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1156 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0x35), 1157 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1158 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x7f), 1159 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_5, 0x3f), 1160 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RCV_DETECT_LVL_2, 0x12), 1161 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1162 }; 1163 1164 static const struct qmp_phy_init_tbl sm8350_usb3_rx_tbl[] = { 1165 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1166 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1167 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1168 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x7f), 1169 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1170 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1171 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1172 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1173 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1174 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1175 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1176 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1177 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1178 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1179 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4a), 1180 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1181 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW, 0xc0), 1182 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH, 0x00), 1183 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1184 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1185 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1186 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xbb), 1187 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7b), 1188 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xbb), 1189 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3d, 1), 1190 QMP_PHY_INIT_CFG_LANE(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0x3c, 2), 1191 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdb), 1192 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1193 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1194 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xd2), 1195 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x13), 1196 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1197 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_EN_TIMER, 0x04), 1198 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1199 QMP_PHY_INIT_CFG(QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE, 0xa0), 1200 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DCC_CTRL1, 0x0c), 1201 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1202 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VTH_CODE, 0x10), 1203 }; 1204 1205 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_tbl[] = { 1206 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1207 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1208 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1209 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1210 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1211 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1212 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1213 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1214 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1215 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1216 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1217 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1218 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1219 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1220 }; 1221 1222 static const struct qmp_phy_init_tbl sm8350_usb3_pcs_usb_tbl[] = { 1223 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_L, 0x40), 1224 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RCVR_DTCT_DLY_U3_H, 0x00), 1225 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1226 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1227 }; 1228 1229 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_tx_tbl[] = { 1230 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1231 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1232 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1233 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1234 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1235 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 1236 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1237 }; 1238 1239 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_rx_tbl[] = { 1240 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), 1241 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1242 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1243 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1244 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1245 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1246 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1247 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1248 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1249 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1250 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1251 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1252 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1253 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1254 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1255 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1256 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1257 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1258 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FO_GAIN, 0x0a), 1259 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1260 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1261 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1262 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1263 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1264 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1265 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1266 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1267 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1268 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1269 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1270 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1271 }; 1272 1273 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_tbl[] = { 1274 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1275 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG2, 0x07), 1276 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG3, 0x20), 1277 QMP_PHY_INIT_CFG(QPHY_V4_PCS_LOCK_DETECT_CONFIG6, 0x13), 1278 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1279 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1280 QMP_PHY_INIT_CFG(QPHY_V4_PCS_RX_SIGDET_LVL, 0xaa), 1281 QMP_PHY_INIT_CFG(QPHY_V4_PCS_PCS_TX_RX_CONFIG, 0x0c), 1282 QMP_PHY_INIT_CFG(QPHY_V4_PCS_CDR_RESET_TIME, 0x0a), 1283 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1284 QMP_PHY_INIT_CFG(QPHY_V4_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1285 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG1, 0x4b), 1286 QMP_PHY_INIT_CFG(QPHY_V4_PCS_EQ_CONFIG5, 0x10), 1287 QMP_PHY_INIT_CFG(QPHY_V4_PCS_REFGEN_REQ_CONFIG1, 0x21), 1288 }; 1289 1290 static const struct qmp_phy_init_tbl sm8350_usb3_uniphy_pcs_usb_tbl[] = { 1291 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1292 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1293 }; 1294 1295 static const struct qmp_phy_init_tbl qcm2290_usb3_serdes_tbl[] = { 1296 QMP_PHY_INIT_CFG(QSERDES_COM_SYSCLK_EN_SEL, 0x14), 1297 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CLKBUFLR_EN, 0x08), 1298 QMP_PHY_INIT_CFG(QSERDES_COM_CLK_SELECT, 0x30), 1299 QMP_PHY_INIT_CFG(QSERDES_COM_SYS_CLK_CTRL, 0x06), 1300 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL, 0x00), 1301 QMP_PHY_INIT_CFG(QSERDES_COM_RESETSM_CNTRL2, 0x08), 1302 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TRIM, 0x0f), 1303 QMP_PHY_INIT_CFG(QSERDES_COM_SVS_MODE_CLK_SEL, 0x01), 1304 QMP_PHY_INIT_CFG(QSERDES_COM_HSCLK_SEL, 0x00), 1305 QMP_PHY_INIT_CFG(QSERDES_COM_DEC_START_MODE0, 0x82), 1306 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START1_MODE0, 0x55), 1307 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START2_MODE0, 0x55), 1308 QMP_PHY_INIT_CFG(QSERDES_COM_DIV_FRAC_START3_MODE0, 0x03), 1309 QMP_PHY_INIT_CFG(QSERDES_COM_CP_CTRL_MODE0, 0x0b), 1310 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_RCTRL_MODE0, 0x16), 1311 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_CCTRL_MODE0, 0x28), 1312 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN0_MODE0, 0x80), 1313 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_GAIN1_MODE0, 0x00), 1314 QMP_PHY_INIT_CFG(QSERDES_COM_CORECLK_DIV, 0x0a), 1315 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP1_MODE0, 0x15), 1316 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP2_MODE0, 0x34), 1317 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP3_MODE0, 0x00), 1318 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_EN, 0x00), 1319 QMP_PHY_INIT_CFG(QSERDES_COM_CORE_CLK_EN, 0x00), 1320 QMP_PHY_INIT_CFG(QSERDES_COM_LOCK_CMP_CFG, 0x00), 1321 QMP_PHY_INIT_CFG(QSERDES_COM_VCO_TUNE_MAP, 0x00), 1322 QMP_PHY_INIT_CFG(QSERDES_COM_BG_TIMER, 0x0a), 1323 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_EN_CENTER, 0x01), 1324 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER1, 0x31), 1325 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_PER2, 0x01), 1326 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER1, 0x00), 1327 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_ADJ_PER2, 0x00), 1328 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE1, 0xde), 1329 QMP_PHY_INIT_CFG(QSERDES_COM_SSC_STEP_SIZE2, 0x07), 1330 QMP_PHY_INIT_CFG(QSERDES_COM_PLL_IVCO, 0x0f), 1331 QMP_PHY_INIT_CFG(QSERDES_COM_CMN_CONFIG, 0x06), 1332 QMP_PHY_INIT_CFG(QSERDES_COM_INTEGLOOP_INITVAL, 0x80), 1333 QMP_PHY_INIT_CFG(QSERDES_COM_BIAS_EN_CTRL_BY_PSM, 0x01), 1334 }; 1335 1336 static const struct qmp_phy_init_tbl qcm2290_usb3_tx_tbl[] = { 1337 QMP_PHY_INIT_CFG(QSERDES_V3_TX_HIGHZ_DRVR_EN, 0x10), 1338 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RCV_DETECT_LVL_2, 0x12), 1339 QMP_PHY_INIT_CFG(QSERDES_V3_TX_LANE_MODE_1, 0xc6), 1340 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_TX, 0x00), 1341 QMP_PHY_INIT_CFG(QSERDES_V3_TX_RES_CODE_LANE_OFFSET_RX, 0x00), 1342 }; 1343 1344 static const struct qmp_phy_init_tbl qcm2290_usb3_rx_tbl[] = { 1345 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_FO_GAIN, 0x0b), 1346 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_PI_CONTROLS, 0x80), 1347 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_LOW, 0x00), 1348 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x00), 1349 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_FO_GAIN, 0x0a), 1350 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_GAIN, 0x06), 1351 QMP_PHY_INIT_CFG(QSERDES_V3_RX_UCDR_SO_SATURATION_AND_ENABLE, 0x75), 1352 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL2, 0x02), 1353 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL3, 0x4e), 1354 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQU_ADAPTOR_CNTRL4, 0x18), 1355 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x77), 1356 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1357 QMP_PHY_INIT_CFG(QSERDES_V3_RX_VGA_CAL_CNTRL2, 0x0a), 1358 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_CNTRL, 0x03), 1359 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_DEGLITCH_CNTRL, 0x16), 1360 QMP_PHY_INIT_CFG(QSERDES_V3_RX_SIGDET_ENABLES, 0x00), 1361 QMP_PHY_INIT_CFG(QSERDES_V3_RX_RX_MODE_00, 0x00), 1362 }; 1363 1364 static const struct qmp_phy_init_tbl qcm2290_usb3_pcs_tbl[] = { 1365 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXMGN_V0, 0x9f), 1366 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M6DB_V0, 0x17), 1367 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TXDEEMPH_M3P5DB_V0, 0x0f), 1368 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL2, 0x83), 1369 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNTRL1, 0x02), 1370 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_L, 0x09), 1371 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_CNT_VAL_H_TOL, 0xa2), 1372 QMP_PHY_INIT_CFG(QPHY_V3_PCS_FLL_MAN_CODE, 0x85), 1373 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG1, 0xd1), 1374 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG2, 0x1f), 1375 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LOCK_DETECT_CONFIG3, 0x47), 1376 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_WAIT_TIME, 0x75), 1377 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RXEQTRAINING_RUN_TIME, 0x13), 1378 QMP_PHY_INIT_CFG(QPHY_V3_PCS_LFPS_TX_ECSTART_EQTLOCK, 0x86), 1379 QMP_PHY_INIT_CFG(QPHY_V3_PCS_PWRUP_RESET_DLY_TIME_AUXCLK, 0x04), 1380 QMP_PHY_INIT_CFG(QPHY_V3_PCS_TSYNC_RSYNC_TIME, 0x44), 1381 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1382 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1383 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_L, 0x40), 1384 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RCVR_DTCT_DLY_U3_H, 0x00), 1385 QMP_PHY_INIT_CFG(QPHY_V3_PCS_RX_SIGDET_LVL, 0x88), 1386 }; 1387 1388 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_serdes_tbl[] = { 1389 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_EN_SEL, 0x1a), 1390 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_HSCLK_SEL, 0x11), 1391 QMP_PHY_INIT_CFG(QSERDES_V5_COM_HSCLK_SEL, 0x01), 1392 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE0, 0x82), 1393 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE0, 0xab), 1394 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE0, 0xea), 1395 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE0, 0x02), 1396 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE0, 0xca), 1397 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE0, 0x1e), 1398 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE0, 0x06), 1399 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE0, 0x16), 1400 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE0, 0x36), 1401 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE0, 0x24), 1402 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE0, 0x34), 1403 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE0, 0x14), 1404 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP_EN, 0x04), 1405 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SYSCLK_BUF_ENABLE, 0x0a), 1406 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE2_MODE1, 0x02), 1407 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE1_MODE1, 0x24), 1408 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CORECLK_DIV_MODE1, 0x08), 1409 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DEC_START_MODE1, 0x82), 1410 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START1_MODE1, 0xab), 1411 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START2_MODE1, 0xea), 1412 QMP_PHY_INIT_CFG(QSERDES_V5_COM_DIV_FRAC_START3_MODE1, 0x02), 1413 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP2_MODE1, 0x82), 1414 QMP_PHY_INIT_CFG(QSERDES_V5_COM_LOCK_CMP1_MODE1, 0x34), 1415 QMP_PHY_INIT_CFG(QSERDES_V5_COM_CP_CTRL_MODE1, 0x06), 1416 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_RCTRL_MODE1, 0x16), 1417 QMP_PHY_INIT_CFG(QSERDES_V5_COM_PLL_CCTRL_MODE1, 0x36), 1418 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE1_MODE1, 0xca), 1419 QMP_PHY_INIT_CFG(QSERDES_V5_COM_BIN_VCOCAL_CMP_CODE2_MODE1, 0x1e), 1420 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_EN_CENTER, 0x01), 1421 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER1, 0x31), 1422 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_PER2, 0x01), 1423 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE1, 0xde), 1424 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE1, 0x07), 1425 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE1_MODE0, 0xde), 1426 QMP_PHY_INIT_CFG(QSERDES_V5_COM_SSC_STEP_SIZE2_MODE0, 0x07), 1427 QMP_PHY_INIT_CFG(QSERDES_V5_COM_VCO_TUNE_MAP, 0x02), 1428 }; 1429 1430 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_tx_tbl[] = { 1431 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_1, 0xa5), 1432 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_2, 0x82), 1433 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_3, 0x3f), 1434 QMP_PHY_INIT_CFG(QSERDES_V5_TX_LANE_MODE_4, 0x3f), 1435 QMP_PHY_INIT_CFG(QSERDES_V5_TX_PI_QEC_CTRL, 0x21), 1436 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX, 0x10), 1437 QMP_PHY_INIT_CFG(QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX, 0x0e), 1438 }; 1439 1440 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_rx_tbl[] = { 1441 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH4, 0xdc), 1442 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH3, 0xbd), 1443 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH2, 0xff), 1444 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_HIGH, 0x7f), 1445 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_00_LOW, 0xff), 1446 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH4, 0xa9), 1447 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH3, 0x7b), 1448 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH2, 0xe4), 1449 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_HIGH, 0x24), 1450 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_MODE_01_LOW, 0x64), 1451 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_PI_CONTROLS, 0x99), 1452 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH1, 0x08), 1453 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_THRESH2, 0x08), 1454 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN1, 0x00), 1455 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SB2_GAIN2, 0x04), 1456 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN, 0x2f), 1457 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW, 0xff), 1458 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH, 0x0f), 1459 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x0a), 1460 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL1, 0x54), 1461 QMP_PHY_INIT_CFG(QSERDES_V5_RX_VGA_CAL_CNTRL2, 0x0f), 1462 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2, 0x0f), 1463 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4, 0x0a), 1464 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1, 0x47), 1465 QMP_PHY_INIT_CFG(QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2, 0x80), 1466 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_CNTRL, 0x04), 1467 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL, 0x0e), 1468 QMP_PHY_INIT_CFG(QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET, 0x38), 1469 QMP_PHY_INIT_CFG(QSERDES_V5_RX_UCDR_SO_GAIN, 0x05), 1470 QMP_PHY_INIT_CFG(QSERDES_V5_RX_GM_CAL, 0x00), 1471 QMP_PHY_INIT_CFG(QSERDES_V5_RX_SIGDET_ENABLES, 0x00), 1472 }; 1473 1474 static const struct qmp_phy_init_tbl sc8280xp_usb3_uniphy_pcs_tbl[] = { 1475 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xd0), 1476 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x07), 1477 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1478 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1479 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1480 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1481 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1482 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1483 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1484 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1485 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a), 1486 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1487 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1488 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1489 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1490 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1491 }; 1492 1493 static const struct qmp_phy_init_tbl sa8775p_usb3_uniphy_pcs_tbl[] = { 1494 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG1, 0xc4), 1495 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG2, 0x89), 1496 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG3, 0x20), 1497 QMP_PHY_INIT_CFG(QPHY_V5_PCS_LOCK_DETECT_CONFIG6, 0x13), 1498 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_L, 0xe7), 1499 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RCVR_DTCT_DLY_P1U2_H, 0x03), 1500 QMP_PHY_INIT_CFG(QPHY_V5_PCS_RX_SIGDET_LVL, 0xaa), 1501 QMP_PHY_INIT_CFG(QPHY_V5_PCS_PCS_TX_RX_CONFIG, 0x0c), 1502 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_RXEQTRAINING_DFE_TIME_S2, 0x07), 1503 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_LFPS_DET_HIGH_COUNT_VAL, 0xf8), 1504 QMP_PHY_INIT_CFG(QPHY_V5_PCS_USB3_POWER_STATE_CONFIG1, 0x6f), 1505 QMP_PHY_INIT_CFG(QPHY_V5_PCS_CDR_RESET_TIME, 0x0a), 1506 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG1, 0x88), 1507 QMP_PHY_INIT_CFG(QPHY_V5_PCS_ALIGN_DETECT_CONFIG2, 0x13), 1508 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG1, 0x4b), 1509 QMP_PHY_INIT_CFG(QPHY_V5_PCS_EQ_CONFIG5, 0x10), 1510 QMP_PHY_INIT_CFG(QPHY_V5_PCS_REFGEN_REQ_CONFIG1, 0x21), 1511 }; 1512 1513 struct qmp_usb_offsets { 1514 u16 serdes; 1515 u16 pcs; 1516 u16 pcs_misc; 1517 u16 pcs_usb; 1518 u16 tx; 1519 u16 rx; 1520 /* for PHYs with >= 2 lanes */ 1521 u16 tx2; 1522 u16 rx2; 1523 }; 1524 1525 /* struct qmp_phy_cfg - per-PHY initialization config */ 1526 struct qmp_phy_cfg { 1527 int lanes; 1528 1529 const struct qmp_usb_offsets *offsets; 1530 1531 /* Init sequence for PHY blocks - serdes, tx, rx, pcs */ 1532 const struct qmp_phy_init_tbl *serdes_tbl; 1533 int serdes_tbl_num; 1534 const struct qmp_phy_init_tbl *tx_tbl; 1535 int tx_tbl_num; 1536 const struct qmp_phy_init_tbl *rx_tbl; 1537 int rx_tbl_num; 1538 const struct qmp_phy_init_tbl *pcs_tbl; 1539 int pcs_tbl_num; 1540 const struct qmp_phy_init_tbl *pcs_usb_tbl; 1541 int pcs_usb_tbl_num; 1542 1543 /* clock ids to be requested */ 1544 const char * const *clk_list; 1545 int num_clks; 1546 /* resets to be requested */ 1547 const char * const *reset_list; 1548 int num_resets; 1549 /* regulators to be requested */ 1550 const char * const *vreg_list; 1551 int num_vregs; 1552 1553 /* array of registers with different offsets */ 1554 const unsigned int *regs; 1555 1556 /* true, if PHY needs delay after POWER_DOWN */ 1557 bool has_pwrdn_delay; 1558 1559 /* true, if PHY has a separate DP_COM control block */ 1560 bool has_phy_dp_com_ctrl; 1561 1562 /* Offset from PCS to PCS_USB region */ 1563 unsigned int pcs_usb_offset; 1564 }; 1565 1566 struct qmp_usb { 1567 struct device *dev; 1568 1569 const struct qmp_phy_cfg *cfg; 1570 1571 void __iomem *serdes; 1572 void __iomem *pcs; 1573 void __iomem *pcs_misc; 1574 void __iomem *pcs_usb; 1575 void __iomem *tx; 1576 void __iomem *rx; 1577 void __iomem *tx2; 1578 void __iomem *rx2; 1579 1580 void __iomem *dp_com; 1581 1582 struct clk *pipe_clk; 1583 struct clk_bulk_data *clks; 1584 struct reset_control_bulk_data *resets; 1585 struct regulator_bulk_data *vregs; 1586 1587 enum phy_mode mode; 1588 1589 struct phy *phy; 1590 1591 struct clk_fixed_rate pipe_clk_fixed; 1592 }; 1593 1594 static inline void qphy_setbits(void __iomem *base, u32 offset, u32 val) 1595 { 1596 u32 reg; 1597 1598 reg = readl(base + offset); 1599 reg |= val; 1600 writel(reg, base + offset); 1601 1602 /* ensure that above write is through */ 1603 readl(base + offset); 1604 } 1605 1606 static inline void qphy_clrbits(void __iomem *base, u32 offset, u32 val) 1607 { 1608 u32 reg; 1609 1610 reg = readl(base + offset); 1611 reg &= ~val; 1612 writel(reg, base + offset); 1613 1614 /* ensure that above write is through */ 1615 readl(base + offset); 1616 } 1617 1618 /* list of clocks required by phy */ 1619 static const char * const msm8996_phy_clk_l[] = { 1620 "aux", "cfg_ahb", "ref", 1621 }; 1622 1623 static const char * const qmp_v3_phy_clk_l[] = { 1624 "aux", "cfg_ahb", "ref", "com_aux", 1625 }; 1626 1627 static const char * const qmp_v4_phy_clk_l[] = { 1628 "aux", "ref", "com_aux", 1629 }; 1630 1631 static const char * const qmp_v4_ref_phy_clk_l[] = { 1632 "aux", "ref_clk_src", "ref", "com_aux", 1633 }; 1634 1635 /* the primary usb3 phy on sm8250 doesn't have a ref clock */ 1636 static const char * const qmp_v4_sm8250_usbphy_clk_l[] = { 1637 "aux", "ref_clk_src", "com_aux" 1638 }; 1639 1640 /* usb3 phy on sdx55 doesn't have com_aux clock */ 1641 static const char * const qmp_v4_sdx55_usbphy_clk_l[] = { 1642 "aux", "cfg_ahb", "ref" 1643 }; 1644 1645 static const char * const qcm2290_usb3phy_clk_l[] = { 1646 "cfg_ahb", "ref", "com_aux", 1647 }; 1648 1649 /* list of resets */ 1650 static const char * const msm8996_usb3phy_reset_l[] = { 1651 "phy", "common", 1652 }; 1653 1654 static const char * const sc7180_usb3phy_reset_l[] = { 1655 "phy", 1656 }; 1657 1658 static const char * const qcm2290_usb3phy_reset_l[] = { 1659 "phy_phy", "phy", 1660 }; 1661 1662 /* list of regulators */ 1663 static const char * const qmp_phy_vreg_l[] = { 1664 "vdda-phy", "vdda-pll", 1665 }; 1666 1667 static const struct qmp_usb_offsets qmp_usb_offsets_ipq9574 = { 1668 .serdes = 0, 1669 .pcs = 0x800, 1670 .pcs_usb = 0x800, 1671 .tx = 0x200, 1672 .rx = 0x400, 1673 }; 1674 1675 static const struct qmp_usb_offsets qmp_usb_offsets_v3 = { 1676 .serdes = 0, 1677 .pcs = 0xc00, 1678 .pcs_misc = 0xa00, 1679 .tx = 0x200, 1680 .rx = 0x400, 1681 .tx2 = 0x600, 1682 .rx2 = 0x800, 1683 }; 1684 1685 static const struct qmp_usb_offsets qmp_usb_offsets_v5 = { 1686 .serdes = 0, 1687 .pcs = 0x0200, 1688 .pcs_usb = 0x1200, 1689 .tx = 0x0e00, 1690 .rx = 0x1000, 1691 }; 1692 1693 static const struct qmp_phy_cfg ipq8074_usb3phy_cfg = { 1694 .lanes = 1, 1695 1696 .serdes_tbl = ipq8074_usb3_serdes_tbl, 1697 .serdes_tbl_num = ARRAY_SIZE(ipq8074_usb3_serdes_tbl), 1698 .tx_tbl = msm8996_usb3_tx_tbl, 1699 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1700 .rx_tbl = ipq8074_usb3_rx_tbl, 1701 .rx_tbl_num = ARRAY_SIZE(ipq8074_usb3_rx_tbl), 1702 .pcs_tbl = ipq8074_usb3_pcs_tbl, 1703 .pcs_tbl_num = ARRAY_SIZE(ipq8074_usb3_pcs_tbl), 1704 .clk_list = msm8996_phy_clk_l, 1705 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1706 .reset_list = msm8996_usb3phy_reset_l, 1707 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1708 .vreg_list = qmp_phy_vreg_l, 1709 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1710 .regs = qmp_v3_usb3phy_regs_layout, 1711 }; 1712 1713 static const struct qmp_phy_cfg ipq9574_usb3phy_cfg = { 1714 .lanes = 1, 1715 1716 .offsets = &qmp_usb_offsets_ipq9574, 1717 1718 .serdes_tbl = ipq9574_usb3_serdes_tbl, 1719 .serdes_tbl_num = ARRAY_SIZE(ipq9574_usb3_serdes_tbl), 1720 .tx_tbl = ipq9574_usb3_tx_tbl, 1721 .tx_tbl_num = ARRAY_SIZE(ipq9574_usb3_tx_tbl), 1722 .rx_tbl = ipq9574_usb3_rx_tbl, 1723 .rx_tbl_num = ARRAY_SIZE(ipq9574_usb3_rx_tbl), 1724 .pcs_tbl = ipq9574_usb3_pcs_tbl, 1725 .pcs_tbl_num = ARRAY_SIZE(ipq9574_usb3_pcs_tbl), 1726 .clk_list = msm8996_phy_clk_l, 1727 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1728 .reset_list = qcm2290_usb3phy_reset_l, 1729 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 1730 .vreg_list = qmp_phy_vreg_l, 1731 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1732 .regs = qmp_v3_usb3phy_regs_layout, 1733 }; 1734 1735 static const struct qmp_phy_cfg msm8996_usb3phy_cfg = { 1736 .lanes = 1, 1737 1738 .serdes_tbl = msm8996_usb3_serdes_tbl, 1739 .serdes_tbl_num = ARRAY_SIZE(msm8996_usb3_serdes_tbl), 1740 .tx_tbl = msm8996_usb3_tx_tbl, 1741 .tx_tbl_num = ARRAY_SIZE(msm8996_usb3_tx_tbl), 1742 .rx_tbl = msm8996_usb3_rx_tbl, 1743 .rx_tbl_num = ARRAY_SIZE(msm8996_usb3_rx_tbl), 1744 .pcs_tbl = msm8996_usb3_pcs_tbl, 1745 .pcs_tbl_num = ARRAY_SIZE(msm8996_usb3_pcs_tbl), 1746 .clk_list = msm8996_phy_clk_l, 1747 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1748 .reset_list = msm8996_usb3phy_reset_l, 1749 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1750 .vreg_list = qmp_phy_vreg_l, 1751 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1752 .regs = qmp_v2_usb3phy_regs_layout, 1753 }; 1754 1755 static const struct qmp_phy_cfg qmp_v3_usb3phy_cfg = { 1756 .lanes = 2, 1757 1758 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1759 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1760 .tx_tbl = qmp_v3_usb3_tx_tbl, 1761 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1762 .rx_tbl = qmp_v3_usb3_rx_tbl, 1763 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1764 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1765 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1766 .clk_list = qmp_v3_phy_clk_l, 1767 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1768 .reset_list = msm8996_usb3phy_reset_l, 1769 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1770 .vreg_list = qmp_phy_vreg_l, 1771 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1772 .regs = qmp_v3_usb3phy_regs_layout, 1773 1774 .has_pwrdn_delay = true, 1775 .has_phy_dp_com_ctrl = true, 1776 }; 1777 1778 static const struct qmp_phy_cfg sa8775p_usb3_uniphy_cfg = { 1779 .lanes = 1, 1780 1781 .offsets = &qmp_usb_offsets_v5, 1782 1783 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, 1784 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), 1785 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl, 1786 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl), 1787 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl, 1788 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl), 1789 .pcs_tbl = sa8775p_usb3_uniphy_pcs_tbl, 1790 .pcs_tbl_num = ARRAY_SIZE(sa8775p_usb3_uniphy_pcs_tbl), 1791 .clk_list = qmp_v4_phy_clk_l, 1792 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1793 .reset_list = qcm2290_usb3phy_reset_l, 1794 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 1795 .vreg_list = qmp_phy_vreg_l, 1796 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1797 .regs = qmp_v5_usb3phy_regs_layout, 1798 }; 1799 1800 static const struct qmp_phy_cfg sc7180_usb3phy_cfg = { 1801 .lanes = 2, 1802 1803 .serdes_tbl = qmp_v3_usb3_serdes_tbl, 1804 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_serdes_tbl), 1805 .tx_tbl = qmp_v3_usb3_tx_tbl, 1806 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_tx_tbl), 1807 .rx_tbl = qmp_v3_usb3_rx_tbl, 1808 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_rx_tbl), 1809 .pcs_tbl = qmp_v3_usb3_pcs_tbl, 1810 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_pcs_tbl), 1811 .clk_list = qmp_v3_phy_clk_l, 1812 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1813 .reset_list = sc7180_usb3phy_reset_l, 1814 .num_resets = ARRAY_SIZE(sc7180_usb3phy_reset_l), 1815 .vreg_list = qmp_phy_vreg_l, 1816 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1817 .regs = qmp_v3_usb3phy_regs_layout, 1818 1819 .has_pwrdn_delay = true, 1820 .has_phy_dp_com_ctrl = true, 1821 }; 1822 1823 static const struct qmp_phy_cfg sc8280xp_usb3_uniphy_cfg = { 1824 .lanes = 1, 1825 1826 .offsets = &qmp_usb_offsets_v5, 1827 1828 .serdes_tbl = sc8280xp_usb3_uniphy_serdes_tbl, 1829 .serdes_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_serdes_tbl), 1830 .tx_tbl = sc8280xp_usb3_uniphy_tx_tbl, 1831 .tx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_tx_tbl), 1832 .rx_tbl = sc8280xp_usb3_uniphy_rx_tbl, 1833 .rx_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_rx_tbl), 1834 .pcs_tbl = sc8280xp_usb3_uniphy_pcs_tbl, 1835 .pcs_tbl_num = ARRAY_SIZE(sc8280xp_usb3_uniphy_pcs_tbl), 1836 .clk_list = qmp_v4_phy_clk_l, 1837 .num_clks = ARRAY_SIZE(qmp_v4_phy_clk_l), 1838 .reset_list = qcm2290_usb3phy_reset_l, 1839 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 1840 .vreg_list = qmp_phy_vreg_l, 1841 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1842 .regs = qmp_v5_usb3phy_regs_layout, 1843 }; 1844 1845 static const struct qmp_phy_cfg qmp_v3_usb3_uniphy_cfg = { 1846 .lanes = 1, 1847 1848 .serdes_tbl = qmp_v3_usb3_uniphy_serdes_tbl, 1849 .serdes_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_serdes_tbl), 1850 .tx_tbl = qmp_v3_usb3_uniphy_tx_tbl, 1851 .tx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_tx_tbl), 1852 .rx_tbl = qmp_v3_usb3_uniphy_rx_tbl, 1853 .rx_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_rx_tbl), 1854 .pcs_tbl = qmp_v3_usb3_uniphy_pcs_tbl, 1855 .pcs_tbl_num = ARRAY_SIZE(qmp_v3_usb3_uniphy_pcs_tbl), 1856 .clk_list = qmp_v3_phy_clk_l, 1857 .num_clks = ARRAY_SIZE(qmp_v3_phy_clk_l), 1858 .reset_list = msm8996_usb3phy_reset_l, 1859 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1860 .vreg_list = qmp_phy_vreg_l, 1861 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1862 .regs = qmp_v3_usb3phy_regs_layout, 1863 1864 .has_pwrdn_delay = true, 1865 }; 1866 1867 static const struct qmp_phy_cfg msm8998_usb3phy_cfg = { 1868 .lanes = 2, 1869 1870 .serdes_tbl = msm8998_usb3_serdes_tbl, 1871 .serdes_tbl_num = ARRAY_SIZE(msm8998_usb3_serdes_tbl), 1872 .tx_tbl = msm8998_usb3_tx_tbl, 1873 .tx_tbl_num = ARRAY_SIZE(msm8998_usb3_tx_tbl), 1874 .rx_tbl = msm8998_usb3_rx_tbl, 1875 .rx_tbl_num = ARRAY_SIZE(msm8998_usb3_rx_tbl), 1876 .pcs_tbl = msm8998_usb3_pcs_tbl, 1877 .pcs_tbl_num = ARRAY_SIZE(msm8998_usb3_pcs_tbl), 1878 .clk_list = msm8996_phy_clk_l, 1879 .num_clks = ARRAY_SIZE(msm8996_phy_clk_l), 1880 .reset_list = msm8996_usb3phy_reset_l, 1881 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1882 .vreg_list = qmp_phy_vreg_l, 1883 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1884 .regs = qmp_v3_usb3phy_regs_layout, 1885 }; 1886 1887 static const struct qmp_phy_cfg sm8150_usb3phy_cfg = { 1888 .lanes = 2, 1889 1890 .serdes_tbl = sm8150_usb3_serdes_tbl, 1891 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1892 .tx_tbl = sm8150_usb3_tx_tbl, 1893 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_tx_tbl), 1894 .rx_tbl = sm8150_usb3_rx_tbl, 1895 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_rx_tbl), 1896 .pcs_tbl = sm8150_usb3_pcs_tbl, 1897 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_tbl), 1898 .pcs_usb_tbl = sm8150_usb3_pcs_usb_tbl, 1899 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_pcs_usb_tbl), 1900 .clk_list = qmp_v4_ref_phy_clk_l, 1901 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1902 .reset_list = msm8996_usb3phy_reset_l, 1903 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1904 .vreg_list = qmp_phy_vreg_l, 1905 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1906 .regs = qmp_v4_usb3phy_regs_layout, 1907 .pcs_usb_offset = 0x300, 1908 1909 .has_pwrdn_delay = true, 1910 .has_phy_dp_com_ctrl = true, 1911 }; 1912 1913 static const struct qmp_phy_cfg sm8150_usb3_uniphy_cfg = { 1914 .lanes = 1, 1915 1916 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1917 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1918 .tx_tbl = sm8150_usb3_uniphy_tx_tbl, 1919 .tx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_tx_tbl), 1920 .rx_tbl = sm8150_usb3_uniphy_rx_tbl, 1921 .rx_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_rx_tbl), 1922 .pcs_tbl = sm8150_usb3_uniphy_pcs_tbl, 1923 .pcs_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_tbl), 1924 .pcs_usb_tbl = sm8150_usb3_uniphy_pcs_usb_tbl, 1925 .pcs_usb_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_pcs_usb_tbl), 1926 .clk_list = qmp_v4_ref_phy_clk_l, 1927 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1928 .reset_list = msm8996_usb3phy_reset_l, 1929 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1930 .vreg_list = qmp_phy_vreg_l, 1931 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1932 .regs = qmp_v4_usb3phy_regs_layout, 1933 .pcs_usb_offset = 0x600, 1934 1935 .has_pwrdn_delay = true, 1936 }; 1937 1938 static const struct qmp_phy_cfg sm8250_usb3phy_cfg = { 1939 .lanes = 2, 1940 1941 .serdes_tbl = sm8150_usb3_serdes_tbl, 1942 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 1943 .tx_tbl = sm8250_usb3_tx_tbl, 1944 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_tx_tbl), 1945 .rx_tbl = sm8250_usb3_rx_tbl, 1946 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_rx_tbl), 1947 .pcs_tbl = sm8250_usb3_pcs_tbl, 1948 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_tbl), 1949 .pcs_usb_tbl = sm8250_usb3_pcs_usb_tbl, 1950 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_pcs_usb_tbl), 1951 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 1952 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 1953 .reset_list = msm8996_usb3phy_reset_l, 1954 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1955 .vreg_list = qmp_phy_vreg_l, 1956 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1957 .regs = qmp_v4_usb3phy_regs_layout, 1958 .pcs_usb_offset = 0x300, 1959 1960 .has_pwrdn_delay = true, 1961 .has_phy_dp_com_ctrl = true, 1962 }; 1963 1964 static const struct qmp_phy_cfg sm8250_usb3_uniphy_cfg = { 1965 .lanes = 1, 1966 1967 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1968 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1969 .tx_tbl = sm8250_usb3_uniphy_tx_tbl, 1970 .tx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_tx_tbl), 1971 .rx_tbl = sm8250_usb3_uniphy_rx_tbl, 1972 .rx_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_rx_tbl), 1973 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1974 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 1975 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, 1976 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), 1977 .clk_list = qmp_v4_ref_phy_clk_l, 1978 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 1979 .reset_list = msm8996_usb3phy_reset_l, 1980 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 1981 .vreg_list = qmp_phy_vreg_l, 1982 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 1983 .regs = qmp_v4_usb3phy_regs_layout, 1984 .pcs_usb_offset = 0x600, 1985 1986 .has_pwrdn_delay = true, 1987 }; 1988 1989 static const struct qmp_phy_cfg sdx55_usb3_uniphy_cfg = { 1990 .lanes = 1, 1991 1992 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 1993 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 1994 .tx_tbl = sdx55_usb3_uniphy_tx_tbl, 1995 .tx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_tx_tbl), 1996 .rx_tbl = sdx55_usb3_uniphy_rx_tbl, 1997 .rx_tbl_num = ARRAY_SIZE(sdx55_usb3_uniphy_rx_tbl), 1998 .pcs_tbl = sm8250_usb3_uniphy_pcs_tbl, 1999 .pcs_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_tbl), 2000 .pcs_usb_tbl = sm8250_usb3_uniphy_pcs_usb_tbl, 2001 .pcs_usb_tbl_num = ARRAY_SIZE(sm8250_usb3_uniphy_pcs_usb_tbl), 2002 .clk_list = qmp_v4_sdx55_usbphy_clk_l, 2003 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), 2004 .reset_list = msm8996_usb3phy_reset_l, 2005 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2006 .vreg_list = qmp_phy_vreg_l, 2007 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2008 .regs = qmp_v4_usb3phy_regs_layout, 2009 .pcs_usb_offset = 0x600, 2010 2011 .has_pwrdn_delay = true, 2012 }; 2013 2014 static const struct qmp_phy_cfg sdx65_usb3_uniphy_cfg = { 2015 .lanes = 1, 2016 2017 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 2018 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 2019 .tx_tbl = sdx65_usb3_uniphy_tx_tbl, 2020 .tx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_tx_tbl), 2021 .rx_tbl = sdx65_usb3_uniphy_rx_tbl, 2022 .rx_tbl_num = ARRAY_SIZE(sdx65_usb3_uniphy_rx_tbl), 2023 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 2024 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 2025 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, 2026 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), 2027 .clk_list = qmp_v4_sdx55_usbphy_clk_l, 2028 .num_clks = ARRAY_SIZE(qmp_v4_sdx55_usbphy_clk_l), 2029 .reset_list = msm8996_usb3phy_reset_l, 2030 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2031 .vreg_list = qmp_phy_vreg_l, 2032 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2033 .regs = qmp_v5_usb3phy_regs_layout, 2034 .pcs_usb_offset = 0x1000, 2035 2036 .has_pwrdn_delay = true, 2037 }; 2038 2039 static const struct qmp_phy_cfg sm8350_usb3phy_cfg = { 2040 .lanes = 2, 2041 2042 .serdes_tbl = sm8150_usb3_serdes_tbl, 2043 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_serdes_tbl), 2044 .tx_tbl = sm8350_usb3_tx_tbl, 2045 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_tx_tbl), 2046 .rx_tbl = sm8350_usb3_rx_tbl, 2047 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_rx_tbl), 2048 .pcs_tbl = sm8350_usb3_pcs_tbl, 2049 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_tbl), 2050 .pcs_usb_tbl = sm8350_usb3_pcs_usb_tbl, 2051 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_pcs_usb_tbl), 2052 .clk_list = qmp_v4_sm8250_usbphy_clk_l, 2053 .num_clks = ARRAY_SIZE(qmp_v4_sm8250_usbphy_clk_l), 2054 .reset_list = msm8996_usb3phy_reset_l, 2055 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2056 .vreg_list = qmp_phy_vreg_l, 2057 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2058 .regs = qmp_v5_usb3phy_regs_layout, 2059 .pcs_usb_offset = 0x300, 2060 2061 .has_pwrdn_delay = true, 2062 .has_phy_dp_com_ctrl = true, 2063 }; 2064 2065 static const struct qmp_phy_cfg sm8350_usb3_uniphy_cfg = { 2066 .lanes = 1, 2067 2068 .serdes_tbl = sm8150_usb3_uniphy_serdes_tbl, 2069 .serdes_tbl_num = ARRAY_SIZE(sm8150_usb3_uniphy_serdes_tbl), 2070 .tx_tbl = sm8350_usb3_uniphy_tx_tbl, 2071 .tx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_tx_tbl), 2072 .rx_tbl = sm8350_usb3_uniphy_rx_tbl, 2073 .rx_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_rx_tbl), 2074 .pcs_tbl = sm8350_usb3_uniphy_pcs_tbl, 2075 .pcs_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_tbl), 2076 .pcs_usb_tbl = sm8350_usb3_uniphy_pcs_usb_tbl, 2077 .pcs_usb_tbl_num = ARRAY_SIZE(sm8350_usb3_uniphy_pcs_usb_tbl), 2078 .clk_list = qmp_v4_ref_phy_clk_l, 2079 .num_clks = ARRAY_SIZE(qmp_v4_ref_phy_clk_l), 2080 .reset_list = msm8996_usb3phy_reset_l, 2081 .num_resets = ARRAY_SIZE(msm8996_usb3phy_reset_l), 2082 .vreg_list = qmp_phy_vreg_l, 2083 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2084 .regs = qmp_v5_usb3phy_regs_layout, 2085 .pcs_usb_offset = 0x1000, 2086 2087 .has_pwrdn_delay = true, 2088 }; 2089 2090 static const struct qmp_phy_cfg qcm2290_usb3phy_cfg = { 2091 .lanes = 2, 2092 2093 .offsets = &qmp_usb_offsets_v3, 2094 2095 .serdes_tbl = qcm2290_usb3_serdes_tbl, 2096 .serdes_tbl_num = ARRAY_SIZE(qcm2290_usb3_serdes_tbl), 2097 .tx_tbl = qcm2290_usb3_tx_tbl, 2098 .tx_tbl_num = ARRAY_SIZE(qcm2290_usb3_tx_tbl), 2099 .rx_tbl = qcm2290_usb3_rx_tbl, 2100 .rx_tbl_num = ARRAY_SIZE(qcm2290_usb3_rx_tbl), 2101 .pcs_tbl = qcm2290_usb3_pcs_tbl, 2102 .pcs_tbl_num = ARRAY_SIZE(qcm2290_usb3_pcs_tbl), 2103 .clk_list = qcm2290_usb3phy_clk_l, 2104 .num_clks = ARRAY_SIZE(qcm2290_usb3phy_clk_l), 2105 .reset_list = qcm2290_usb3phy_reset_l, 2106 .num_resets = ARRAY_SIZE(qcm2290_usb3phy_reset_l), 2107 .vreg_list = qmp_phy_vreg_l, 2108 .num_vregs = ARRAY_SIZE(qmp_phy_vreg_l), 2109 .regs = qmp_v3_usb3phy_regs_layout, 2110 }; 2111 2112 static void qmp_usb_configure_lane(void __iomem *base, 2113 const struct qmp_phy_init_tbl tbl[], 2114 int num, 2115 u8 lane_mask) 2116 { 2117 int i; 2118 const struct qmp_phy_init_tbl *t = tbl; 2119 2120 if (!t) 2121 return; 2122 2123 for (i = 0; i < num; i++, t++) { 2124 if (!(t->lane_mask & lane_mask)) 2125 continue; 2126 2127 writel(t->val, base + t->offset); 2128 } 2129 } 2130 2131 static void qmp_usb_configure(void __iomem *base, 2132 const struct qmp_phy_init_tbl tbl[], 2133 int num) 2134 { 2135 qmp_usb_configure_lane(base, tbl, num, 0xff); 2136 } 2137 2138 static int qmp_usb_serdes_init(struct qmp_usb *qmp) 2139 { 2140 const struct qmp_phy_cfg *cfg = qmp->cfg; 2141 void __iomem *serdes = qmp->serdes; 2142 const struct qmp_phy_init_tbl *serdes_tbl = cfg->serdes_tbl; 2143 int serdes_tbl_num = cfg->serdes_tbl_num; 2144 2145 qmp_usb_configure(serdes, serdes_tbl, serdes_tbl_num); 2146 2147 return 0; 2148 } 2149 2150 static int qmp_usb_init(struct phy *phy) 2151 { 2152 struct qmp_usb *qmp = phy_get_drvdata(phy); 2153 const struct qmp_phy_cfg *cfg = qmp->cfg; 2154 void __iomem *pcs = qmp->pcs; 2155 void __iomem *dp_com = qmp->dp_com; 2156 int ret; 2157 2158 ret = regulator_bulk_enable(cfg->num_vregs, qmp->vregs); 2159 if (ret) { 2160 dev_err(qmp->dev, "failed to enable regulators, err=%d\n", ret); 2161 return ret; 2162 } 2163 2164 ret = reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2165 if (ret) { 2166 dev_err(qmp->dev, "reset assert failed\n"); 2167 goto err_disable_regulators; 2168 } 2169 2170 ret = reset_control_bulk_deassert(cfg->num_resets, qmp->resets); 2171 if (ret) { 2172 dev_err(qmp->dev, "reset deassert failed\n"); 2173 goto err_disable_regulators; 2174 } 2175 2176 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2177 if (ret) 2178 goto err_assert_reset; 2179 2180 if (cfg->has_phy_dp_com_ctrl) { 2181 qphy_setbits(dp_com, QPHY_V3_DP_COM_POWER_DOWN_CTRL, 2182 SW_PWRDN); 2183 /* override hardware control for reset of qmp phy */ 2184 qphy_setbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2185 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2186 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2187 2188 /* Default type-c orientation, i.e CC1 */ 2189 qphy_setbits(dp_com, QPHY_V3_DP_COM_TYPEC_CTRL, 0x02); 2190 2191 qphy_setbits(dp_com, QPHY_V3_DP_COM_PHY_MODE_CTRL, 2192 USB3_MODE | DP_MODE); 2193 2194 /* bring both QMP USB and QMP DP PHYs PCS block out of reset */ 2195 qphy_clrbits(dp_com, QPHY_V3_DP_COM_RESET_OVRD_CTRL, 2196 SW_DPPHY_RESET_MUX | SW_DPPHY_RESET | 2197 SW_USB3PHY_RESET_MUX | SW_USB3PHY_RESET); 2198 2199 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SWI_CTRL, 0x03); 2200 qphy_clrbits(dp_com, QPHY_V3_DP_COM_SW_RESET, SW_RESET); 2201 } 2202 2203 qphy_setbits(pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], SW_PWRDN); 2204 2205 return 0; 2206 2207 err_assert_reset: 2208 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2209 err_disable_regulators: 2210 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2211 2212 return ret; 2213 } 2214 2215 static int qmp_usb_exit(struct phy *phy) 2216 { 2217 struct qmp_usb *qmp = phy_get_drvdata(phy); 2218 const struct qmp_phy_cfg *cfg = qmp->cfg; 2219 2220 reset_control_bulk_assert(cfg->num_resets, qmp->resets); 2221 2222 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2223 2224 regulator_bulk_disable(cfg->num_vregs, qmp->vregs); 2225 2226 return 0; 2227 } 2228 2229 static int qmp_usb_power_on(struct phy *phy) 2230 { 2231 struct qmp_usb *qmp = phy_get_drvdata(phy); 2232 const struct qmp_phy_cfg *cfg = qmp->cfg; 2233 void __iomem *tx = qmp->tx; 2234 void __iomem *rx = qmp->rx; 2235 void __iomem *pcs = qmp->pcs; 2236 void __iomem *status; 2237 unsigned int val; 2238 int ret; 2239 2240 qmp_usb_serdes_init(qmp); 2241 2242 ret = clk_prepare_enable(qmp->pipe_clk); 2243 if (ret) { 2244 dev_err(qmp->dev, "pipe_clk enable failed err=%d\n", ret); 2245 return ret; 2246 } 2247 2248 /* Tx, Rx, and PCS configurations */ 2249 qmp_usb_configure_lane(tx, cfg->tx_tbl, cfg->tx_tbl_num, 1); 2250 qmp_usb_configure_lane(rx, cfg->rx_tbl, cfg->rx_tbl_num, 1); 2251 2252 if (cfg->lanes >= 2) { 2253 qmp_usb_configure_lane(qmp->tx2, cfg->tx_tbl, cfg->tx_tbl_num, 2); 2254 qmp_usb_configure_lane(qmp->rx2, cfg->rx_tbl, cfg->rx_tbl_num, 2); 2255 } 2256 2257 qmp_usb_configure(pcs, cfg->pcs_tbl, cfg->pcs_tbl_num); 2258 2259 if (cfg->has_pwrdn_delay) 2260 usleep_range(10, 20); 2261 2262 /* Pull PHY out of reset state */ 2263 qphy_clrbits(pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2264 2265 /* start SerDes and Phy-Coding-Sublayer */ 2266 qphy_setbits(pcs, cfg->regs[QPHY_START_CTRL], SERDES_START | PCS_START); 2267 2268 status = pcs + cfg->regs[QPHY_PCS_STATUS]; 2269 ret = readl_poll_timeout(status, val, !(val & PHYSTATUS), 200, 2270 PHY_INIT_COMPLETE_TIMEOUT); 2271 if (ret) { 2272 dev_err(qmp->dev, "phy initialization timed-out\n"); 2273 goto err_disable_pipe_clk; 2274 } 2275 2276 return 0; 2277 2278 err_disable_pipe_clk: 2279 clk_disable_unprepare(qmp->pipe_clk); 2280 2281 return ret; 2282 } 2283 2284 static int qmp_usb_power_off(struct phy *phy) 2285 { 2286 struct qmp_usb *qmp = phy_get_drvdata(phy); 2287 const struct qmp_phy_cfg *cfg = qmp->cfg; 2288 2289 clk_disable_unprepare(qmp->pipe_clk); 2290 2291 /* PHY reset */ 2292 qphy_setbits(qmp->pcs, cfg->regs[QPHY_SW_RESET], SW_RESET); 2293 2294 /* stop SerDes and Phy-Coding-Sublayer */ 2295 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_START_CTRL], 2296 SERDES_START | PCS_START); 2297 2298 /* Put PHY into POWER DOWN state: active low */ 2299 qphy_clrbits(qmp->pcs, cfg->regs[QPHY_PCS_POWER_DOWN_CONTROL], 2300 SW_PWRDN); 2301 2302 return 0; 2303 } 2304 2305 static int qmp_usb_enable(struct phy *phy) 2306 { 2307 int ret; 2308 2309 ret = qmp_usb_init(phy); 2310 if (ret) 2311 return ret; 2312 2313 ret = qmp_usb_power_on(phy); 2314 if (ret) 2315 qmp_usb_exit(phy); 2316 2317 return ret; 2318 } 2319 2320 static int qmp_usb_disable(struct phy *phy) 2321 { 2322 int ret; 2323 2324 ret = qmp_usb_power_off(phy); 2325 if (ret) 2326 return ret; 2327 return qmp_usb_exit(phy); 2328 } 2329 2330 static int qmp_usb_set_mode(struct phy *phy, enum phy_mode mode, int submode) 2331 { 2332 struct qmp_usb *qmp = phy_get_drvdata(phy); 2333 2334 qmp->mode = mode; 2335 2336 return 0; 2337 } 2338 2339 static const struct phy_ops qmp_usb_phy_ops = { 2340 .init = qmp_usb_enable, 2341 .exit = qmp_usb_disable, 2342 .set_mode = qmp_usb_set_mode, 2343 .owner = THIS_MODULE, 2344 }; 2345 2346 static void qmp_usb_enable_autonomous_mode(struct qmp_usb *qmp) 2347 { 2348 const struct qmp_phy_cfg *cfg = qmp->cfg; 2349 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2350 void __iomem *pcs_misc = qmp->pcs_misc; 2351 u32 intr_mask; 2352 2353 if (qmp->mode == PHY_MODE_USB_HOST_SS || 2354 qmp->mode == PHY_MODE_USB_DEVICE_SS) 2355 intr_mask = ARCVR_DTCT_EN | ALFPS_DTCT_EN; 2356 else 2357 intr_mask = ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL; 2358 2359 /* Clear any pending interrupts status */ 2360 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2361 /* Writing 1 followed by 0 clears the interrupt */ 2362 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2363 2364 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2365 ARCVR_DTCT_EN | ALFPS_DTCT_EN | ARCVR_DTCT_EVENT_SEL); 2366 2367 /* Enable required PHY autonomous mode interrupts */ 2368 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], intr_mask); 2369 2370 /* Enable i/o clamp_n for autonomous mode */ 2371 if (pcs_misc) 2372 qphy_clrbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2373 } 2374 2375 static void qmp_usb_disable_autonomous_mode(struct qmp_usb *qmp) 2376 { 2377 const struct qmp_phy_cfg *cfg = qmp->cfg; 2378 void __iomem *pcs_usb = qmp->pcs_usb ?: qmp->pcs; 2379 void __iomem *pcs_misc = qmp->pcs_misc; 2380 2381 /* Disable i/o clamp_n on resume for normal mode */ 2382 if (pcs_misc) 2383 qphy_setbits(pcs_misc, QPHY_V3_PCS_MISC_CLAMP_ENABLE, CLAMP_EN); 2384 2385 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_AUTONOMOUS_MODE_CTRL], 2386 ARCVR_DTCT_EN | ARCVR_DTCT_EVENT_SEL | ALFPS_DTCT_EN); 2387 2388 qphy_setbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2389 /* Writing 1 followed by 0 clears the interrupt */ 2390 qphy_clrbits(pcs_usb, cfg->regs[QPHY_PCS_LFPS_RXTERM_IRQ_CLEAR], IRQ_CLEAR); 2391 } 2392 2393 static int __maybe_unused qmp_usb_runtime_suspend(struct device *dev) 2394 { 2395 struct qmp_usb *qmp = dev_get_drvdata(dev); 2396 const struct qmp_phy_cfg *cfg = qmp->cfg; 2397 2398 dev_vdbg(dev, "Suspending QMP phy, mode:%d\n", qmp->mode); 2399 2400 if (!qmp->phy->init_count) { 2401 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2402 return 0; 2403 } 2404 2405 qmp_usb_enable_autonomous_mode(qmp); 2406 2407 clk_disable_unprepare(qmp->pipe_clk); 2408 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2409 2410 return 0; 2411 } 2412 2413 static int __maybe_unused qmp_usb_runtime_resume(struct device *dev) 2414 { 2415 struct qmp_usb *qmp = dev_get_drvdata(dev); 2416 const struct qmp_phy_cfg *cfg = qmp->cfg; 2417 int ret = 0; 2418 2419 dev_vdbg(dev, "Resuming QMP phy, mode:%d\n", qmp->mode); 2420 2421 if (!qmp->phy->init_count) { 2422 dev_vdbg(dev, "PHY not initialized, bailing out\n"); 2423 return 0; 2424 } 2425 2426 ret = clk_bulk_prepare_enable(cfg->num_clks, qmp->clks); 2427 if (ret) 2428 return ret; 2429 2430 ret = clk_prepare_enable(qmp->pipe_clk); 2431 if (ret) { 2432 dev_err(dev, "pipe_clk enable failed, err=%d\n", ret); 2433 clk_bulk_disable_unprepare(cfg->num_clks, qmp->clks); 2434 return ret; 2435 } 2436 2437 qmp_usb_disable_autonomous_mode(qmp); 2438 2439 return 0; 2440 } 2441 2442 static const struct dev_pm_ops qmp_usb_pm_ops = { 2443 SET_RUNTIME_PM_OPS(qmp_usb_runtime_suspend, 2444 qmp_usb_runtime_resume, NULL) 2445 }; 2446 2447 static int qmp_usb_vreg_init(struct qmp_usb *qmp) 2448 { 2449 const struct qmp_phy_cfg *cfg = qmp->cfg; 2450 struct device *dev = qmp->dev; 2451 int num = cfg->num_vregs; 2452 int i; 2453 2454 qmp->vregs = devm_kcalloc(dev, num, sizeof(*qmp->vregs), GFP_KERNEL); 2455 if (!qmp->vregs) 2456 return -ENOMEM; 2457 2458 for (i = 0; i < num; i++) 2459 qmp->vregs[i].supply = cfg->vreg_list[i]; 2460 2461 return devm_regulator_bulk_get(dev, num, qmp->vregs); 2462 } 2463 2464 static int qmp_usb_reset_init(struct qmp_usb *qmp) 2465 { 2466 const struct qmp_phy_cfg *cfg = qmp->cfg; 2467 struct device *dev = qmp->dev; 2468 int i; 2469 int ret; 2470 2471 qmp->resets = devm_kcalloc(dev, cfg->num_resets, 2472 sizeof(*qmp->resets), GFP_KERNEL); 2473 if (!qmp->resets) 2474 return -ENOMEM; 2475 2476 for (i = 0; i < cfg->num_resets; i++) 2477 qmp->resets[i].id = cfg->reset_list[i]; 2478 2479 ret = devm_reset_control_bulk_get_exclusive(dev, cfg->num_resets, qmp->resets); 2480 if (ret) 2481 return dev_err_probe(dev, ret, "failed to get resets\n"); 2482 2483 return 0; 2484 } 2485 2486 static int qmp_usb_clk_init(struct qmp_usb *qmp) 2487 { 2488 const struct qmp_phy_cfg *cfg = qmp->cfg; 2489 struct device *dev = qmp->dev; 2490 int num = cfg->num_clks; 2491 int i; 2492 2493 qmp->clks = devm_kcalloc(dev, num, sizeof(*qmp->clks), GFP_KERNEL); 2494 if (!qmp->clks) 2495 return -ENOMEM; 2496 2497 for (i = 0; i < num; i++) 2498 qmp->clks[i].id = cfg->clk_list[i]; 2499 2500 return devm_clk_bulk_get(dev, num, qmp->clks); 2501 } 2502 2503 static void phy_clk_release_provider(void *res) 2504 { 2505 of_clk_del_provider(res); 2506 } 2507 2508 /* 2509 * Register a fixed rate pipe clock. 2510 * 2511 * The <s>_pipe_clksrc generated by PHY goes to the GCC that gate 2512 * controls it. The <s>_pipe_clk coming out of the GCC is requested 2513 * by the PHY driver for its operations. 2514 * We register the <s>_pipe_clksrc here. The gcc driver takes care 2515 * of assigning this <s>_pipe_clksrc as parent to <s>_pipe_clk. 2516 * Below picture shows this relationship. 2517 * 2518 * +---------------+ 2519 * | PHY block |<<---------------------------------------+ 2520 * | | | 2521 * | +-------+ | +-----+ | 2522 * I/P---^-->| PLL |---^--->pipe_clksrc--->| GCC |--->pipe_clk---+ 2523 * clk | +-------+ | +-----+ 2524 * +---------------+ 2525 */ 2526 static int phy_pipe_clk_register(struct qmp_usb *qmp, struct device_node *np) 2527 { 2528 struct clk_fixed_rate *fixed = &qmp->pipe_clk_fixed; 2529 struct clk_init_data init = { }; 2530 int ret; 2531 2532 ret = of_property_read_string(np, "clock-output-names", &init.name); 2533 if (ret) { 2534 dev_err(qmp->dev, "%pOFn: No clock-output-names\n", np); 2535 return ret; 2536 } 2537 2538 init.ops = &clk_fixed_rate_ops; 2539 2540 /* controllers using QMP phys use 125MHz pipe clock interface */ 2541 fixed->fixed_rate = 125000000; 2542 fixed->hw.init = &init; 2543 2544 ret = devm_clk_hw_register(qmp->dev, &fixed->hw); 2545 if (ret) 2546 return ret; 2547 2548 ret = of_clk_add_hw_provider(np, of_clk_hw_simple_get, &fixed->hw); 2549 if (ret) 2550 return ret; 2551 2552 /* 2553 * Roll a devm action because the clock provider is the child node, but 2554 * the child node is not actually a device. 2555 */ 2556 return devm_add_action_or_reset(qmp->dev, phy_clk_release_provider, np); 2557 } 2558 2559 static void __iomem *qmp_usb_iomap(struct device *dev, struct device_node *np, 2560 int index, bool exclusive) 2561 { 2562 struct resource res; 2563 2564 if (!exclusive) { 2565 if (of_address_to_resource(np, index, &res)) 2566 return IOMEM_ERR_PTR(-EINVAL); 2567 2568 return devm_ioremap(dev, res.start, resource_size(&res)); 2569 } 2570 2571 return devm_of_iomap(dev, np, index, NULL); 2572 } 2573 2574 static int qmp_usb_parse_dt_legacy(struct qmp_usb *qmp, struct device_node *np) 2575 { 2576 struct platform_device *pdev = to_platform_device(qmp->dev); 2577 const struct qmp_phy_cfg *cfg = qmp->cfg; 2578 struct device *dev = qmp->dev; 2579 bool exclusive = true; 2580 2581 qmp->serdes = devm_platform_ioremap_resource(pdev, 0); 2582 if (IS_ERR(qmp->serdes)) 2583 return PTR_ERR(qmp->serdes); 2584 2585 if (cfg->has_phy_dp_com_ctrl) { 2586 qmp->dp_com = devm_platform_ioremap_resource(pdev, 1); 2587 if (IS_ERR(qmp->dp_com)) 2588 return PTR_ERR(qmp->dp_com); 2589 } 2590 2591 /* 2592 * FIXME: These bindings should be fixed to not rely on overlapping 2593 * mappings for PCS. 2594 */ 2595 if (of_device_is_compatible(dev->of_node, "qcom,sdx65-qmp-usb3-uni-phy")) 2596 exclusive = false; 2597 if (of_device_is_compatible(dev->of_node, "qcom,sm8350-qmp-usb3-uni-phy")) 2598 exclusive = false; 2599 2600 /* 2601 * Get memory resources for the PHY: 2602 * Resources are indexed as: tx -> 0; rx -> 1; pcs -> 2. 2603 * For dual lane PHYs: tx2 -> 3, rx2 -> 4, pcs_misc (optional) -> 5 2604 * For single lane PHYs: pcs_misc (optional) -> 3. 2605 */ 2606 qmp->tx = devm_of_iomap(dev, np, 0, NULL); 2607 if (IS_ERR(qmp->tx)) 2608 return PTR_ERR(qmp->tx); 2609 2610 qmp->rx = devm_of_iomap(dev, np, 1, NULL); 2611 if (IS_ERR(qmp->rx)) 2612 return PTR_ERR(qmp->rx); 2613 2614 qmp->pcs = qmp_usb_iomap(dev, np, 2, exclusive); 2615 if (IS_ERR(qmp->pcs)) 2616 return PTR_ERR(qmp->pcs); 2617 2618 if (cfg->pcs_usb_offset) 2619 qmp->pcs_usb = qmp->pcs + cfg->pcs_usb_offset; 2620 2621 if (cfg->lanes >= 2) { 2622 qmp->tx2 = devm_of_iomap(dev, np, 3, NULL); 2623 if (IS_ERR(qmp->tx2)) 2624 return PTR_ERR(qmp->tx2); 2625 2626 qmp->rx2 = devm_of_iomap(dev, np, 4, NULL); 2627 if (IS_ERR(qmp->rx2)) 2628 return PTR_ERR(qmp->rx2); 2629 2630 qmp->pcs_misc = devm_of_iomap(dev, np, 5, NULL); 2631 } else { 2632 qmp->pcs_misc = devm_of_iomap(dev, np, 3, NULL); 2633 } 2634 2635 if (IS_ERR(qmp->pcs_misc)) { 2636 dev_vdbg(dev, "PHY pcs_misc-reg not used\n"); 2637 qmp->pcs_misc = NULL; 2638 } 2639 2640 qmp->pipe_clk = devm_get_clk_from_child(dev, np, NULL); 2641 if (IS_ERR(qmp->pipe_clk)) { 2642 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2643 "failed to get pipe clock\n"); 2644 } 2645 2646 return 0; 2647 } 2648 2649 static int qmp_usb_parse_dt(struct qmp_usb *qmp) 2650 { 2651 struct platform_device *pdev = to_platform_device(qmp->dev); 2652 const struct qmp_phy_cfg *cfg = qmp->cfg; 2653 const struct qmp_usb_offsets *offs = cfg->offsets; 2654 struct device *dev = qmp->dev; 2655 void __iomem *base; 2656 2657 if (!offs) 2658 return -EINVAL; 2659 2660 base = devm_platform_ioremap_resource(pdev, 0); 2661 if (IS_ERR(base)) 2662 return PTR_ERR(base); 2663 2664 qmp->serdes = base + offs->serdes; 2665 qmp->pcs = base + offs->pcs; 2666 qmp->pcs_misc = base + offs->pcs_misc; 2667 qmp->pcs_usb = base + offs->pcs_usb; 2668 qmp->tx = base + offs->tx; 2669 qmp->rx = base + offs->rx; 2670 2671 if (cfg->lanes >= 2) { 2672 qmp->tx2 = base + offs->tx2; 2673 qmp->rx2 = base + offs->rx2; 2674 } 2675 2676 qmp->pipe_clk = devm_clk_get(dev, "pipe"); 2677 if (IS_ERR(qmp->pipe_clk)) { 2678 return dev_err_probe(dev, PTR_ERR(qmp->pipe_clk), 2679 "failed to get pipe clock\n"); 2680 } 2681 2682 return 0; 2683 } 2684 2685 static int qmp_usb_probe(struct platform_device *pdev) 2686 { 2687 struct device *dev = &pdev->dev; 2688 struct phy_provider *phy_provider; 2689 struct device_node *np; 2690 struct qmp_usb *qmp; 2691 int ret; 2692 2693 qmp = devm_kzalloc(dev, sizeof(*qmp), GFP_KERNEL); 2694 if (!qmp) 2695 return -ENOMEM; 2696 2697 qmp->dev = dev; 2698 2699 qmp->cfg = of_device_get_match_data(dev); 2700 if (!qmp->cfg) 2701 return -EINVAL; 2702 2703 ret = qmp_usb_clk_init(qmp); 2704 if (ret) 2705 return ret; 2706 2707 ret = qmp_usb_reset_init(qmp); 2708 if (ret) 2709 return ret; 2710 2711 ret = qmp_usb_vreg_init(qmp); 2712 if (ret) 2713 return ret; 2714 2715 /* Check for legacy binding with child node. */ 2716 np = of_get_next_available_child(dev->of_node, NULL); 2717 if (np) { 2718 ret = qmp_usb_parse_dt_legacy(qmp, np); 2719 } else { 2720 np = of_node_get(dev->of_node); 2721 ret = qmp_usb_parse_dt(qmp); 2722 } 2723 if (ret) 2724 goto err_node_put; 2725 2726 pm_runtime_set_active(dev); 2727 ret = devm_pm_runtime_enable(dev); 2728 if (ret) 2729 goto err_node_put; 2730 /* 2731 * Prevent runtime pm from being ON by default. Users can enable 2732 * it using power/control in sysfs. 2733 */ 2734 pm_runtime_forbid(dev); 2735 2736 ret = phy_pipe_clk_register(qmp, np); 2737 if (ret) 2738 goto err_node_put; 2739 2740 qmp->phy = devm_phy_create(dev, np, &qmp_usb_phy_ops); 2741 if (IS_ERR(qmp->phy)) { 2742 ret = PTR_ERR(qmp->phy); 2743 dev_err(dev, "failed to create PHY: %d\n", ret); 2744 goto err_node_put; 2745 } 2746 2747 phy_set_drvdata(qmp->phy, qmp); 2748 2749 of_node_put(np); 2750 2751 phy_provider = devm_of_phy_provider_register(dev, of_phy_simple_xlate); 2752 2753 return PTR_ERR_OR_ZERO(phy_provider); 2754 2755 err_node_put: 2756 of_node_put(np); 2757 return ret; 2758 } 2759 2760 static const struct of_device_id qmp_usb_of_match_table[] = { 2761 { 2762 .compatible = "qcom,ipq6018-qmp-usb3-phy", 2763 .data = &ipq8074_usb3phy_cfg, 2764 }, { 2765 .compatible = "qcom,ipq8074-qmp-usb3-phy", 2766 .data = &ipq8074_usb3phy_cfg, 2767 }, { 2768 .compatible = "qcom,ipq9574-qmp-usb3-phy", 2769 .data = &ipq9574_usb3phy_cfg, 2770 }, { 2771 .compatible = "qcom,msm8996-qmp-usb3-phy", 2772 .data = &msm8996_usb3phy_cfg, 2773 }, { 2774 .compatible = "qcom,msm8998-qmp-usb3-phy", 2775 .data = &msm8998_usb3phy_cfg, 2776 }, { 2777 .compatible = "qcom,qcm2290-qmp-usb3-phy", 2778 .data = &qcm2290_usb3phy_cfg, 2779 }, { 2780 .compatible = "qcom,sa8775p-qmp-usb3-uni-phy", 2781 .data = &sa8775p_usb3_uniphy_cfg, 2782 }, { 2783 .compatible = "qcom,sc7180-qmp-usb3-phy", 2784 .data = &sc7180_usb3phy_cfg, 2785 }, { 2786 .compatible = "qcom,sc8180x-qmp-usb3-phy", 2787 .data = &sm8150_usb3phy_cfg, 2788 }, { 2789 .compatible = "qcom,sc8280xp-qmp-usb3-uni-phy", 2790 .data = &sc8280xp_usb3_uniphy_cfg, 2791 }, { 2792 .compatible = "qcom,sdm845-qmp-usb3-phy", 2793 .data = &qmp_v3_usb3phy_cfg, 2794 }, { 2795 .compatible = "qcom,sdm845-qmp-usb3-uni-phy", 2796 .data = &qmp_v3_usb3_uniphy_cfg, 2797 }, { 2798 .compatible = "qcom,sdx55-qmp-usb3-uni-phy", 2799 .data = &sdx55_usb3_uniphy_cfg, 2800 }, { 2801 .compatible = "qcom,sdx65-qmp-usb3-uni-phy", 2802 .data = &sdx65_usb3_uniphy_cfg, 2803 }, { 2804 .compatible = "qcom,sm6115-qmp-usb3-phy", 2805 .data = &qcm2290_usb3phy_cfg, 2806 }, { 2807 .compatible = "qcom,sm8150-qmp-usb3-phy", 2808 .data = &sm8150_usb3phy_cfg, 2809 }, { 2810 .compatible = "qcom,sm8150-qmp-usb3-uni-phy", 2811 .data = &sm8150_usb3_uniphy_cfg, 2812 }, { 2813 .compatible = "qcom,sm8250-qmp-usb3-phy", 2814 .data = &sm8250_usb3phy_cfg, 2815 }, { 2816 .compatible = "qcom,sm8250-qmp-usb3-uni-phy", 2817 .data = &sm8250_usb3_uniphy_cfg, 2818 }, { 2819 .compatible = "qcom,sm8350-qmp-usb3-phy", 2820 .data = &sm8350_usb3phy_cfg, 2821 }, { 2822 .compatible = "qcom,sm8350-qmp-usb3-uni-phy", 2823 .data = &sm8350_usb3_uniphy_cfg, 2824 }, { 2825 .compatible = "qcom,sm8450-qmp-usb3-phy", 2826 .data = &sm8350_usb3phy_cfg, 2827 }, 2828 { }, 2829 }; 2830 MODULE_DEVICE_TABLE(of, qmp_usb_of_match_table); 2831 2832 static struct platform_driver qmp_usb_driver = { 2833 .probe = qmp_usb_probe, 2834 .driver = { 2835 .name = "qcom-qmp-usb-phy", 2836 .pm = &qmp_usb_pm_ops, 2837 .of_match_table = qmp_usb_of_match_table, 2838 }, 2839 }; 2840 2841 module_platform_driver(qmp_usb_driver); 2842 2843 MODULE_AUTHOR("Vivek Gautam <vivek.gautam@codeaurora.org>"); 2844 MODULE_DESCRIPTION("Qualcomm QMP USB PHY driver"); 2845 MODULE_LICENSE("GPL v2"); 2846