1 /* SPDX-License-Identifier: GPL-2.0 */ 2 /* 3 * Copyright (c) 2017, The Linux Foundation. All rights reserved. 4 */ 5 6 #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_ 7 #define QCOM_PHY_QMP_QSERDES_TXRX_V5_20_H_ 8 9 /* Only for QMP V5_20 PHY - TX registers */ 10 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_TX 0x30 11 #define QSERDES_V5_20_TX_RES_CODE_LANE_OFFSET_RX 0x34 12 #define QSERDES_V5_20_TX_LANE_MODE_1 0x78 13 #define QSERDES_V5_20_TX_LANE_MODE_2 0x7c 14 15 /* Only for QMP V5_20 PHY - RX registers */ 16 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE2 0x008 17 #define QSERDES_V5_20_RX_UCDR_FO_GAIN_RATE3 0x00c 18 #define QSERDES_V5_20_RX_UCDR_PI_CONTROLS 0x020 19 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_0_1 0x02c 20 #define QSERDES_V5_20_RX_AUX_DATA_THRESH_BIN_RATE_2_3 0x030 21 #define QSERDES_V5_20_RX_RX_IDAC_SAOFFSET 0x07c 22 #define QSERDES_V5_20_RX_DFE_3 0x090 23 #define QSERDES_V5_20_RX_DFE_DAC_ENABLE1 0x0b4 24 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH1 0x0c4 25 #define QSERDES_V5_20_RX_TX_ADAPT_POST_THRESH2 0x0c8 26 #define QSERDES_V5_20_RX_VGA_CAL_MAN_VAL 0x0dc 27 #define QSERDES_V5_20_RX_GM_CAL 0x0ec 28 #define QSERDES_V5_20_RX_RX_EQU_ADAPTOR_CNTRL4 0x108 29 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B1 0x164 30 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B2 0x168 31 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B3 0x16c 32 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B5 0x174 33 #define QSERDES_V5_20_RX_RX_MODE_RATE_0_1_B6 0x178 34 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B0 0x17c 35 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B1 0x180 36 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B2 0x184 37 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B3 0x188 38 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B4 0x18c 39 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B5 0x190 40 #define QSERDES_V5_20_RX_RX_MODE_RATE2_B6 0x194 41 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B0 0x198 42 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B1 0x19c 43 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B2 0x1a0 44 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B3 0x1a4 45 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B4 0x1a8 46 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B5 0x1ac 47 #define QSERDES_V5_20_RX_RX_MODE_RATE3_B6 0x1b0 48 #define QSERDES_V5_20_RX_PHPRE_CTRL 0x1b4 49 #define QSERDES_V5_20_RX_DFE_CTLE_POST_CAL_OFFSET 0x1c0 50 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE210 0x1f4 51 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH1_RATE3 0x1f8 52 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE210 0x1fc 53 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH2_RATE3 0x200 54 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE210 0x204 55 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH3_RATE3 0x208 56 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH4_RATE3 0x210 57 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH5_RATE3 0x218 58 #define QSERDES_V5_20_RX_RX_MARG_COARSE_THRESH6_RATE3 0x220 59 60 #endif 61