1*f1f923adSDmitry Baryshkov 2*f1f923adSDmitry Baryshkov /* SPDX-License-Identifier: GPL-2.0 */ 3*f1f923adSDmitry Baryshkov /* 4*f1f923adSDmitry Baryshkov * Copyright (c) 2017, The Linux Foundation. All rights reserved. 5*f1f923adSDmitry Baryshkov */ 6*f1f923adSDmitry Baryshkov 7*f1f923adSDmitry Baryshkov #ifndef QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ 8*f1f923adSDmitry Baryshkov #define QCOM_PHY_QMP_QSERDES_TXRX_V5_H_ 9*f1f923adSDmitry Baryshkov 10*f1f923adSDmitry Baryshkov /* Only for QMP V5 PHY - TX registers */ 11*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_RES_CODE_LANE_TX 0x034 12*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_RES_CODE_LANE_RX 0x038 13*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_TX 0x03c 14*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_RES_CODE_LANE_OFFSET_RX 0x040 15*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_LANE_MODE_1 0x084 16*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_LANE_MODE_2 0x088 17*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_LANE_MODE_3 0x08c 18*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_LANE_MODE_4 0x090 19*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_LANE_MODE_5 0x094 20*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_RCV_DETECT_LVL_2 0x0a4 21*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_TRAN_DRVR_EMP_EN 0x0c0 22*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_PI_QEC_CTRL 0x0e4 23*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_PWM_GEAR_1_DIVIDER_BAND0_1 0x178 24*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_PWM_GEAR_2_DIVIDER_BAND0_1 0x17c 25*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_PWM_GEAR_3_DIVIDER_BAND0_1 0x180 26*f1f923adSDmitry Baryshkov #define QSERDES_V5_TX_PWM_GEAR_4_DIVIDER_BAND0_1 0x184 27*f1f923adSDmitry Baryshkov 28*f1f923adSDmitry Baryshkov /* Only for QMP V5 PHY - RX registers */ 29*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_UCDR_FO_GAIN 0x008 30*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_UCDR_SO_GAIN 0x014 31*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_UCDR_FASTLOCK_FO_GAIN 0x030 32*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_UCDR_SO_SATURATION_AND_ENABLE 0x034 33*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_LOW 0x03c 34*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_UCDR_FASTLOCK_COUNT_HIGH 0x040 35*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_UCDR_PI_CONTROLS 0x044 36*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_UCDR_PI_CTRL2 0x048 37*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_UCDR_SB2_THRESH1 0x04c 38*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_UCDR_SB2_THRESH2 0x050 39*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_UCDR_SB2_GAIN1 0x054 40*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_UCDR_SB2_GAIN2 0x058 41*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_AUX_DATA_TCOARSE_TFINE 0x060 42*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RCLK_AUXDATA_SEL 0x064 43*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_AC_JTAG_ENABLE 0x068 44*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_AC_JTAG_MODE 0x078 45*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_TERM_BW 0x080 46*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_TX_ADAPT_POST_THRESH 0x0cc 47*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_VGA_CAL_CNTRL1 0x0d4 48*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_VGA_CAL_CNTRL2 0x0d8 49*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_GM_CAL 0x0dc 50*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL1 0x0e8 51*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL2 0x0ec 52*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL3 0x0f0 53*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_EQU_ADAPTOR_CNTRL4 0x0f4 54*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_IDAC_TSETTLE_LOW 0x0f8 55*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_IDAC_TSETTLE_HIGH 0x0fc 56*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_IDAC_MEASURE_TIME 0x100 57*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_EQ_OFFSET_ADAPTOR_CNTRL1 0x110 58*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_OFFSET_ADAPTOR_CNTRL2 0x114 59*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_SIGDET_ENABLES 0x118 60*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_SIGDET_CNTRL 0x11c 61*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_SIGDET_LVL 0x120 62*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_SIGDET_DEGLITCH_CNTRL 0x124 63*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_BAND 0x128 64*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_00_LOW 0x15c 65*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_00_HIGH 0x160 66*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_00_HIGH2 0x164 67*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_00_HIGH3 0x168 68*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_00_HIGH4 0x16c 69*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_01_LOW 0x170 70*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_01_HIGH 0x174 71*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_01_HIGH2 0x178 72*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_01_HIGH3 0x17c 73*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_01_HIGH4 0x180 74*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_10_LOW 0x184 75*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_10_HIGH 0x188 76*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_10_HIGH2 0x18c 77*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_10_HIGH3 0x190 78*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_RX_MODE_10_HIGH4 0x194 79*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_DFE_EN_TIMER 0x1a0 80*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_DFE_CTLE_POST_CAL_OFFSET 0x1a4 81*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_DCC_CTRL1 0x1a8 82*f1f923adSDmitry Baryshkov #define QSERDES_V5_RX_VTH_CODE 0x1b0 83*f1f923adSDmitry Baryshkov 84*f1f923adSDmitry Baryshkov #endif 85